net: hns3: add 5ms delay before clear firmware reset irq source

[ Upstream commit 0770063096d5da4a8e467b6e73c1646a75589628 ]

Currently the reset process in hns3 and firmware watchdog init process is
asynchronous. we think firmware watchdog initialization is completed
before hns3 clear the firmware interrupt source. However, firmware
initialization may not complete early.

so we add delay before hns3 clear firmware interrupt source and 5 ms delay
is enough to avoid second firmware reset interrupt.

Fixes: c1a81619d73a ("net: hns3: Add mailbox interrupt handling to PF driver")
Signed-off-by: Jie Wang <wangjie125@huawei.com>
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index e44c507..3e1d202 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3662,9 +3662,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
                                    u32 regclr)
 {
+#define HCLGE_IMP_RESET_DELAY          5
+
        switch (event_type) {
        case HCLGE_VECTOR0_EVENT_PTP:
        case HCLGE_VECTOR0_EVENT_RST:
+               if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
+                       mdelay(HCLGE_IMP_RESET_DELAY);
+
                hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
                break;
        case HCLGE_VECTOR0_EVENT_MBX: