drm/amdgpu/gfx10: add gfx config for navi12

got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE

v2: squash all navi asics together because the
settings are the same.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d8d60d7..9dd12f6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1095,18 +1095,12 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
-               adev->gfx.config.max_hw_contexts = 8;
-               adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-               adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-               adev->gfx.config.sc_hiz_tile_fifo_size = 0;
-               adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
-               gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
-               break;
        case CHIP_NAVI14:
+       case CHIP_NAVI12:
                adev->gfx.config.max_hw_contexts = 8;
                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-               adev->gfx.config.sc_hiz_tile_fifo_size = 0x0;
+               adev->gfx.config.sc_hiz_tile_fifo_size = 0;
                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
                gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
                break;