Fix mx31_decode_pll

The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 8873fb7..3a35bfa 100644 (file)
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
@@ -30,16 +31,17 @@
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
        u32 mfi = GET_PLL_MFI(reg);
-       u32 mfn = GET_PLL_MFN(reg);
+       s32 mfn = GET_PLL_MFN(reg);
        u32 mfd = GET_PLL_MFD(reg);
        u32 pd =  GET_PLL_PD(reg);
 
        mfi = mfi <= 5 ? 5 : mfi;
+       mfn = mfn >= 512 ? mfn - 1024 : mfn;
        mfd += 1;
        pd += 1;
 
-       return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-               (mfd * pd)) << 10;
+       return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+               mfd * pd);
 }
 
 static u32 mx31_get_mpl_dpdgck_clk(void)