+2014-12-04 Tobias Burnus <burnus@net-b.de>
+
+ * configure.ac: Permit also ISL 0.14 with CLooG.
+ * Makefile.def: Make more dependent on mpfr, mpc, isl, and cloog.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
// Host modules specific to gcc.
dependencies = { module=configure-gcc; on=configure-intl; };
dependencies = { module=configure-gcc; on=all-gmp; };
+dependencies = { module=configure-gcc; on=all-mpfr; };
+dependencies = { module=configure-gcc; on=all-mpc; };
+dependencies = { module=configure-gcc; on=all-isl; };
+dependencies = { module=configure-gcc; on=all-cloog; };
dependencies = { module=configure-gcc; on=all-lto-plugin; };
dependencies = { module=configure-gcc; on=all-binutils; };
dependencies = { module=configure-gcc; on=all-gas; };
configure-stage4-gcc: maybe-all-stage4-gmp
configure-stageprofile-gcc: maybe-all-stageprofile-gmp
configure-stagefeedback-gcc: maybe-all-stagefeedback-gmp
+configure-gcc: maybe-all-mpfr
+
+configure-stage1-gcc: maybe-all-stage1-mpfr
+configure-stage2-gcc: maybe-all-stage2-mpfr
+configure-stage3-gcc: maybe-all-stage3-mpfr
+configure-stage4-gcc: maybe-all-stage4-mpfr
+configure-stageprofile-gcc: maybe-all-stageprofile-mpfr
+configure-stagefeedback-gcc: maybe-all-stagefeedback-mpfr
+configure-gcc: maybe-all-mpc
+
+configure-stage1-gcc: maybe-all-stage1-mpc
+configure-stage2-gcc: maybe-all-stage2-mpc
+configure-stage3-gcc: maybe-all-stage3-mpc
+configure-stage4-gcc: maybe-all-stage4-mpc
+configure-stageprofile-gcc: maybe-all-stageprofile-mpc
+configure-stagefeedback-gcc: maybe-all-stagefeedback-mpc
+configure-gcc: maybe-all-isl
+
+configure-stage1-gcc: maybe-all-stage1-isl
+configure-stage2-gcc: maybe-all-stage2-isl
+configure-stage3-gcc: maybe-all-stage3-isl
+configure-stage4-gcc: maybe-all-stage4-isl
+configure-stageprofile-gcc: maybe-all-stageprofile-isl
+configure-stagefeedback-gcc: maybe-all-stagefeedback-isl
+configure-gcc: maybe-all-cloog
+
+configure-stage1-gcc: maybe-all-stage1-cloog
+configure-stage2-gcc: maybe-all-stage2-cloog
+configure-stage3-gcc: maybe-all-stage3-cloog
+configure-stage4-gcc: maybe-all-stage4-cloog
+configure-stageprofile-gcc: maybe-all-stageprofile-cloog
+configure-stagefeedback-gcc: maybe-all-stagefeedback-cloog
configure-gcc: maybe-all-lto-plugin
configure-stage1-gcc: maybe-all-stage1-lto-plugin
fi
+ if test "${gcc_cv_isl}" = no ; then
+
+ if test "${ENABLE_ISL_CHECK}" = yes ; then
+ _isl_saved_CFLAGS=$CFLAGS
+ _isl_saved_LDFLAGS=$LDFLAGS
+ _isl_saved_LIBS=$LIBS
+
+ CFLAGS="${_isl_saved_CFLAGS} ${islinc} ${gmpinc}"
+ LDFLAGS="${_isl_saved_LDFLAGS} ${isllibs}"
+ LIBS="${_isl_saved_LIBS} -lisl"
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.14 of ISL" >&5
+$as_echo_n "checking for version 0.14 of ISL... " >&6; }
+ if test "$cross_compiling" = yes; then :
+ gcc_cv_isl=yes
+else
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include <isl/version.h>
+ #include <string.h>
+int
+main ()
+{
+if (strncmp (isl_version (), "isl-0.14", strlen ("isl-0.14")) != 0)
+ return 1;
+
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_run "$LINENO"; then :
+ gcc_cv_isl=yes
+else
+ gcc_cv_isl=no
+fi
+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
+ conftest.$ac_objext conftest.beam conftest.$ac_ext
+fi
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_isl" >&5
+$as_echo "$gcc_cv_isl" >&6; }
+
+ CFLAGS=$_isl_saved_CFLAGS
+ LDFLAGS=$_isl_saved_LDFLAGS
+ LIBS=$_isl_saved_LIBS
+ fi
+
+
+ fi
fi
fi
ISL_CHECK_VERSION(0,11)
if test "${gcc_cv_isl}" = no ; then
ISL_CHECK_VERSION(0,12)
+ if test "${gcc_cv_isl}" = no ; then
+ ISL_CHECK_VERSION(0,14)
+ fi
fi
fi
dnl Only execute fail-action, if ISL has been requested.
+2014-12-04 Tobias Burnus <burnus@net-b.de>
+
+ * configure.ac
+ (ac_has_isl_schedule_constraints_compute_schedule):
+ New check.
+ * graphite-clast-to-gimple.c: For ISL 0.14, include deprecate headers.
+ * graphite-interchange.c: Ditto.
+ * graphite-poly.c: Ditto.
+ * graphite-sese-to-poly.c: Ditto.
+ * graphite-optimize-isl.c (getScheduleForBandList): Ditto.
+ Conditionally use ISL 0.13+ functions.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2014-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/56493
+ * convert.c (convert_to_real, convert_to_expr, convert_to_complex):
+ Handle COMPOUND_EXPR.
+
+2014-12-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/59708
+ * expmed.c (expand_widening_mult): Return const0_rtx if
+ coeff is 0.
+
+2014-12-03 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/64153
+ * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Check
+ type sizes before view_converting.
+
+2014-12-03 Shanyao Chen <chenshanyao@huawei.com>
+
+ Backport from mainline
+ 2014-11-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ PR target/59593
+ * config/arm/arm.md (*movhi_insn): Use right formatting
+ for immediate.
+
+ 2014-11-19 Felix Yang <felix.yang@huawei.com>
+ Shanyao Chen <chenshanyao@huawei.com>
+
+ PR target/59593
+ * config/arm/arm.md (define_attr "arch"): Add v6t2.
+ (define_attr "arch_enabled"): Add test for the above.
+ (*movhi_insn_arch4): Add new alternative.
+
+2014-12-03 Renlin Li <Renlin.Li@arm.com>
+
+ Backported from mainline
+ 2014-12-03 Renlin Li <Renlin.Li@arm.com>
+
+ PR middle-end/63762
+ PR target/63661
+ * ira.c (ira): Update preferred class.
+
+2014-12-02 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/64113
+ * config/alpha/alpha.md (call_value_osf_tlsgd): Do not split insn
+ using post-reload splitter. Use peephole2 pass instead.
+ (call_value_osf_tlsldm): Ditto.
+ (TLS_CALL): New int iterator.
+ (tls): New int attribute.
+ (call_value_osf_<tls>): Merge insn pattern from call_value_osf_tlsgd
+ and call_value_tlsldm using TLS_CALL int iterator.
+
+2014-12-02 Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
+
+ PR target/64115
+ * config/rs6000/rs6000.c (rs6000_delegitimize_address): Remove
+ invalid UNSPEC_TOCREL sanity check under ENABLE_CHECKING.
+
+2014-12-01 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/64111
+ * tree.c (int_cst_hash_hash): Use TYPE_UID instead of
+ htab_hash_pointer to not break PCH.
+
+2014-12-01 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/63551
+ * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Convert
+ value of the argument to the type of the value in the condition.
+
+2014-11-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2014-11-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/64067
+ * expr.c (expand_expr_addr_expr_1) <case COMPOUND_LITERAL_EXPR>:
+ Handle it by returning address of COMPOUND_LITERAL_EXPR_DECL
+ not only if modifier is EXPAND_INITIALIZER, but whenever
+ COMPOUND_LITERAL_EXPR_DECL is non-NULL and TREE_STATIC.
+
+ 2014-11-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/63915
+ * tree-vect-stmts.c (vectorizable_simd_clone_call): Pass
+ true instead of false as last argument to gsi_replace.
+
+ PR sanitizer/63913
+ * ubsan.c: Include tree-eh.h.
+ (instrument_bool_enum_load): Handle loads that can throw.
+
+ 2014-10-31 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/63659
+ * ree.c (update_reg_equal_equiv_notes): New function.
+ (combine_set_extension, transform_ifelse): Use it.
+
+2014-11-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ Backport from mainline.
+ 2014-11-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ * config/arm/t-aprofile (MULTILIB_MATCHES): New entry for
+ -march=armv8-a+crc.
+
+2014-11-26 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/63738
+ * tree-data-ref.c (split_constant_offset_1): Do not follow
+ SSA edges for SSA names with SSA_NAME_OCCURS_IN_ABNORMAL_PHI.
+
+2014-11-26 Richard Biener <rguenther@suse.de>
+
+ Backport from mainline
+ 2014-11-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/62238
+ * tree-predcom.c (ref_at_iteration): Unshare the expression
+ before gimplifying it.
+
+ 2014-11-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/61927
+ * tree-vect-loop.c (vect_analyze_loop_2): Revert ordering
+ of group and pattern analysis to the one in GCC 4.8.
+
+ 2014-11-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/63605
+ * fold-const.c (fold_binary_loc): Properly use element_precision
+ for types that may not be scalar.
+
+ 2014-10-28 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/63665
+ * fold-const.c (fold_comparison): Properly guard simplifying
+ against INT_MAX/INT_MIN with !TYPE_OVERFLOW_WRAPS.
+
+2014-11-25 Rohit <rohitarulraj@freescale.com>
+
+ PR bootstrap/63703
+ * config/rs6000/darwin.h (REGISTER_NAMES): Update based on 32 newly
+ added GCC hard register numbers for SPE high registers.
+
+2014-11-23 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline
+ 2014-11-23 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/53976
+ * config/sh/sh_optimize_sett_clrt.cc
+ (sh_optimize_sett_clrt::find_last_ccreg_values): Return bool instead
+ of void. Abort at complex edges.
+ (sh_optimize_sett_clrt::execute): Do nothing if find_last_ccreg_values
+ returned false.
+
+2014-11-22 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline
+ 2014-11-22 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/63783
+ PR target/51244
+ * config/sh/sh_treg_combine.cc (sh_treg_combine::make_not_reg_insn):
+ Do not emit bitwise not insn. Emit logical not insn sequence instead.
+ Adjust related comments throughout the file.
+
+2014-11-22 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline
+ 2014-11-20 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/60111
+ * config/sh/sh.c: Use signed char for signed field.
+
+2014-11-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ PR target/63673
+ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Allow
+ the base pointer of vec_vsx_ld and vec_vsx_st to take a pointer to
+ double.
+
+2014-11-21 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/61750
+ * tree-ssa-forwprop.c (simplify_vce): Verify type sizes
+ match for the resulting VIEW_CONVERT_EXPR.
+
+2014-11-19 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/63947
+ * config/i386/i386.c (put_condition_code) <case LTU, case GEU>:
+ Output "b" and "nb" suffix for FP mode.
+
+2014-11-19 Tom de Vries <tom@codesourcery.com>
+
+ Backport from mainline
+ PR tree-optimization/62167
+ * tree-ssa-tail-merge.c (stmt_local_def): Handle statements with vuse
+ conservatively.
+ (gimple_equal_p): Don't use vn_valueize to compare for lhs equality of
+ assigns.
+
+2014-11-16 Eric Botcazou <ebotcazou@adacore.com>
+
+ * doc/tm.texi.in (TARGET_FLAGS_REGNUM): Move around.
+ * doc/tm.texi: Regenerate.
+
+2014-11-14 Felix Yang <felix.yang@huawei.com>
+
+ Backport from mainline
+ 2014-11-14 Felix Yang <felix.yang@huawei.com>
+ Jiji Jiang <jiangjiji@huawei.com>
+
+ * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): Use
+ VALL mode iterator instead of VALLDI.
+
+2014-11-13 Teresa Johnson <tejohnson@google.com>
+
+ PR tree-optimization/63841
+ * tree-ssa-strlen.c (strlen_optimize_stmt): Ignore clobbers.
+
+2014-11-13 Christophe Lyon <christophe.lyon@linaro.org>
+
+ Backport from mainline
+ 2014-11-02 Michael Collison <michael.collison@linaro.org>
+
+ * config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update
+ to support vector modes.
+ (CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
+
+2014-11-13 Eric Botcazou <ebotcazou@adacore.com>
+
+ * doc/tm.texi.in (SELECT_CC_MODE): Update example.
+ (REVERSIBLE_CC_MODE): Fix example.
+ (REVERSE_CONDITION): Fix typo.
+ * doc/tm.texi: Regenerate.
+
+2014-11-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR ipa/63838
+ * ipa-pure-const.c (propagate_nothrow): Walk w->indirect_calls
+ chain instead of node->indirect_calls.
+
+2014-11-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR target/61535
+ * config/sparc/sparc.c (function_arg_vector_value): Deal with vectors
+ smaller than 8 bytes.
+ (sparc_function_arg_1): Tweak.
+ (sparc_function_value_1): Tweak.
+
+2014-11-08 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/arm/arm.c (arm_set_return_address): Mark the store as frame
+ related, if any.
+ (thumb_set_return_address): Likewise.
+
+2014-11-07 Daniel Hellstrom <daniel@gaisler.com>
+
+ * config.gcc (sparc-*-rtems*): Clean away unused t-elf.
+ * config/sparc/t-rtems: Add leon3v7 and muser-mode multilibs.
+
+2014-11-07 Marek Polacek <polacek@redhat.com>
+
+ Backported from mainline
+ 2014-10-23 Marek Polacek <polacek@redhat.com>
+
+ * c-ubsan.c (ubsan_instrument_shift): Perform the MINUS_EXPR
+ in unsigned type.
+
+2014-11-06 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.md (trap): New insn. Add "trap" to attribute type.
+ Don't allow trap insn in in_branch_delay, in_nullified_branch_delay
+ or in_call_delay.
+
+2014-11-06 Daniel Hellstrom <daniel@gaisler.com>
+
+ * config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor.
+ * doc/invoke.texi (SPARC options): Add mcpu=leon3v7 comment.
+ * config/sparc/leon.md (leon3_load, leon_store, leon_fp_*): Handle
+ leon3v7 as leon3.
+ * config/sparc/sparc-opts.h (enum processor_type): Add LEON3V7.
+ * config/sparc/sparc.c (sparc_option_override): Add leon3v7 support.
+ * config/sparc/sparc.h (TARGET_CPU_leon3v7): New define.
+ * config/sparc/sparc.md (cpu): Add leon3v7.
+ * config/sparc/sparc.opt (enum processor_type): Add leon3v7.
+
+2014-11-05 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/63538
+ * config/i386/i386.c (in_large_data_p): Reject automatic variables.
+ (ix86_encode_section_info): Do not check for non-automatic varibles
+ when setting SYMBOL_FLAG_FAR_ADDR flag.
+ (x86_64_elf_select_section): Do not check ix86_cmodel here.
+ (x86_64_elf_unique_section): Ditto.
+ (x86_elf_aligned_common): Emit tab before .largecomm.
+
+2014-11-05 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline:
+ 2014-10-20 Uros Bizjak <ubizjak@gmail.com>
+
+ * varasm.c (const_alias_set): Remove.
+ (init_varasm_once): Remove initialization of const_alias_set.
+ (build_constant_desc): Do not set alias set to const_alias_set.
+
+ Backport from mainline:
+ 2014-10-14 Uros Bizjak <ubizjak@gmail.com>
+
+ PR rtl-optimization/63475
+ * alias.c (true_dependence_1): Always use get_addr to extract
+ true address operands from x_addr and mem_addr. Use extracted
+ address operands to check for references with alignment ANDs.
+ Use extracted address operands with find_base_term and
+ base_alias_check. For noncanonicalized operands call canon_rtx with
+ extracted address operand.
+ (write_dependence_1): Ditto.
+ (may_alias_p): Ditto. Remove unused calls to canon_rtx.
+
+ Backport from mainline:
+ 2014-10-10 Uros Bizjak <ubizjak@gmail.com>
+
+ PR rtl-optimization/63483
+ * alias.c (true_dependence_1): Do not exit early for MEM_READONLY_P
+ references when alignment ANDs are involved.
+ (write_dependence_p): Ditto.
+ (may_alias_p): Ditto.
+
+2014-10-31 DJ Delorie <dj@redhat.com>
+
+ * expmed.c (strict_volatile_bitfield_p): Fix off-by-one error.
+
2014-10-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-elf-raw.h (CA53_ERR_835769_SPEC): Define.
Backport from mainline
2014-06-24 Max Ostapenko <m.ostapenko@partner.samsung.com>
- * asan.c (instrument_strlen_call): Do not instrument first byte in strlen
- if already instrumented.
+ * asan.c (instrument_strlen_call): Do not instrument first byte in
+ strlen if already instrumented.
2014-10-16 Yury Gribov <y.gribov@samsung.com>
+2014-11-24 Eric Botcazou <ebotcazou@adacore.com>
+
+ * gcc-interface/trans.c (push_range_check_info): Replace early test
+ with assertion.
+ (Raise_Error_to_gnu): Do not call push_range_check_info if the loop
+ stack is empty.
+ * gcc-interface/utils.c (convert_to_fat_pointer): Fix formatting.
+ * gcc-interface/utils2.c (gnat_invariant_expr): Deal with padded types
+ and revert latest change.
+
+2014-11-22 Eric Botcazou <ebotcazou@adacore.com>
+
+ Backport from mainline
+ 2014-11-20 Vincent Celier <celier@adacore.com>
+
+ PR ada/47500
+ * back_end.adb (Scan_Back_End_Switches): Skip switch -G and
+ its argument.
+
+2014-11-11 Simon Wright <simon@pushface.org>
+
+ PR ada/42978
+ * mlib-utl.adb (ar): Output the options passed to ranlib.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
Last : constant Natural := Switch_Last (Switch_Chars);
begin
- -- Skip -o or internal GCC switches together with their argument
+ -- Skip -o, -G or internal GCC switches together with their argument.
if Switch_Chars (First .. Last) = "o"
+ or else Switch_Chars (First .. Last) = "G"
or else Is_Internal_GCC_Switch (Switch_Chars)
then
Next_Arg := Next_Arg + 1;
struct loop_info_d *iter = NULL;
unsigned int i;
- if (vec_safe_is_empty (gnu_loop_stack))
- return NULL;
-
var = remove_conversions (var, false);
if (TREE_CODE (var) != VAR_DECL)
if (decl_function_context (var) != current_function_decl)
return NULL;
+ gcc_assert (vec_safe_length (gnu_loop_stack) > 0);
+
for (i = vec_safe_length (gnu_loop_stack) - 1;
vec_safe_iterate (gnu_loop_stack, i, &iter);
i--)
the original checks reinstated, and a run time selection.
The former loop will be suitable for vectorization. */
if (flag_unswitch_loops
+ && !vec_safe_is_empty (gnu_loop_stack)
&& (!gnu_low_bound
|| (gnu_low_bound = gnat_invariant_expr (gnu_low_bound)))
&& (!gnu_high_bound
{
/* The template type can still be dummy at this point so we build an
empty constructor. The middle-end will fill it in with zeros. */
- t = build_constructor (template_type,
- NULL);
+ t = build_constructor (template_type, NULL);
TREE_CONSTANT (t) = TREE_STATIC (t) = 1;
null_bounds = build_unary_op (ADDR_EXPR, NULL_TREE, t);
SET_TYPE_NULL_BOUNDS (ptr_template_type, null_bounds);
|| (TREE_CODE (expr) == VAR_DECL && TREE_READONLY (expr)))
&& decl_function_context (expr) == current_function_decl
&& DECL_INITIAL (expr))
- expr = remove_conversions (DECL_INITIAL (expr), false);
+ {
+ expr = DECL_INITIAL (expr);
+ /* Look into CONSTRUCTORs built to initialize padded types. */
+ if (TYPE_IS_PADDING_P (TREE_TYPE (expr)))
+ expr = convert (TREE_TYPE (TYPE_FIELDS (TREE_TYPE (expr))), expr);
+ expr = remove_conversions (expr, false);
+ }
if (TREE_CONSTANT (expr))
return fold_convert (type, expr);
if (!TREE_READONLY (t))
return NULL_TREE;
- if (TREE_CODE (t) == CONSTRUCTOR || TREE_CODE (t) == PARM_DECL)
+ if (TREE_CODE (t) == PARM_DECL)
return fold_convert (type, expr);
if (TREE_CODE (t) == VAR_DECL
if not Opt.Quiet_Output then
Write_Str (Ranlib_Name.all);
Write_Char (' ');
+ for J in Ranlib_Options'Range loop
+ Write_Str (Ranlib_Options (J).all);
+ Write_Char (' ');
+ end loop;
Write_Line (Arguments (Ar_Options'Length + 1).all);
end if;
true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr,
const_rtx x, rtx x_addr, bool mem_canonicalized)
{
+ rtx true_mem_addr;
rtx base;
int ret;
|| MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
return 1;
- /* Read-only memory is by definition never modified, and therefore can't
- conflict with anything. We don't expect to find read-only set on MEM,
- but stupid user tricks can produce them, so don't die. */
- if (MEM_READONLY_P (x))
- return 0;
-
- /* If we have MEMs referring to different address spaces (which can
- potentially overlap), we cannot easily tell from the addresses
- whether the references overlap. */
- if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
- return 1;
+ if (! x_addr)
+ x_addr = XEXP (x, 0);
+ x_addr = get_addr (x_addr);
if (! mem_addr)
{
if (mem_mode == VOIDmode)
mem_mode = GET_MODE (mem);
}
+ true_mem_addr = get_addr (mem_addr);
- if (! x_addr)
- {
- x_addr = XEXP (x, 0);
- if (!((GET_CODE (x_addr) == VALUE
- && GET_CODE (mem_addr) != VALUE
- && reg_mentioned_p (x_addr, mem_addr))
- || (GET_CODE (x_addr) != VALUE
- && GET_CODE (mem_addr) == VALUE
- && reg_mentioned_p (mem_addr, x_addr))))
- {
- x_addr = get_addr (x_addr);
- if (! mem_canonicalized)
- mem_addr = get_addr (mem_addr);
- }
- }
+ /* Read-only memory is by definition never modified, and therefore can't
+ conflict with anything. However, don't assume anything when AND
+ addresses are involved and leave to the code below to determine
+ dependence. We don't expect to find read-only set on MEM, but
+ stupid user tricks can produce them, so don't die. */
+ if (MEM_READONLY_P (x)
+ && GET_CODE (x_addr) != AND
+ && GET_CODE (true_mem_addr) != AND)
+ return 0;
+
+ /* If we have MEMs referring to different address spaces (which can
+ potentially overlap), we cannot easily tell from the addresses
+ whether the references overlap. */
+ if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
+ return 1;
base = find_base_term (x_addr);
if (base && (GET_CODE (base) == LABEL_REF
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
- rtx mem_base = find_base_term (mem_addr);
- if (! base_alias_check (x_addr, base, mem_addr, mem_base,
+ rtx mem_base = find_base_term (true_mem_addr);
+ if (! base_alias_check (x_addr, base, true_mem_addr, mem_base,
GET_MODE (x), mem_mode))
return 0;
x_addr = canon_rtx (x_addr);
if (!mem_canonicalized)
- mem_addr = canon_rtx (mem_addr);
+ mem_addr = canon_rtx (true_mem_addr);
if ((ret = memrefs_conflict_p (GET_MODE_SIZE (mem_mode), mem_addr,
SIZE_FOR_MODE (x), x_addr, 0)) != -1)
bool mem_canonicalized, bool x_canonicalized, bool writep)
{
rtx mem_addr;
+ rtx true_mem_addr, true_x_addr;
rtx base;
int ret;
|| MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
return 1;
- /* A read from read-only memory can't conflict with read-write memory. */
- if (!writep && MEM_READONLY_P (mem))
+ if (!x_addr)
+ x_addr = XEXP (x, 0);
+ true_x_addr = get_addr (x_addr);
+
+ mem_addr = XEXP (mem, 0);
+ true_mem_addr = get_addr (mem_addr);
+
+ /* A read from read-only memory can't conflict with read-write memory.
+ Don't assume anything when AND addresses are involved and leave to
+ the code below to determine dependence. */
+ if (!writep
+ && MEM_READONLY_P (mem)
+ && GET_CODE (true_x_addr) != AND
+ && GET_CODE (true_mem_addr) != AND)
return 0;
/* If we have MEMs referring to different address spaces (which can
if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
return 1;
- mem_addr = XEXP (mem, 0);
- if (!x_addr)
- {
- x_addr = XEXP (x, 0);
- if (!((GET_CODE (x_addr) == VALUE
- && GET_CODE (mem_addr) != VALUE
- && reg_mentioned_p (x_addr, mem_addr))
- || (GET_CODE (x_addr) != VALUE
- && GET_CODE (mem_addr) == VALUE
- && reg_mentioned_p (mem_addr, x_addr))))
- {
- x_addr = get_addr (x_addr);
- if (!mem_canonicalized)
- mem_addr = get_addr (mem_addr);
- }
- }
-
- base = find_base_term (mem_addr);
+ base = find_base_term (true_mem_addr);
if (! writep
&& base
&& (GET_CODE (base) == LABEL_REF
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
- rtx x_base = find_base_term (x_addr);
- if (! base_alias_check (x_addr, x_base, mem_addr, base, GET_MODE (x),
- GET_MODE (mem)))
+ rtx x_base = find_base_term (true_x_addr);
+ if (! base_alias_check (true_x_addr, x_base, true_mem_addr, base,
+ GET_MODE (x), GET_MODE (mem)))
return 0;
if (!x_canonicalized)
{
- x_addr = canon_rtx (x_addr);
+ x_addr = canon_rtx (true_x_addr);
x_mode = GET_MODE (x);
}
if (!mem_canonicalized)
- mem_addr = canon_rtx (mem_addr);
+ mem_addr = canon_rtx (true_mem_addr);
if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr,
GET_MODE_SIZE (x_mode), x_addr, 0)) != -1)
|| MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER)
return 1;
+ x_addr = XEXP (x, 0);
+ x_addr = get_addr (x_addr);
+
+ mem_addr = XEXP (mem, 0);
+ mem_addr = get_addr (mem_addr);
+
/* Read-only memory is by definition never modified, and therefore can't
- conflict with anything. We don't expect to find read-only set on MEM,
- but stupid user tricks can produce them, so don't die. */
- if (MEM_READONLY_P (x))
+ conflict with anything. However, don't assume anything when AND
+ addresses are involved and leave to the code below to determine
+ dependence. We don't expect to find read-only set on MEM, but
+ stupid user tricks can produce them, so don't die. */
+ if (MEM_READONLY_P (x)
+ && GET_CODE (x_addr) != AND
+ && GET_CODE (mem_addr) != AND)
return 0;
/* If we have MEMs referring to different address spaces (which can
if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x))
return 1;
- x_addr = XEXP (x, 0);
- mem_addr = XEXP (mem, 0);
- if (!((GET_CODE (x_addr) == VALUE
- && GET_CODE (mem_addr) != VALUE
- && reg_mentioned_p (x_addr, mem_addr))
- || (GET_CODE (x_addr) != VALUE
- && GET_CODE (mem_addr) == VALUE
- && reg_mentioned_p (mem_addr, x_addr))))
- {
- x_addr = get_addr (x_addr);
- mem_addr = get_addr (mem_addr);
- }
-
rtx x_base = find_base_term (x_addr);
rtx mem_base = find_base_term (mem_addr);
if (! base_alias_check (x_addr, x_base, mem_addr, mem_base,
GET_MODE (x), GET_MODE (mem_addr)))
return 0;
- x_addr = canon_rtx (x_addr);
- mem_addr = canon_rtx (mem_addr);
-
if (nonoverlapping_memrefs_p (mem, x, true))
return 0;
tree op1_utype = unsigned_type_for (type1);
HOST_WIDE_INT op0_prec = TYPE_PRECISION (type0);
tree uprecm1 = build_int_cst (op1_utype, op0_prec - 1);
- tree precm1 = build_int_cst (type1, op0_prec - 1);
t = fold_convert_loc (loc, op1_utype, op1);
t = fold_build2 (GT_EXPR, boolean_type_node, t, uprecm1);
/* For signed x << y, in C99/C11, the following:
- (unsigned) x >> (precm1 - y)
+ (unsigned) x >> (uprecm1 - y)
if non-zero, is undefined. */
if (code == LSHIFT_EXPR
&& !TYPE_UNSIGNED (type0)
&& flag_isoc99)
{
- tree x = fold_build2 (MINUS_EXPR, integer_type_node, precm1, op1);
+ tree x = fold_build2 (MINUS_EXPR, unsigned_type_node, uprecm1,
+ fold_convert (op1_utype, op1));
tt = fold_convert_loc (loc, unsigned_type_for (type0), op0);
tt = fold_build2 (RSHIFT_EXPR, TREE_TYPE (tt), tt, x);
tt = fold_build2 (NE_EXPR, boolean_type_node, tt,
}
/* For signed x << y, in C++11/C++14, the following:
- x < 0 || ((unsigned) x >> (precm1 - y))
+ x < 0 || ((unsigned) x >> (uprecm1 - y))
if > 1, is undefined. */
if (code == LSHIFT_EXPR
&& !TYPE_UNSIGNED (TREE_TYPE (op0))
&& (cxx_dialect == cxx11 || cxx_dialect == cxx1y))
{
- tree x = fold_build2 (MINUS_EXPR, integer_type_node, precm1, op1);
+ tree x = fold_build2 (MINUS_EXPR, unsigned_type_node, uprecm1,
+ fold_convert (op1_utype, op1));
tt = fold_convert_loc (loc, unsigned_type_for (type0), op0);
tt = fold_build2 (RSHIFT_EXPR, TREE_TYPE (tt), tt, x);
tt = fold_build2 (GT_EXPR, boolean_type_node, tt,
;;
sparc-*-rtems*)
tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h"
- tmake_file="${tmake_file} sparc/t-sparc sparc/t-elf sparc/t-rtems"
+ tmake_file="${tmake_file} sparc/t-sparc sparc/t-rtems"
;;
sparc-*-linux*)
tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h"
*-leon[3-9]*)
with_cpu=leon3
;;
+ *-leon[3-9]v7*)
+ with_cpu=leon3v7
+ ;;
*)
with_cpu="`echo ${target} | sed 's/-.*$//'`"
;;
case ${val} in
"" | sparc | sparcv9 | sparc64 \
| v7 | cypress \
- | v8 | supersparc | hypersparc | leon | leon3 \
+ | v8 | supersparc | hypersparc | leon | leon3 | leon3v7 \
| sparclite | f930 | f934 | sparclite86x \
| sparclet | tsc701 \
| v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
#endif
+/* Define if isl_schedule_constraints_compute_schedule exists. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+#endif
+
+
/* Define to 1 if you have the `kill' function. */
#ifndef USED_FOR_TARGET
#undef HAVE_KILL
})
(define_insn "*aarch64_simd_ld1r<mode>"
- [(set (match_operand:VALLDI 0 "register_operand" "=w")
- (vec_duplicate:VALLDI
+ [(set (match_operand:VALL 0 "register_operand" "=w")
+ (vec_duplicate:VALL
(match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))]
"TARGET_SIMD"
"ld1r\\t{%0.<Vtype>}, %1"
[(set_attr "type" "jsr")
(set_attr "length" "*,*,8")])
-(define_insn_and_split "call_value_osf_tlsgd"
+(define_int_iterator TLS_CALL
+ [UNSPEC_TLSGD_CALL
+ UNSPEC_TLSLDM_CALL])
+
+(define_int_attr tls
+ [(UNSPEC_TLSGD_CALL "tlsgd")
+ (UNSPEC_TLSLDM_CALL "tlsldm")])
+
+(define_insn "call_value_osf_<tls>"
[(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand"))
(const_int 0)))
- (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL)
+ (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
(use (reg:DI 29))
(clobber (reg:DI 26))]
"HAVE_AS_TLS"
- "#"
- "&& reload_completed"
+ "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
+ [(set_attr "type" "jsr")
+ (set_attr "length" "16")])
+
+;; We must use peep2 instead of a split because we need accurate life
+;; information for $gp.
+(define_peephole2
+ [(parallel
+ [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
+ (const_int 0)))
+ (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
+ (use (reg:DI 29))
+ (clobber (reg:DI 26))])]
+ "HAVE_AS_TLS && reload_completed
+ && peep2_regno_dead_p (1, 29)"
[(set (match_dup 3)
(unspec:DI [(match_dup 5)
(match_dup 1)
(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(const_int 0)))
- (set (match_dup 5)
- (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
+ (use (match_dup 5))
(use (match_dup 1))
- (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))
+ (use (unspec [(match_dup 2)] TLS_CALL))
(clobber (reg:DI 26))])
(set (match_dup 5)
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
operands[3] = gen_rtx_REG (Pmode, 27);
operands[4] = GEN_INT (alpha_next_sequence_number++);
operands[5] = pic_offset_table_rtx;
-}
- [(set_attr "type" "multi")])
+})
-(define_insn_and_split "call_value_osf_tlsldm"
- [(set (match_operand 0)
- (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
- (const_int 0)))
- (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL)
- (use (reg:DI 29))
- (clobber (reg:DI 26))]
- "HAVE_AS_TLS"
- "#"
- "&& reload_completed"
+(define_peephole2
+ [(parallel
+ [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
+ (const_int 0)))
+ (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL)
+ (use (reg:DI 29))
+ (clobber (reg:DI 26))])]
+ "HAVE_AS_TLS && reload_completed
+ && !peep2_regno_dead_p (1, 29)"
[(set (match_dup 3)
(unspec:DI [(match_dup 5)
(match_dup 1)
(set (match_dup 5)
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1))
(use (match_dup 1))
- (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))
+ (use (unspec [(match_dup 2)] TLS_CALL))
(clobber (reg:DI 26))])
(set (match_dup 5)
(unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
operands[3] = gen_rtx_REG (Pmode, 27);
operands[4] = GEN_INT (alpha_next_sequence_number++);
operands[5] = pic_offset_table_rtx;
-}
- [(set_attr "type" "multi")])
+})
(define_insn "*call_value_osf_1"
[(set (match_operand 0)
addr = plus_constant (Pmode, addr, delta);
}
- emit_move_insn (gen_frame_mem (Pmode, addr), source);
+ /* The store needs to be marked as frame related in order to prevent
+ DSE from deleting it as dead if it is based on fp. */
+ rtx insn = emit_move_insn (gen_frame_mem (Pmode, addr), source);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNUM));
}
}
else
addr = plus_constant (Pmode, addr, delta);
- emit_move_insn (gen_frame_mem (Pmode, addr), source);
+ /* The store needs to be marked as frame related in order to prevent
+ DSE from deleting it as dead if it is based on fp. */
+ rtx insn = emit_move_insn (gen_frame_mem (Pmode, addr), source);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNUM));
}
else
emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6"
; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
-; arm_arch6. This attribute is used to compute attribute "enabled",
-; use type "any" to enable an alternative in all cases.
-(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2"
+; arm_arch6. "v6t2" for Thumb-2 with arm_arch6. This attribute is
+; used to compute attribute "enabled", use type "any" to enable an
+; alternative in all cases.
+(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2"
(const_string "any"))
(define_attr "arch_enabled" "no,yes"
(match_test "TARGET_32BIT && !arm_arch6"))
(const_string "yes")
+ (and (eq_attr "arch" "v6t2")
+ (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2"))
+ (const_string "yes")
+
(and (eq_attr "arch" "avoid_neon_for_64bits")
(match_test "TARGET_NEON")
(not (match_test "TARGET_PREFER_NEON_64BITS")))
;; Pattern to recognize insn generated default case above
(define_insn "*movhi_insn_arch4"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
- (match_operand:HI 1 "general_operand" "rI,K,r,mi"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
+ (match_operand:HI 1 "general_operand" "rI,K,n,r,mi"))]
"TARGET_ARM
&& arm_arch4
&& (register_operand (operands[0], HImode)
"@
mov%?\\t%0, %1\\t%@ movhi
mvn%?\\t%0, #%B1\\t%@ movhi
+ movw%?\\t%0, %L1\\t%@ movhi
str%(h%)\\t%1, %0\\t%@ movhi
ldr%(h%)\\t%0, %1\\t%@ movhi"
[(set_attr "predicable" "yes")
- (set_attr "pool_range" "*,*,*,256")
- (set_attr "neg_pool_range" "*,*,*,244")
+ (set_attr "pool_range" "*,*,*,*,256")
+ (set_attr "neg_pool_range" "*,*,*,*,244")
+ (set_attr "arch" "*,*,v6t2,*,*")
(set_attr_alternative "type"
[(if_then_else (match_operand 1 "const_int_operand" "")
(const_string "mov_imm" )
(const_string "mov_reg"))
(const_string "mvn_imm")
+ (const_string "mov_imm")
(const_string "store1")
(const_string "load1")])]
)
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53
+# Arch Matches
+MULTILIB_MATCHES += march?armv8-a=march?armv8-a+crc
+
# FPU matches
MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3
MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
if (TREE_CODE (exp) == FUNCTION_DECL)
return false;
+ /* Automatic variables are never large data. */
+ if (TREE_CODE (exp) == VAR_DECL && !is_global_var (exp))
+ return false;
+
if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
{
const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
x86_64_elf_select_section (tree decl, int reloc,
unsigned HOST_WIDE_INT align)
{
- if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
- && ix86_in_large_data_p (decl))
+ if (ix86_in_large_data_p (decl))
{
const char *sname = NULL;
unsigned int flags = SECTION_WRITE;
static void ATTRIBUTE_UNUSED
x86_64_elf_unique_section (tree decl, int reloc)
{
- if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
- && ix86_in_large_data_p (decl))
+ if (ix86_in_large_data_p (decl))
{
const char *prefix = NULL;
/* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
{
if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
&& size > (unsigned int)ix86_section_threshold)
- fputs (".largecomm\t", file);
+ fputs ("\t.largecomm\t", file);
else
fputs (COMMON_ASM_OP, file);
assemble_name (file, name);
if (mode == CCmode)
suffix = "b";
else if (mode == CCCmode)
- suffix = "c";
+ suffix = fp ? "b" : "c";
else
gcc_unreachable ();
break;
break;
case GEU:
if (mode == CCmode)
- suffix = fp ? "nb" : "ae";
+ suffix = "nb";
else if (mode == CCCmode)
- suffix = "nc";
+ suffix = fp ? "nb" : "nc";
else
gcc_unreachable ();
break;
{
default_encode_section_info (decl, rtl, first);
- if (TREE_CODE (decl) == VAR_DECL
- && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
- && ix86_in_large_data_p (decl))
+ if (ix86_in_large_data_p (decl))
SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
}
;; type "binary" insns have two input operands (1,2) and one output (0)
(define_attr "type"
- "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload"
+ "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap"
(const_string "binary"))
(define_attr "pa_combine_type"
;; For conditional branches. Frame related instructions are not allowed
;; because they confuse the unwind support.
(define_attr "in_branch_delay" "false,true"
- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
+ (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
(eq_attr "length" "4")
(not (match_test "RTX_FRAME_RELATED_P (insn)")))
(const_string "true")
;; Disallow instructions which use the FPU since they will tie up the FPU
;; even if the instruction is nullified.
(define_attr "in_nullified_branch_delay" "false,true"
- (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
+ (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap")
(eq_attr "length" "4")
(not (match_test "RTX_FRAME_RELATED_P (insn)")))
(const_string "true")
;; For calls and millicode calls. Allow unconditional branches in the
;; delay slot.
(define_attr "in_call_delay" "false,true"
- (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
+ (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap")
(eq_attr "length" "4")
(not (match_test "RTX_FRAME_RELATED_P (insn)")))
(const_string "true")
[(set_attr "type" "binary,binary")
(set_attr "length" "4,4")])
+;; Trap instructions.
+
+(define_insn "trap"
+ [(trap_if (const_int 1) (const_int 0))]
+ ""
+ "{addit|addi,tc},<> 1,%%r0,%%r0"
+ [(set_attr "type" "trap")
+ (set_attr "length" "4")])
+
;; Clobbering a "register_operand" instead of a match_scratch
;; in operand3 of millicode calls avoids spilling %r1 and
;; produces better code.
"vrsave", "vscr", \
"spe_acc", "spefscr", \
"sfp", \
- "tfhar", "tfiar", "texasr" \
+ "tfhar", "tfiar", "texasr", \
+ "rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7", \
+ "rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15", \
+ "rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23", \
+ "rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31" \
}
/* This outputs NAME to FILE. */
{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
+ { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
+ RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
{ VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
+ { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
+ RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
{ VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
if (GET_CODE (y) == UNSPEC
&& XINT (y, 1) == UNSPEC_TOCREL)
{
-#ifdef ENABLE_CHECKING
- if (REG_P (XVECEXP (y, 0, 1))
- && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER)
- {
- /* All good. */
- }
- else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR)
- {
- /* Weirdness alert. df_note_compute can replace r2 with a
- debug_expr when this unspec is in a debug_insn.
- Seen in gcc.dg/pr51957-1.c */
- }
- else
- {
- debug_rtx (orig_x);
- abort ();
- }
-#endif
y = XVECEXP (y, 0, 0);
#ifdef HAVE_AS_TLS
struct ashl_lshr_sequence
{
char insn_count;
- char amount[6];
+ signed char amount[6];
char clobbers_t;
};
// Given a start insn and its basic block, recursively determine all
// possible ccreg values in all basic block paths that can lead to the
// start insn.
- void find_last_ccreg_values (rtx start_insn, basic_block bb,
+ bool find_last_ccreg_values (rtx start_insn, basic_block bb,
std::vector<ccreg_value>& values_out,
std::vector<basic_block>& prev_visited_bb) const;
ccreg_values.clear ();
visited_bbs.clear ();
- find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values,
- visited_bbs);
+ bool ok = find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values,
+ visited_bbs);
log_msg ("number of ccreg values collected: %u\n",
(unsigned int)ccreg_values.size ());
// If all the collected values are equal and are equal to the
// constant value of the setcc insn, the setcc insn can be
// removed.
- if (all_ccreg_values_equal (ccreg_values)
+ if (ok && all_ccreg_values_equal (ccreg_values)
&& rtx_equal_p (ccreg_values.front ().value, setcc_val))
{
log_msg ("all values are ");
gcc_unreachable ();
}
-void
+bool
sh_optimize_sett_clrt
::find_last_ccreg_values (rtx start_insn, basic_block bb,
std::vector<ccreg_value>& values_out,
log_msg ("\n");
values_out.push_back (v);
- return;
+ return true;
}
if (any_condjump_p (i) && onlyjump_p (i) && !prev_visited_bb.empty ())
log_msg ("\n");
values_out.push_back (v);
- return;
+ return true;
}
}
for (edge_iterator ei = ei_start (bb->preds); !ei_end_p (ei);
ei_next (&ei))
{
+ if (ei_edge (ei)->flags & EDGE_COMPLEX)
+ log_return (false, "aborting due to complex edge\n");
+
basic_block pred_bb = ei_edge (ei)->src;
pred_bb_count += 1;
- find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out,
- prev_visited_bb);
+ if (!find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out,
+ prev_visited_bb))
+ return false;
}
prev_visited_bb.pop_back ();
values_out.push_back (v);
}
+
+ return true;
}
bool
In [bb 4] elimination of the comparison would require inversion of the branch
condition and compensation of other BBs.
-Instead an inverting reg-move can be used:
+Instead the comparison in [bb 3] can be replaced with the comparison in [bb 5]
+by using a reg-reg move. In [bb 4] a logical not is used to compensate the
+inverted condition.
[bb 3]
(set (reg:SI 167) (reg:SI 173))
-> bb 5
[BB 4]
-(set (reg:SI 167) (not:SI (reg:SI 177)))
+(set (reg:SI 147 t) (eq:SI (reg:SI 177) (const_int 0)))
+(set (reg:SI 167) (reg:SI 147 t))
-> bb 5
[bb 5]
and replace the comparisons in the BBs with reg-reg copies to get the
operands in place (create new pseudo regs).
- - If the cstores differ, try to apply the special case
- (eq (reg) (const_int 0)) -> inverted = (not (reg)).
- for the subordinate cstore types and eliminate the dominating ones.
+ - If the cstores differ and the comparison is a test against zero,
+ use reg-reg copies for the dominating cstores and logical not cstores
+ for the subordinate cstores.
- If the comparison types in the BBs are not the same, or the first approach
doesn't work out for some reason, try to eliminate the comparison before the
bool can_extend_ccreg_usage (const bb_entry& e,
const cbranch_trace& trace) const;
- // Create an insn rtx that is a negating reg move (not operation).
+ // Create an insn rtx that performs a logical not (test != 0) on the src_reg
+ // and stores the result in dst_reg.
rtx make_not_reg_insn (rtx dst_reg, rtx src_reg) const;
// Create an insn rtx that inverts the ccreg.
rtx
sh_treg_combine::make_not_reg_insn (rtx dst_reg, rtx src_reg) const
{
- // This will to go through expanders and may output multiple insns
- // for multi-word regs.
+ // On SH we can do only SImode and DImode comparisons.
+ if (! (GET_MODE (src_reg) == SImode || GET_MODE (src_reg) == DImode))
+ return NULL;
+
+ // On SH we can store the ccreg into an SImode or DImode reg only.
+ if (! (GET_MODE (dst_reg) == SImode || GET_MODE (dst_reg) == DImode))
+ return NULL;
+
start_sequence ();
- expand_simple_unop (GET_MODE (dst_reg), NOT, src_reg, dst_reg, 0);
+
+ emit_insn (gen_rtx_SET (VOIDmode, m_ccreg,
+ gen_rtx_fmt_ee (EQ, SImode, src_reg, const0_rtx)));
+
+ if (GET_MODE (dst_reg) == SImode)
+ emit_move_insn (dst_reg, m_ccreg);
+ else if (GET_MODE (dst_reg) == DImode)
+ {
+ emit_move_insn (gen_lowpart (SImode, dst_reg), m_ccreg);
+ emit_move_insn (gen_highpart (SImode, dst_reg), const0_rtx);
+ }
+ else
+ gcc_unreachable ();
+
rtx i = get_insns ();
end_sequence ();
+
return i;
}
// There is one special case though, where an integer comparison
// (eq (reg) (const_int 0))
// can be inverted with a sequence
- // (eq (not (reg)) (const_int 0))
+ // (set (t) (eq (reg) (const_int 0))
+ // (set (reg) (t))
+ // (eq (reg) (const_int 0))
+ //
+ // FIXME: On SH2A it might be better to use the nott insn in this case,
+ // i.e. do the try_eliminate_cstores approach instead.
if (inv_cstore_count != 0 && cstore_count != 0)
{
if (make_not_reg_insn (comp_op0, comp_op0) == NULL_RTX)
;; Use a double reservation to work around the load pipeline hazard on UT699.
(define_insn_reservation "leon3_load" 1
- (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload"))
+ (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload"))
"leon_memory*2")
(define_insn_reservation "leon_store" 2
- (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store"))
+ (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "store"))
"leon_memory*2")
;; This describes Gaisler Research's FPU
(define_cpu_unit "grfpu_ds" "grfpu")
(define_insn_reservation "leon_fp_alu" 4
- (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul"))
+ (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fp,fpcmp,fpmul"))
"grfpu_alu, nothing*3")
(define_insn_reservation "leon_fp_divs" 16
- (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs"))
+ (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivs"))
"grfpu_ds*14, nothing*2")
(define_insn_reservation "leon_fp_divd" 17
- (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd"))
+ (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivd"))
"grfpu_ds*15, nothing*2")
(define_insn_reservation "leon_fp_sqrts" 24
- (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts"))
+ (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrts"))
"grfpu_ds*22, nothing*2")
(define_insn_reservation "leon_fp_sqrtd" 25
- (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd"))
+ (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrtd"))
"grfpu_ds*23, nothing*2")
PROCESSOR_HYPERSPARC,
PROCESSOR_LEON,
PROCESSOR_LEON3,
+ PROCESSOR_LEON3V7,
PROCESSOR_SPARCLITE,
PROCESSOR_F930,
PROCESSOR_F934,
{ TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC },
{ TARGET_CPU_leon, PROCESSOR_LEON },
{ TARGET_CPU_leon3, PROCESSOR_LEON3 },
+ { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 },
{ TARGET_CPU_sparclite, PROCESSOR_F930 },
{ TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X },
{ TARGET_CPU_sparclet, PROCESSOR_TSC701 },
{ "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
{ "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
{ "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
+ { "leon3v7", MASK_ISA, MASK_LEON3|MASK_FPU },
{ "sparclite", MASK_ISA, MASK_SPARCLITE },
/* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
{ "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
sparc_costs = &leon_costs;
break;
case PROCESSOR_LEON3:
+ case PROCESSOR_LEON3V7:
sparc_costs = &leon3_costs;
break;
case PROCESSOR_SPARCLET:
}
/* Used by function_arg and sparc_function_value_1 to implement the conventions
- for passing and returning large (BLKmode) vectors.
+ for passing and returning BLKmode vectors.
Return an expression valid as a return value for the FUNCTION_ARG
and TARGET_FUNCTION_VALUE.
- SIZE is the size in bytes of the vector (at least 8 bytes).
+ SIZE is the size in bytes of the vector.
REGNO is the FP hard register the vector will be passed in. */
static rtx
function_arg_vector_value (int size, int regno)
{
- int i, nregs = size / 8;
- rtx regs;
-
- regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
+ const int nregs = MAX (1, size / 8);
+ rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
- for (i = 0; i < nregs; i++)
- {
+ if (size < 8)
+ XVECEXP (regs, 0, 0)
+ = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (SImode, regno),
+ const0_rtx);
+ else
+ for (int i = 0; i < nregs; i++)
XVECEXP (regs, 0, i)
= gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (DImode, regno + 2*i),
GEN_INT (i*8));
- }
return regs;
}
|| (TARGET_ARCH64 && size <= 16));
if (mode == BLKmode)
- return function_arg_vector_value (size,
- SPARC_FP_ARG_FIRST + 2*slotno);
- else
- mclass = MODE_FLOAT;
+ return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno);
+
+ mclass = MODE_FLOAT;
}
if (TARGET_ARCH32)
|| (TARGET_ARCH64 && size <= 32));
if (mode == BLKmode)
- return function_arg_vector_value (size,
- SPARC_FP_ARG_FIRST);
- else
- mclass = MODE_FLOAT;
+ return function_arg_vector_value (size, SPARC_FP_ARG_FIRST);
+
+ mclass = MODE_FLOAT;
}
if (TARGET_ARCH64 && type)
#define TARGET_CPU_hypersparc 3
#define TARGET_CPU_leon 4
#define TARGET_CPU_leon3 5
-#define TARGET_CPU_sparclite 6
-#define TARGET_CPU_f930 6 /* alias */
-#define TARGET_CPU_f934 6 /* alias */
-#define TARGET_CPU_sparclite86x 7
-#define TARGET_CPU_sparclet 8
-#define TARGET_CPU_tsc701 8 /* alias */
-#define TARGET_CPU_v9 9 /* generic v9 implementation */
-#define TARGET_CPU_sparcv9 9 /* alias */
-#define TARGET_CPU_sparc64 9 /* alias */
-#define TARGET_CPU_ultrasparc 10
-#define TARGET_CPU_ultrasparc3 11
-#define TARGET_CPU_niagara 12
-#define TARGET_CPU_niagara2 13
-#define TARGET_CPU_niagara3 14
-#define TARGET_CPU_niagara4 15
+#define TARGET_CPU_leon3v7 6
+#define TARGET_CPU_sparclite 7
+#define TARGET_CPU_f930 7 /* alias */
+#define TARGET_CPU_f934 7 /* alias */
+#define TARGET_CPU_sparclite86x 8
+#define TARGET_CPU_sparclet 9
+#define TARGET_CPU_tsc701 9 /* alias */
+#define TARGET_CPU_v9 10 /* generic v9 implementation */
+#define TARGET_CPU_sparcv9 10 /* alias */
+#define TARGET_CPU_sparc64 10 /* alias */
+#define TARGET_CPU_ultrasparc 11
+#define TARGET_CPU_ultrasparc3 12
+#define TARGET_CPU_niagara 13
+#define TARGET_CPU_niagara2 14
+#define TARGET_CPU_niagara3 15
+#define TARGET_CPU_niagara4 16
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7
+#define CPP_CPU32_DEFAULT_SPEC "-D__leon__"
+#define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG
+#endif
+
#endif
#if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
%{mcpu=leon:-D__leon__ -D__sparc_v8__} \
%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
+%{mcpu=leon3v7:-D__leon__} \
%{mcpu=v9:-D__sparc_v9__} \
%{mcpu=ultrasparc:-D__sparc_v9__} \
%{mcpu=ultrasparc3:-D__sparc_v9__} \
%{mcpu=hypersparc:-Av8} \
%{mcpu=leon:" AS_LEON_FLAG "} \
%{mcpu=leon3:" AS_LEON_FLAG "} \
+%{mcpu=leon3v7:" AS_LEONV7_FLAG "} \
%{mv8plus:-Av8plus} \
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
#ifdef HAVE_AS_LEON
#define AS_LEON_FLAG "-Aleon"
+#define AS_LEONV7_FLAG "-Aleon"
#else
#define AS_LEON_FLAG "-Av8"
+#define AS_LEONV7_FLAG "-Av7"
#endif
/* We use gcc _mcount for profiling. */
hypersparc,
leon,
leon3,
+ leon3v7,
sparclite,
f930,
f934,
Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
EnumValue
+Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7)
+
+EnumValue
Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
EnumValue
# <http://www.gnu.org/licenses/>.
#
-MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3
-MULTILIB_DIRNAMES = soft v8 leon3
+MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3/mcpu=leon3v7 muser-mode
+MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 user-mode
MULTILIB_MATCHES = msoft-float=mno-fpu
+
+MULTILIB_EXCEPTIONS = muser-mode
+MULTILIB_EXCEPTIONS += mcpu=leon3
+MULTILIB_EXCEPTIONS += mcpu=leon3v7
+MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3
+MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3v7
+MULTILIB_EXCEPTIONS += msoft-float/muser-mode
+MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/muser-mode
+MULTILIB_EXCEPTIONS += mcpu=v8/muser-mode
$as_echo "#define HAVE_cloog 1" >>confdefs.h
+
+ # Check whether isl_schedule_constraints_compute_schedule is available;
+ # it's new in ISL-0.13.
+ saved_CFLAGS="$CFLAGS"
+ CFLAGS="$CFLAGS $ISLINC"
+ saved_LIBS="$LIBS"
+ LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS"
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking Checking for isl_schedule_constraints_compute_schedule" >&5
+$as_echo_n "checking Checking for isl_schedule_constraints_compute_schedule... " >&6; }
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h. */
+#include <isl/schedule.h>
+int
+main ()
+{
+isl_schedule_constraints_compute_schedule (NULL);
+ ;
+ return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+ ac_has_isl_schedule_constraints_compute_schedule=yes
+else
+ ac_has_isl_schedule_constraints_compute_schedule=no
fi
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_has_isl_schedule_constraints_compute_schedule" >&5
+$as_echo "$ac_has_isl_schedule_constraints_compute_schedule" >&6; }
+
+ LIBS="$saved_LIBS"
+ CFLAGS="$saved_CFLAGS"
+
+ if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then
+
+$as_echo "#define HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE 1" >>confdefs.h
+
+ fi
+fi
+
# Check for plugin support
# Check whether --enable-plugin was given.
AC_ARG_VAR(CLOOGINC,[How to find CLOOG include files])
if test "x${CLOOGLIBS}" != "x" ; then
AC_DEFINE(HAVE_cloog, 1, [Define if cloog is in use.])
+
+ # Check whether isl_schedule_constraints_compute_schedule is available;
+ # it's new in ISL-0.13.
+ saved_CFLAGS="$CFLAGS"
+ CFLAGS="$CFLAGS $ISLINC"
+ saved_LIBS="$LIBS"
+ LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS"
+
+ AC_MSG_CHECKING([Checking for isl_schedule_constraints_compute_schedule])
+ AC_TRY_LINK([#include <isl/schedule.h>],
+ [isl_schedule_constraints_compute_schedule (NULL);],
+ [ac_has_isl_schedule_constraints_compute_schedule=yes],
+ [ac_has_isl_schedule_constraints_compute_schedule=no])
+ AC_MSG_RESULT($ac_has_isl_schedule_constraints_compute_schedule)
+
+ LIBS="$saved_LIBS"
+ CFLAGS="$saved_CFLAGS"
+
+ if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then
+ AC_DEFINE(HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE, 1,
+ [Define if isl_schedule_constraints_compute_schedule exists.])
+ fi
fi
+
# Check for plugin support
AC_ARG_ENABLE(plugin,
[AS_HELP_STRING([--enable-plugin], [enable plugin support])],
enum built_in_function fcode = builtin_mathfn_code (expr);
tree itype = TREE_TYPE (expr);
+ if (TREE_CODE (expr) == COMPOUND_EXPR)
+ {
+ tree t = convert_to_real (type, TREE_OPERAND (expr, 1));
+ if (t == TREE_OPERAND (expr, 1))
+ return expr;
+ return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t),
+ TREE_OPERAND (expr, 0), t);
+ }
+
/* Disable until we figure out how to decide whether the functions are
present in runtime. */
/* Convert (float)sqrt((double)x) where x is float into sqrtf(x) */
return error_mark_node;
}
+ if (ex_form == COMPOUND_EXPR)
+ {
+ tree t = convert_to_integer (type, TREE_OPERAND (expr, 1));
+ if (t == TREE_OPERAND (expr, 1))
+ return expr;
+ return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t),
+ TREE_OPERAND (expr, 0), t);
+ }
+
/* Convert e.g. (long)round(d) -> lround(d). */
/* If we're converting to char, we may encounter differing behavior
between converting from double->char vs double->long->char.
if (TYPE_MAIN_VARIANT (elt_type) == TYPE_MAIN_VARIANT (subtype))
return expr;
+ else if (TREE_CODE (expr) == COMPOUND_EXPR)
+ {
+ tree t = convert_to_complex (type, TREE_OPERAND (expr, 1));
+ if (t == TREE_OPERAND (expr, 1))
+ return expr;
+ return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR,
+ TREE_TYPE (t), TREE_OPERAND (expr, 0), t);
+ }
else if (TREE_CODE (expr) == COMPLEX_EXPR)
return fold_build2 (COMPLEX_EXPR, type,
convert (subtype, TREE_OPERAND (expr, 0)),
+2014-11-21 Jason Merrill <jason@redhat.com>
+
+ PR c++/63849
+ * mangle.c (decl_mangling_context): Use template_type_parameter_p.
+
+2014-11-11 Paolo Carlini <paolo.carlini@oracle.com>
+
+ PR c++/63265
+ * pt.c (tsubst_copy_and_build, case COND_EXPR): Maybe fold to
+ constant the condition.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
if (extra)
return extra;
}
- else if (TREE_CODE (decl) == TYPE_DECL
- && TREE_CODE (TREE_TYPE (decl)) == TEMPLATE_TYPE_PARM)
+ else if (template_type_parameter_p (decl))
/* template type parms have no mangling context. */
return NULL_TREE;
return CP_DECL_CONTEXT (decl);
case COND_EXPR:
{
tree cond = RECUR (TREE_OPERAND (t, 0));
+ tree folded_cond = (maybe_constant_value
+ (fold_non_dependent_expr_sfinae (cond, tf_none)));
tree exp1, exp2;
- if (TREE_CODE (cond) == INTEGER_CST)
+ if (TREE_CODE (folded_cond) == INTEGER_CST)
{
- if (integer_zerop (cond))
+ if (integer_zerop (folded_cond))
{
++c_inhibit_evaluation_warnings;
exp1 = RECUR (TREE_OPERAND (t, 1));
exp2 = RECUR (TREE_OPERAND (t, 2));
--c_inhibit_evaluation_warnings;
}
+ cond = folded_cond;
}
else
{
Set the instruction set, register set, and instruction scheduling parameters
for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc},
-@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934},
-@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
+@samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930},
+@samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
@samp{niagara3} and @samp{niagara4}.
@table @asis
@item v7
-cypress
+cypress, leon3v7
@item v8
supersparc, hypersparc, leon, leon3
The same values for @option{-mcpu=@var{cpu_type}} can be used for
@option{-mtune=@var{cpu_type}}, but the only useful values are those
that select a particular CPU implementation. Those are @samp{cypress},
-@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930},
-@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
-@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and
-@samp{niagara4}. With native Solaris and GNU/Linux toolchains, @samp{native}
-can also be used.
+@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3},
+@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701},
+@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
+@samp{niagara3} and @samp{niagara4}. With native Solaris and GNU/Linux
+toolchains, @samp{native} can also be used.
@item -mv8plus
@itemx -mno-v8plus
of spill registers and print a fatal error message.
@end deftypefn
-@deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM
-If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately.
-@end deftypevr
-
@node Scalar Return
@subsection How Scalar Function Values Are Returned
@cindex return values in registers
@smallexample
#define SELECT_CC_MODE(OP,X,Y) \
- (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
- ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
- : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
- || GET_CODE (X) == NEG) \
+ (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
+ ? ((OP == LT || OP == LE || OP == GT || OP == GE) \
+ ? CCFPEmode : CCFPmode) \
+ : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
+ || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \
? CC_NOOVmode : CCmode))
@end smallexample
You need not define this macro if it would always returns zero or if the
floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}.
For example, here is the definition used on the SPARC, where floating-point
-inequality comparisons are always given @code{CCFPEmode}:
+inequality comparisons are given either @code{CCFPEmode} or @code{CCFPmode}:
@smallexample
-#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
+#define REVERSIBLE_CC_MODE(MODE) \
+ ((MODE) != CCFPEmode && (MODE) != CCFPmode)
@end smallexample
@end defmac
@code{REVERSIBLE_CC_MODE (@var{mode})} is nonzero. Define this macro in case
machine has some non-standard way how to reverse certain conditionals. For
instance in case all floating point conditions are non-trapping, compiler may
-freely convert unordered compares to ordered one. Then definition may look
+freely convert unordered compares to ordered ones. Then definition may look
like:
@smallexample
returns @code{VOIDmode}.
@end deftypefn
+@deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM
+If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately.
+@end deftypevr
+
@node Costs
@section Describing Relative Costs of Operations
@cindex costs of instructions
@hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
-@hook TARGET_FLAGS_REGNUM
-
@node Scalar Return
@subsection How Scalar Function Values Are Returned
@cindex return values in registers
@smallexample
#define SELECT_CC_MODE(OP,X,Y) \
- (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
- ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
- : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
- || GET_CODE (X) == NEG) \
+ (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
+ ? ((OP == LT || OP == LE || OP == GT || OP == GE) \
+ ? CCFPEmode : CCFPmode) \
+ : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
+ || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \
? CC_NOOVmode : CCmode))
@end smallexample
You need not define this macro if it would always returns zero or if the
floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}.
For example, here is the definition used on the SPARC, where floating-point
-inequality comparisons are always given @code{CCFPEmode}:
+inequality comparisons are given either @code{CCFPEmode} or @code{CCFPmode}:
@smallexample
-#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
+#define REVERSIBLE_CC_MODE(MODE) \
+ ((MODE) != CCFPEmode && (MODE) != CCFPmode)
@end smallexample
@end defmac
@code{REVERSIBLE_CC_MODE (@var{mode})} is nonzero. Define this macro in case
machine has some non-standard way how to reverse certain conditionals. For
instance in case all floating point conditions are non-trapping, compiler may
-freely convert unordered compares to ordered one. Then definition may look
+freely convert unordered compares to ordered ones. Then definition may look
like:
@smallexample
@hook TARGET_CC_MODES_COMPATIBLE
+@hook TARGET_FLAGS_REGNUM
+
@node Costs
@section Describing Relative Costs of Operations
@cindex costs of instructions
/* Check for cases where the C++ memory model applies. */
if (bitregion_end != 0
&& (bitnum - bitnum % modesize < bitregion_start
- || bitnum - bitnum % modesize + modesize > bitregion_end))
+ || bitnum - bitnum % modesize + modesize - 1 > bitregion_end))
return false;
return true;
enum mult_variant variant;
struct algorithm algorithm;
+ if (coeff == 0)
+ return CONST0_RTX (mode);
+
/* Special case powers of two. */
if (EXACT_POWER_OF_2_OR_ZERO_P (coeff))
{
break;
case COMPOUND_LITERAL_EXPR:
- /* Allow COMPOUND_LITERAL_EXPR in initializers, if e.g.
- rtl_for_decl_init is called on DECL_INITIAL with
- COMPOUNT_LITERAL_EXPRs in it, they aren't gimplified. */
- if (modifier == EXPAND_INITIALIZER
- && COMPOUND_LITERAL_EXPR_DECL (exp))
+ /* Allow COMPOUND_LITERAL_EXPR in initializers or coming from
+ initializers, if e.g. rtl_for_decl_init is called on DECL_INITIAL
+ with COMPOUND_LITERAL_EXPRs in it, or ARRAY_REF on a const static
+ array with address of COMPOUND_LITERAL_EXPR in DECL_INITIAL;
+ the initializers aren't gimplified. */
+ if (COMPOUND_LITERAL_EXPR_DECL (exp)
+ && TREE_STATIC (COMPOUND_LITERAL_EXPR_DECL (exp)))
return expand_expr_addr_expr_1 (COMPOUND_LITERAL_EXPR_DECL (exp),
target, tmode, modifier, as);
/* FALLTHRU */
/* If the constant operation overflowed this can be
simplified as a comparison against INT_MAX/INT_MIN. */
if (TREE_CODE (lhs) == INTEGER_CST
- && TREE_OVERFLOW (lhs))
+ && TREE_OVERFLOW (lhs)
+ && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0)))
{
int const1_sgn = tree_int_cst_sgn (const1);
enum tree_code code2 = code;
tree itype = TREE_TYPE (arg00);
if (TREE_INT_CST_HIGH (arg01) == 0
&& TREE_INT_CST_LOW (arg01)
- == (unsigned HOST_WIDE_INT) (TYPE_PRECISION (itype) - 1))
+ == (unsigned HOST_WIDE_INT) (element_precision (itype) - 1))
{
if (TYPE_UNSIGNED (itype))
{
+2014-11-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2014-11-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/63938
+ * trans-openmp.c (gfc_trans_omp_atomic): Make sure lhsaddr is
+ simple enough for goa_lhs_expr_p.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
}
lhsaddr = save_expr (lhsaddr);
+ if (TREE_CODE (lhsaddr) != SAVE_EXPR
+ && (TREE_CODE (lhsaddr) != ADDR_EXPR
+ || TREE_CODE (TREE_OPERAND (lhsaddr, 0)) != VAR_DECL))
+ {
+ /* Make sure LHS is simple enough so that goa_lhs_expr_p can recognize
+ it even after unsharing function body. */
+ tree var = create_tmp_var_raw (TREE_TYPE (lhsaddr), NULL);
+ DECL_CONTEXT (var) = current_function_decl;
+ lhsaddr = build4 (TARGET_EXPR, TREE_TYPE (lhsaddr), var, lhsaddr,
+ NULL_TREE, NULL_TREE);
+ }
+
rhs = gfc_evaluate_now (rse.expr, &block);
if (((atomic_code->ext.omp_atomic & GFC_OMP_ATOMIC_MASK)
#include <isl/aff.h>
#include <cloog/cloog.h>
#include <cloog/isl/domain.h>
+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+#include <isl/deprecated/int.h>
+#include <isl/lp.h>
+#include <isl/deprecated/ilp_int.h>
+#endif
#endif
#include "system.h"
#include <isl/ilp.h>
#include <cloog/cloog.h>
#include <cloog/isl/domain.h>
+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+#include <isl/deprecated/int.h>
+#include <isl/deprecated/aff_int.h>
+#include <isl/deprecated/ilp_int.h>
+#include <isl/deprecated/constraint_int.h>
+#endif
#endif
#include "system.h"
#include <isl/band.h>
#include <isl/aff.h>
#include <isl/options.h>
+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+#include <isl/deprecated/int.h>
+#include <isl/deprecated/aff_int.h>
+#endif
#endif
#include "system.h"
{
for (i = ScheduleDimensions - 1 ; i >= 0 ; i--)
{
+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+ if (isl_band_member_is_coincident (Band, i))
+#else
if (isl_band_member_is_zero_distance (Band, i))
+#endif
{
isl_map *TileMap;
isl_union_map *TileUMap;
#include <isl/aff.h>
#include <cloog/cloog.h>
#include <cloog/isl/domain.h>
+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+#include <isl/deprecated/int.h>
+#include <isl/deprecated/ilp_int.h>
+#endif
#endif
#include "system.h"
#include <cloog/cloog.h>
#include <cloog/cloog.h>
#include <cloog/isl/domain.h>
+#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE
+#include <isl/deprecated/int.h>
+#include <isl/deprecated/aff_int.h>
+#include <isl/deprecated/constraint_int.h>
+#endif
#endif
#include "system.h"
}
if (c->code == IS_NOT_CONSTANT || c->code == CHANGED)
continue;
- res = fold_binary_to_constant (c->code, boolean_type_node, val, c->val);
- if (res && integer_zerop (res))
- continue;
+
+ if (operand_equal_p (TYPE_SIZE (TREE_TYPE (c->val)),
+ TYPE_SIZE (TREE_TYPE (val)), 0))
+ {
+ val = fold_unary (VIEW_CONVERT_EXPR, TREE_TYPE (c->val), val);
+
+ res = val
+ ? fold_binary_to_constant (c->code, boolean_type_node, val, c->val)
+ : NULL;
+
+ if (res && integer_zerop (res))
+ continue;
+ }
clause |= 1 << (i + predicate_first_dynamic_condition);
}
return clause;
else if (e->can_throw_external && !TREE_NOTHROW (y->decl))
can_throw = true;
}
- for (ie = node->indirect_calls; ie; ie = ie->next_callee)
+ for (ie = w->indirect_calls; ie; ie = ie->next_callee)
if (ie->can_throw_external)
{
can_throw = true;
ira_allocno_iterator ai;
FOR_EACH_ALLOCNO (a, ai)
- ALLOCNO_REGNO (a) = REGNO (ALLOCNO_EMIT_DATA (a)->reg);
+ {
+ int old_regno = ALLOCNO_REGNO (a);
+ int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg);
+
+ ALLOCNO_REGNO (a) = new_regno;
+
+ if (old_regno != new_regno)
+ setup_reg_classes (new_regno, reg_preferred_class (old_regno),
+ reg_alternate_class (old_regno),
+ reg_allocno_class (old_regno));
+ }
+
}
else
{
static int max_insn_uid;
+/* Update or remove REG_EQUAL or REG_EQUIV notes for INSN. */
+
+static bool
+update_reg_equal_equiv_notes (rtx insn, enum machine_mode new_mode,
+ enum machine_mode old_mode, enum rtx_code code)
+{
+ rtx *loc = ®_NOTES (insn);
+ while (*loc)
+ {
+ enum reg_note kind = REG_NOTE_KIND (*loc);
+ if (kind == REG_EQUAL || kind == REG_EQUIV)
+ {
+ rtx orig_src = XEXP (*loc, 0);
+ /* Update equivalency constants. Recall that RTL constants are
+ sign-extended. */
+ if (GET_CODE (orig_src) == CONST_INT
+ && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (new_mode))
+ {
+ if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
+ /* Nothing needed. */;
+ else
+ {
+ /* Zero-extend the negative constant by masking out the
+ bits outside the source mode. */
+ rtx new_const_int
+ = gen_int_mode (INTVAL (orig_src)
+ & GET_MODE_MASK (old_mode),
+ new_mode);
+ if (!validate_change (insn, &XEXP (*loc, 0),
+ new_const_int, true))
+ return false;
+ }
+ loc = &XEXP (*loc, 1);
+ }
+ /* Drop all other notes, they assume a wrong mode. */
+ else if (!validate_change (insn, loc, XEXP (*loc, 1), true))
+ return false;
+ }
+ else
+ loc = &XEXP (*loc, 1);
+ }
+ return true;
+}
+
/* Given a insn (CURR_INSN), an extension candidate for removal (CAND)
and a pointer to the SET rtx (ORIG_SET) that needs to be modified,
this code modifies the SET rtx to a new SET rtx that extends the
combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set)
{
rtx orig_src = SET_SRC (*orig_set);
+ enum machine_mode orig_mode = GET_MODE (SET_DEST (*orig_set));
rtx new_set;
rtx cand_pat = PATTERN (cand->insn);
{
/* Zero-extend the negative constant by masking out the bits outside
the source mode. */
- enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set));
rtx new_const_int
- = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (src_mode),
+ = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (orig_mode),
GET_MODE (new_reg));
new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int);
}
/* This change is a part of a group of changes. Hence,
validate_change will not try to commit the change. */
- if (validate_change (curr_insn, orig_set, new_set, true))
+ if (validate_change (curr_insn, orig_set, new_set, true)
+ && update_reg_equal_equiv_notes (curr_insn, cand->mode, orig_mode,
+ cand->code))
{
if (dump_file)
{
ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2);
new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr);
- if (validate_change (def_insn, &PATTERN (def_insn), new_set, true))
+ if (validate_change (def_insn, &PATTERN (def_insn), new_set, true)
+ && update_reg_equal_equiv_notes (def_insn, cand->mode, GET_MODE (dstreg),
+ cand->code))
{
if (dump_file)
{
+2014-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/56493
+ * c-c++-common/pr56493.c: New test.
+
+2014-12-03 Renlin Li <Renlin.Li@arm.com>
+
+ Backported from mainline
+ 2014-12-03 Renlin Li <Renlin.Li@arm.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ PR middle-end/63762
+ PR target/63661
+ * gcc.dg/pr63762.c: New test.
+ * gcc.target/i386/pr63661.c: New test.
+
+2014-12-01 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/63551
+ * gcc.dg/ipa/pr63551.c: New test.
+ * gcc.dg/ipa/pr64041.c: Likewise.
+
+2014-12-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/63738
+ * gcc.dg/torture/pr63738.c: Fix call to setjmp.
+
+2014-11-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2014-11-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/64067
+ * gcc.c-torture/compile/pr64067.c: New test.
+
+ 2014-11-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/63915
+ * c-c++-common/gomp/pr60823-4.c: New test.
+
+ PR sanitizer/63913
+ * g++.dg/ubsan/pr63913.C: New test.
+
+ 2014-10-31 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/63659
+ * gcc.c-torture/execute/pr63659.c: New test.
+
+2014-11-26 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/63738
+ * gcc.dg/torture/pr63738.c: New testcase.
+
+2014-11-26 Richard Biener <rguenther@suse.de>
+
+ Backport from mainline
+ 2014-11-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/62238
+ * gcc.dg/torture/pr62238.c: New testcase.
+
+ 2014-11-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/63605
+ * gcc.dg/vect/pr63605.c: New testcase.
+
+ 2014-10-28 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/63665
+ * gcc.dg/pr63665.c: New testcase.
+
+2014-11-24 Eric Botcazou <ebotcazou@adacore.com>
+
+ * gnat.dg/opt45.adb: New test.
+
+2014-11-22 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline
+ 2014-11-22 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/63783
+ PR target/51244
+ * gcc.target/sh/torture/pr63783-1.c: New.
+ * gcc.target/sh/torture/pr63783-2.c: New.
+ * gcc.target/sh/pr51244-20.c: Adjust.
+ * gcc.target/sh/pr51244-20-sh2a.c: Adjust.
+
+2014-11-19 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/63947
+ * gcc.target/i386/pr63947.c: New test.
+
+2014-11-19 Tom de Vries <tom@codesourcery.com>
+
+ Backport from mainline
+ PR tree-optimization/62167
+ * gcc.dg/pr51879-12.c: Add xfails.
+ * gcc.dg/pr62167-run.c: New test.
+ * gcc.dg/pr62167.c: New test.
+
+2014-11-13 Teresa Johnson <tejohnson@google.com>
+
+ PR tree-optimization/63841
+ * g++.dg/tree-ssa/pr63841.C: New test.
+
+2014-11-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR ipa/63838
+ * g++.dg/ipa/pr63838.C: New test.
+
+2014-11-11 Paolo Carlini <paolo.carlini@oracle.com>
+
+ PR c++/63265
+ * g++.dg/cpp0x/constexpr-63265.C: New.
+
+2014-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backported from mainline
+ 2014-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR testsuite/63305
+ * gcc.target/i386/avx256-unaligned-load-7.c (avx_test): Fix
+ buffer overflow.
+ * gcc.target/i386/avx256-unaligned-store-7.c (avx_test): Likewise.
+
+2014-11-07 Marek Polacek <polacek@redhat.com>
+
+ * c-c++-common/ubsan/undefined-2.c: New test.
+
+2014-11-05 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/63538
+ * gcc.target/i386/pr63538.c: New test.
+
+2014-11-03 Marek Polacek <polacek@redhat.com>
+
+ PR c/52769
+ * gcc.dg/pr52769.c: New test.
+
+2014-10-31 DJ Delorie <dj@redhat.com>
+
+ * gcc.dg/20141029-1.c: New.
+
2014-10-31 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/63697
--- /dev/null
+/* PR tree-optimization/63915 */
+/* { dg-do run } */
+/* { dg-require-effective-target vect_simd_clones } */
+/* { dg-options "-O2 -fopenmp-simd" } */
+/* { dg-additional-options "-fpic" { target fpic } } */
+
+#include "pr60823-2.c"
--- /dev/null
+/* PR c++/56493 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-gimple" } */
+
+unsigned long long bar (void);
+int x;
+
+void
+foo (void)
+{
+ x += bar ();
+}
+
+/* Verify we narrow the addition from unsigned long long to unsigned int type. */
+/* { dg-final { scan-tree-dump " (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* = \\1 \\+ \\2;" "gimple" { target { ilp32 || lp64 } } } } */
+/* { dg-final { cleanup-tree-dump "gimple" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-fsanitize=undefined" } */
+/* { dg-additional-options "-std=gnu11" { target c } } */
+/* { dg-additional-options "-std=c++11" { target c++ } } */
+
+#include <stdio.h>
+
+volatile int w, z;
+
+__attribute__ ((noinline, noclone)) int
+foo (int x, int y)
+{
+ z++;
+ return x << y;
+}
+
+int
+main ()
+{
+ fputs ("1st\n", stderr);
+ w = foo (0, -__INT_MAX__);
+ return 0;
+}
+
+/* { dg-output "1st(\n|\r\n|\r)" } */
+/* { dg-output "\[^\n\r]*shift exponent -\[^\n\r]* is negative\[^\n\r]*(\n|\r\n|\r)" } */
--- /dev/null
+// PR c++/63849
+// { dg-do compile { target c++11 } }
+
+template <class _T, class...>
+using First = _T; // we should not use this
+ // alias with only
+ // one pack parameter (?)
+
+template <template <class...> class _Successor,
+ int,
+ class... _Xs>
+struct Overlay
+{
+ using O = _Successor<_Xs...>;
+};
+
+template <class... _Pack>
+struct List
+{
+ template <int _s>
+ using O = typename Overlay<List, _s, _Pack...>::O;
+
+ template <template <class...> class _S>
+ using Pass = _S<_Pack...>;
+
+ template <int _i>
+ using At = typename O<_i>
+ ::template Pass<First>;
+};
+
+template <int _i>
+using At = typename List<int, char>
+::template At<_i>;
+
+template <int _i>
+void func_crash(At<_i>&) {}
+
+int main(int argc, char *argv[])
+{
+ char ccc;
+ int iii;
+ func_crash<0>(iii);
+}
--- /dev/null
+// PR c++/63265
+// { dg-do compile { target c++11 } }
+
+#define LSHIFT (sizeof(unsigned int) * __CHAR_BIT__)
+
+template <int lshift>
+struct SpuriouslyWarns1 {
+ static constexpr unsigned int v = lshift < LSHIFT ? 1U << lshift : 0;
+};
+
+static_assert(SpuriouslyWarns1<LSHIFT>::v == 0, "Impossible occurred");
+
+template <int lshift>
+struct SpuriouslyWarns2 {
+ static constexpr bool okay = lshift < LSHIFT;
+ static constexpr unsigned int v = okay ? 1U << lshift : 0;
+};
+
+static_assert(SpuriouslyWarns2<LSHIFT>::v == 0, "Impossible occurred");
--- /dev/null
+// PR ipa/63838
+// { dg-do run }
+// { dg-options "-O2 -fdump-ipa-pure-const" }
+// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void foo" "pure-const" } }
+// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void bar" "pure-const" } }
+// { dg-final { cleanup-ipa-dump "pure-const" } }
+
+__attribute__((noinline, noclone)) static void bar (int);
+volatile int v;
+void (*fn) ();
+struct S { S () { v++; } ~S () { v++; } };
+
+__attribute__((noinline, noclone)) static void
+foo (int x)
+{
+ v++;
+ if (x == 5)
+ bar (x);
+}
+
+__attribute__((noinline, noclone)) static void
+bar (int x)
+{
+ v++;
+ if (x == 6)
+ foo (x);
+ else if (x == 5)
+ fn ();
+}
+
+__attribute__((noinline, noclone)) int
+baz (int x)
+{
+ S s;
+ foo (x);
+}
+
+void
+throw0 ()
+{
+ throw 0;
+}
+
+int
+main ()
+{
+ fn = throw0;
+ asm volatile ("" : : : "memory");
+ try
+ {
+ baz (5);
+ }
+ catch (int)
+ {
+ }
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include <string>
+
+std::string __attribute__ ((noinline)) comp_test_write() {
+ std::string data;
+
+ for (int i = 0; i < 2; ++i) {
+ char b = 1 >> (i * 8);
+ data.append(&b, 1);
+ }
+
+ return data;
+}
+
+std::string __attribute__ ((noinline)) comp_test_write_good() {
+ std::string data;
+
+ char b;
+ for (int i = 0; i < 2; ++i) {
+ b = 1 >> (i * 8);
+ data.append(&b, 1);
+ }
+
+ return data;
+}
+
+int main() {
+ std::string good = comp_test_write_good();
+ std::string bad = comp_test_write();
+
+ if (good != bad)
+ __builtin_abort ();
+}
--- /dev/null
+// PR sanitizer/63913
+// { dg-do compile }
+// { dg-options "-fsanitize=bool -fnon-call-exceptions" }
+
+struct B { B (); ~B (); };
+
+double
+foo (bool *x)
+{
+ B b;
+ return *x;
+}
--- /dev/null
+/* PR middle-end/64067 */
+
+struct S { int s; };
+int *const v[1] = { &((struct S) { .s = 42 }).s };
+
+int *
+foo (void)
+{
+ return v[0];
+}
--- /dev/null
+/* PR rtl-optimization/63659 */
+
+int a, b, c, *d = &b, g, h, i;
+unsigned char e;
+char f;
+
+int
+main ()
+{
+ while (a)
+ {
+ for (a = 0; a; a++)
+ for (; c; c++)
+ ;
+ if (i)
+ break;
+ }
+
+ char j = c, k = -1, l;
+ l = g = j >> h;
+ f = l == 0 ? k : k % l;
+ e = 0 ? 0 : f;
+ *d = e;
+
+ if (b != 255)
+ __builtin_abort ();
+
+ return 0;
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-fstrict-volatile-bitfields -fdump-rtl-final" } */
+
+#define PERIPH (*(volatile struct system_periph *)0x81234)
+
+struct system_periph {
+ union {
+ unsigned short WORD;
+ struct {
+ unsigned short a:1;
+ unsigned short b:1;
+ unsigned short :5;
+ unsigned short c:1;
+ unsigned short :8;
+ } BIT;
+ } ALL;
+};
+
+void
+foo()
+{
+ while (1)
+ {
+ PERIPH.ALL.BIT.a = 1;
+ }
+}
+/* { dg-final { scan-rtl-dump-times "mem/v(/.)*:HI" 4 "final" } } */
+/* { dg-final { cleanup-rtl-dump "final" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-Os" } */
+
+union U
+{
+ unsigned int f0;
+ int f1;
+};
+
+int a, d;
+
+void
+fn1 (union U p)
+{
+ if (p.f1 <= 0)
+ if (a)
+ d = 0;
+}
+
+void
+fn2 ()
+{
+ d = 0;
+ union U b = { 4294967286 };
+ fn1 (b);
+}
+
+int
+main ()
+{
+ fn2 ();
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+int printf (const char *, ...);
+
+int a, b = 1, d;
+
+union U1
+{
+ unsigned int f0;
+ int f1;
+};
+
+union U2
+{
+ int f2;
+ int f3;
+} c;
+
+int
+fn1 (int p)
+{
+ int t = p && a || p && a && p;
+ return t ? t : a;
+}
+
+unsigned
+fn2 (union U1 p1, union U2 p2)
+{
+ if (p1.f1 <= 0)
+ {
+ for (; p2.f2;)
+ c.f2 = 0;
+ p2.f2 = fn1 (d);
+ }
+ return p2.f3;
+}
+
+int g = 0;
+
+int
+foo ()
+{
+ if (b)
+ {
+ union U1 f = { 0xFFFFFFFFU };
+
+ fn2 (f, c);
+ }
+ g = 1;
+ return 0;
+}
+
+
+int
+main ()
+{
+ foo ();
+
+ if (g == 0)
+ __builtin_abort ();
+
+ return 0;
+}
baz (a);
}
-/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre"} } */
-/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre"} } */
+/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre" { xfail *-*-* } } } */
+/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre" { xfail *-*-* } } } */
/* { dg-final { cleanup-tree-dump "pre" } } */
--- /dev/null
+/* PR c/52769 */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+typedef struct
+{
+ int should_be_zero;
+ char s[6];
+ int x;
+} foo_t;
+
+int
+main (void)
+{
+ volatile foo_t foo = {
+ .s = "123456",
+ .x = 2
+ };
+
+ if (foo.should_be_zero != 0)
+ __builtin_abort ();
+
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-tail-merge" } */
+
+struct node
+{
+ struct node *next;
+ struct node *prev;
+};
+
+struct node node;
+
+struct head
+{
+ struct node *first;
+};
+
+struct head heads[5];
+
+int k = 2;
+
+struct head *head = &heads[2];
+
+int
+main ()
+{
+ struct node *p;
+
+ node.next = (void*)0;
+
+ node.prev = (void *)head;
+
+ head->first = &node;
+
+ struct node *n = head->first;
+
+ struct head *h = &heads[k];
+
+ heads[2].first = n->next;
+
+ if ((void*)n->prev == (void *)h)
+ p = h->first;
+ else
+ /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */
+ p = n->prev->next;
+
+ return !(p == (void*)0);
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */
+
+struct node
+{
+ struct node *next;
+ struct node *prev;
+};
+
+struct node node;
+
+struct head
+{
+ struct node *first;
+};
+
+struct head heads[5];
+
+int k = 2;
+
+struct head *head = &heads[2];
+
+int
+main ()
+{
+ struct node *p;
+
+ node.next = (void*)0;
+
+ node.prev = (void *)head;
+
+ head->first = &node;
+
+ struct node *n = head->first;
+
+ struct head *h = &heads[k];
+
+ heads[2].first = n->next;
+
+ if ((void*)n->prev == (void *)h)
+ p = h->first;
+ else
+ /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */
+ p = n->prev->next;
+
+ return !(p == (void*)0);
+}
+
+/* { dg-final { scan-tree-dump-not "Removing basic block" "pre"} } */
+/* { dg-final { cleanup-tree-dump "pre" } } */
--- /dev/null
+/* { dg-do run } */
+/* { dg-require-effective-target int32plus } */
+/* { dg-options "-O -fno-tree-ccp -fno-tree-fre -fno-tree-copy-prop -fwrapv" } */
+
+static inline int
+test5 (int x)
+{
+ int y = 0x80000000;
+ return x + y;
+}
+
+int
+main ()
+{
+ if (test5 (0x80000000) != 0)
+ __builtin_abort ();
+ return 0;
+}
--- /dev/null
+/* PR middle-end/63762 */
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+#include <stdlib.h>
+
+void *astFree ();
+void *astMalloc ();
+void astNegate (void *);
+int astGetNegated (void *);
+void astGetRegionBounds (void *, double *, double *);
+int astResampleF (void *, ...);
+
+extern int astOK;
+
+int
+MaskF (int inside, int ndim, const int lbnd[], const int ubnd[],
+ float in[], float val)
+{
+
+ void *used_region;
+ float *c, *d, *out, *tmp_out;
+ double *lbndgd, *ubndgd;
+ int *lbndg, *ubndg, idim, ipix, nax, nin, nout, npix, npixg, result = 0;
+ if (!astOK) return result;
+ lbndg = astMalloc (sizeof (int)*(size_t) ndim);
+ ubndg = astMalloc (sizeof (int)*(size_t) ndim);
+ lbndgd = astMalloc (sizeof (double)*(size_t) ndim);
+ ubndgd = astMalloc (sizeof (double)*(size_t) ndim);
+ if (astOK)
+ {
+ astGetRegionBounds (used_region, lbndgd, ubndgd);
+ npix = 1;
+ npixg = 1;
+ for (idim = 0; idim < ndim; idim++)
+ {
+ lbndg[ idim ] = lbnd[ idim ];
+ ubndg[ idim ] = ubnd[ idim ];
+ npix *= (ubnd[ idim ] - lbnd[ idim ] + 1);
+ if (npixg >= 0) npixg *= (ubndg[ idim ] - lbndg[ idim ] + 1);
+ }
+ if (npixg <= 0 && astOK)
+ {
+ if ((inside != 0) == (astGetNegated( used_region ) != 0))
+ {
+ c = in;
+ for (ipix = 0; ipix < npix; ipix++) *(c++) = val;
+ result = npix;
+ }
+ }
+ else if (npixg > 0 && astOK)
+ {
+ if ((inside != 0) == (astGetNegated (used_region) != 0))
+ {
+ tmp_out = astMalloc (sizeof (float)*(size_t) npix);
+ if (tmp_out)
+ {
+ c = tmp_out;
+ for (ipix = 0; ipix < npix; ipix++) *(c++) = val;
+ result = npix - npixg;
+ }
+ out = tmp_out;
+ }
+ else
+ {
+ tmp_out = NULL;
+ out = in;
+ }
+ if (inside) astNegate (used_region);
+ result += astResampleF (used_region, ndim, lbnd, ubnd, in, NULL,
+ NULL, NULL, 0, 0.0, 100, val, ndim,
+ lbnd, ubnd, lbndg, ubndg, out, NULL);
+ if (inside) astNegate (used_region);
+ }
+ }
+ return result;
+}
--- /dev/null
+/* { dg-do run } */
+
+int a[4], b, c, d;
+
+int
+fn1 (int p)
+{
+ for (; d; d++)
+ {
+ unsigned int h;
+ for (h = 0; h < 3; h++)
+ {
+ if (a[c+c+h])
+ {
+ if (p)
+ break;
+ return 0;
+ }
+ b = 0;
+ }
+ }
+ return 0;
+}
+
+int
+main ()
+{
+ fn1 (0);
+ return 0;
+}
--- /dev/null
+/* { dg-do compile } */
+
+#include <setjmp.h>
+
+struct longjmp_buffer {
+ jmp_buf buf;
+};
+
+void plouf();
+
+extern long interprete()
+{
+ long * sp;
+ int i;
+ long *args;
+ int n;
+
+ struct longjmp_buffer raise_buf;
+ setjmp (raise_buf.buf);
+
+ plouf();
+ sp -= 4;
+ for (i = 0; i < n; i++)
+ args[i] = sp[10-i];
+ plouf();
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+
+#include "tree-vect.h"
+
+extern void abort (void);
+
+int a, b[8] = { 2, 0, 0, 0, 0, 0, 0, 0 }, c[8];
+
+int
+main ()
+{
+ int d;
+ check_vect ();
+ for (; a < 8; a++)
+ {
+ d = b[a] >> 1;
+ c[a] = d != 0;
+ }
+ if (c[0] != 1)
+ abort ();
+ return 0;
+}
cp = mp;
dp = lp;
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
*cp++ = str;
*dp++ = str;
cp = mp;
dp = lp;
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
*ap++ = *cp++;
*bp++ = *dp++;
}
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
if (strcmp (*--ap, "STR") != 0)
abort ();
ap = ep;
bp = fp;
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
*ap++ = str;
*bp++ = str;
}
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
if (strcmp (*--ap, "STR") != 0)
abort ();
--- /dev/null
+/* PR target/63538 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcmodel=medium -mlarge-data-threshold=0" } */
+
+static char *str = "Hello World";
+
+char *foo ()
+{
+ return str;
+}
+
+/* { dg-final { scan-assembler "movabs" } } */
--- /dev/null
+/* PR target/63661 */
+/* { dg-do run } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-mtune=nehalem -fPIC -O2" } */
+
+static void __attribute__((noinline,noclone,hot))
+foo (double a, double q, double *ff, double *gx, int e, int ni)
+{
+ union
+ {
+ double n;
+ unsigned long long o;
+ } punner;
+ double d;
+
+ punner.n = q;
+ __builtin_printf("B: 0x%016llx ---- %g\n", punner.o, q);
+
+ d = q - 5;
+ if(d < 0)
+ d = -d;
+ if (d > 0.1)
+ __builtin_abort();
+}
+
+static int __attribute__((noinline,noclone,hot))
+bar (int order, double q, double c[])
+{
+ int ni, nn, i, e;
+ double g2, x2, de, s, ratio, ff;
+
+ nn = 0;
+ e = order & 1;
+ s = 0;
+ ratio = 0;
+ x2 = 0;
+ g2 = 0;
+
+ if(q == 0.0)
+ return 0;
+
+ if (order < 5)
+ {
+ ratio = 1.0 / q;
+ nn = order;
+ }
+
+ ni = -nn;
+
+ while(1)
+ {
+ de = ratio - g2 - x2;
+
+ foo (0, q, &ff, &g2, e, ni);
+
+ if((int)de == 0)
+ break;
+ }
+
+ s += 2 * nn * c[nn];
+
+ for (i = 0; i < 1; i++)
+ {
+ c[0] = nn;
+ for (; i < 10; i++)
+ c[i] = 0.0;
+ c[0] /= s;
+ }
+
+ return 0;
+}
+
+int
+main ()
+{
+ double c[1000];
+
+ bar (1, 5.0, c);
+ return 0;
+}
--- /dev/null
+/* PR target/63947 */
+/* { dg-do assemble } */
+/* { dg-options "-Os" } */
+/* { dg-additional-options "-march=i686" { target ia32 } } */
+
+long double foo (unsigned a, unsigned b)
+{
+ return a + b < a;
+}
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
-/* { dg-final { scan-assembler-times "tst" 5 } } */
-/* { dg-final { scan-assembler-times "movt" 0 } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 1 } } */
/* { dg-final { scan-assembler-times "nott" 1 } } */
/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
/* { dg-final { scan-assembler-times "cmp/gt" 3 } } */
-/* { dg-final { scan-assembler-times "not\t" 1 } } */
+/* { dg-final { scan-assembler-not "not\t" } } */
#include "pr51244-20.c"
/* Check that the SH specific sh_treg_combine RTL optimization pass works as
expected. On SH2A the expected insns are slightly different, see
- pr51244-21.c. */
+ pr51244-20-sh2a.c. */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
-/* { dg-final { scan-assembler-times "tst" 6 } } */
-/* { dg-final { scan-assembler-times "movt" 1 } } */
+/* { dg-final { scan-assembler-times "tst" 7 } } */
+/* { dg-final { scan-assembler-times "movt" 2 } } */
/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
/* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
-/* { dg-final { scan-assembler-times "not\t" 1 } } */
+/* { dg-final { scan-assembler-not "not\t" } } */
/* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
}
-/* 2x tst, 1x cmp/hi, 1x not */
+/* 3x tst, 1x movt, 1x cmp/hi, 1x not */
static inline int
blk_oversized_queue_5 (int* q)
{
--- /dev/null
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99" } */
+
+#include <assert.h>
+
+int decision_result;
+int val;
+int truecount = 0;
+
+static void __attribute__((noinline))
+buggy (int flag)
+{
+ int condition;
+ if(flag == 0)
+ condition = val != 0;
+ else
+ condition = !decision_result;
+ if (condition)
+ truecount++;
+}
+
+int
+main (void)
+{
+ decision_result = 1;
+ buggy(1);
+ assert (truecount == 0);
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99" } */
+
+#include <assert.h>
+
+long long decision_result;
+long long val;
+int truecount = 0;
+
+static void __attribute__((noinline))
+buggy (int flag)
+{
+ int condition;
+ if(flag == 0)
+ condition = val != 0;
+ else
+ condition = !decision_result;
+ if (condition)
+ truecount++;
+}
+
+int
+main (void)
+{
+ decision_result = 1;
+ buggy(1);
+ assert (truecount == 0);
+ return 0;
+}
--- /dev/null
+-- { dg-do compile }
+-- { dg-options "-O3" }
+
+procedure Opt45 is
+
+ type Index_T is mod 2 ** 32;
+ for Index_T'Size use 32;
+ for Index_T'Alignment use 1;
+
+ type Array_T is array (Index_T range <>) of Natural;
+ type Array_Ptr_T is access all Array_T;
+
+ My_Array_1 : aliased Array_T := (1, 2);
+ My_Array_2 : aliased Array_T := (3, 4);
+
+ Array_Ptr : Array_Ptr_T := null;
+ Index : Index_T := Index_T'First;
+
+ My_Value : Natural := Natural'First;
+
+ procedure Proc (Selection : Positive) is
+ begin
+ if Selection = 1 then
+ Array_Ptr := My_Array_1'Access;
+ Index := My_Array_1'First;
+ else
+ Array_Ptr := My_Array_2'Access;
+ Index := My_Array_2'First;
+ end if;
+
+ if My_Value = Natural'First then
+ My_Value := Array_Ptr.all (Index);
+ end if;
+ end;
+
+begin
+ Proc (2);
+end;
case SSA_NAME:
{
+ if (SSA_NAME_OCCURS_IN_ABNORMAL_PHI (op0))
+ return false;
+
gimple def_stmt = SSA_NAME_DEF_STMT (op0);
enum tree_code subcode;
off = size_binop (PLUS_EXPR, off,
size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter)));
tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off);
- addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr,
- NULL_TREE);
+ addr = force_gimple_operand_1 (unshare_expr (addr), stmts,
+ is_gimple_mem_ref_addr, NULL_TREE);
tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff);
/* While data-ref analysis punts on bit offsets it still handles
bitfield accesses at byte boundaries. Cope with that. Note that
&& (INTEGRAL_TYPE_P (TREE_TYPE (def_op))
|| POINTER_TYPE_P (TREE_TYPE (def_op)))
&& (TYPE_PRECISION (TREE_TYPE (op))
- == TYPE_PRECISION (TREE_TYPE (def_op))))
+ == TYPE_PRECISION (TREE_TYPE (def_op)))
+ && (TYPE_SIZE (TREE_TYPE (op))
+ == TYPE_SIZE (TREE_TYPE (def_op))))
{
TREE_OPERAND (gimple_assign_rhs1 (stmt), 0) = def_op;
update_stmt (stmt);
break;
}
}
- else if (is_gimple_assign (stmt))
+ else if (is_gimple_assign (stmt) && !gimple_clobber_p (stmt))
{
tree lhs = gimple_assign_lhs (stmt);
if (gimple_vdef (stmt) != NULL_TREE
|| gimple_has_side_effects (stmt)
- || gimple_could_trap_p_1 (stmt, false, false))
+ || gimple_could_trap_p_1 (stmt, false, false)
+ || gimple_vuse (stmt) != NULL_TREE)
return false;
def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF);
gimple_assign_rhs1 (s2)));
else if (TREE_CODE (lhs1) == SSA_NAME
&& TREE_CODE (lhs2) == SSA_NAME)
- return vn_valueize (lhs1) == vn_valueize (lhs2);
+ return operand_equal_p (gimple_assign_rhs1 (s1),
+ gimple_assign_rhs1 (s2), 0);
return false;
case GIMPLE_COND:
return false;
}
+ /* Classify all cross-iteration scalar data-flow cycles.
+ Cross-iteration cycles caused by virtual phis are analyzed separately. */
+
+ vect_analyze_scalar_cycles (loop_vinfo);
+
+ vect_pattern_recog (loop_vinfo, NULL);
+
/* Analyze the access patterns of the data-refs in the loop (consecutive,
complex, etc.). FORNOW: Only handle consecutive access pattern. */
return false;
}
- /* Classify all cross-iteration scalar data-flow cycles.
- Cross-iteration cycles caused by virtual phis are analyzed separately. */
-
- vect_analyze_scalar_cycles (loop_vinfo);
-
- vect_pattern_recog (loop_vinfo, NULL);
-
/* Data-flow analysis to detect stmts that do not need to be vectorized. */
ok = vect_mark_stmts_to_be_vectorized (loop_vinfo);
set_vinfo_for_stmt (new_stmt, stmt_info);
set_vinfo_for_stmt (stmt, NULL);
STMT_VINFO_STMT (stmt_info) = new_stmt;
- gsi_replace (gsi, new_stmt, false);
+ gsi_replace (gsi, new_stmt, true);
unlink_stmt_vdef (stmt);
return true;
const_tree const t = (const_tree) x;
return (TREE_INT_CST_HIGH (t) ^ TREE_INT_CST_LOW (t)
- ^ htab_hash_pointer (TREE_TYPE (t)));
+ ^ TYPE_UID (TREE_TYPE (t)));
}
/* Return nonzero if the value represented by *X (an INTEGER_CST tree node)
#include "asan.h"
#include "gimplify-me.h"
#include "intl.h"
+#include "tree-eh.h"
/* Map from a tree to a VAR_DECL tree. */
|| TREE_CODE (gimple_assign_lhs (stmt)) != SSA_NAME)
return;
+ bool can_throw = stmt_could_throw_p (stmt);
location_t loc = gimple_location (stmt);
+ tree lhs = gimple_assign_lhs (stmt);
tree ptype = build_pointer_type (TREE_TYPE (rhs));
tree atype = reference_alias_ptr_type (rhs);
gimple g = gimple_build_assign (make_ssa_name (ptype, NULL),
tree mem = build2 (MEM_REF, utype, gimple_assign_lhs (g),
build_int_cst (atype, 0));
tree urhs = make_ssa_name (utype, NULL);
- g = gimple_build_assign (urhs, mem);
- gimple_set_location (g, loc);
- gsi_insert_before (gsi, g, GSI_SAME_STMT);
+ if (can_throw)
+ {
+ gimple_assign_set_lhs (stmt, urhs);
+ g = gimple_build_assign_with_ops (NOP_EXPR, lhs, urhs, NULL_TREE);
+ gimple_set_location (g, loc);
+ edge e = find_fallthru_edge (gimple_bb (stmt)->succs);
+ gsi_insert_on_edge_immediate (e, g);
+ gimple_assign_set_rhs_from_tree (gsi, mem);
+ update_stmt (stmt);
+ *gsi = gsi_for_stmt (g);
+ g = stmt;
+ }
+ else
+ {
+ g = gimple_build_assign (urhs, mem);
+ gimple_set_location (g, loc);
+ gsi_insert_before (gsi, g, GSI_SAME_STMT);
+ }
minv = fold_convert (utype, minv);
maxv = fold_convert (utype, maxv);
if (!integer_zerop (minv))
gimple_set_location (g, loc);
gsi_insert_after (gsi, g, GSI_NEW_STMT);
- gimple_assign_set_rhs_with_ops (&gsi2, NOP_EXPR, urhs, NULL_TREE);
- update_stmt (stmt);
+ if (!can_throw)
+ {
+ gimple_assign_set_rhs_with_ops (&gsi2, NOP_EXPR, urhs, NULL_TREE);
+ update_stmt (stmt);
+ }
tree data = ubsan_create_data ("__ubsan_invalid_value_data",
&loc, NULL,
bool first_function_block_is_cold;
-/* We give all constants their own alias set. Perhaps redundant with
- MEM_READONLY_P, but pre-dates it. */
-
-static alias_set_type const_alias_set;
-
/* Whether we saw any functions with no_split_stack. */
static bool saw_no_split_stack;
rtl = gen_const_mem (TYPE_MODE (TREE_TYPE (exp)), symbol);
set_mem_attributes (rtl, exp, 1);
set_mem_alias_set (rtl, 0);
- set_mem_alias_set (rtl, const_alias_set);
/* We cannot share RTX'es in pool entries.
Mark this piece of RTL as required for unsharing. */
const_desc_htab = htab_create_ggc (1009, const_desc_hash,
const_desc_eq, NULL);
- const_alias_set = new_alias_set ();
shared_constant_pool = create_constant_pool ();
#ifdef TEXT_SECTION_ASM_OP
+2014-11-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2014-11-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR preprocessor/60436
+ * line-map.c (linemap_line_start): If highest is above 0x60000000
+ and we are still tracking columns or highest is above 0x70000000,
+ force add_map.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
&& line_delta * ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) > 1000)
|| (max_column_hint >= (1U << ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map)))
|| (max_column_hint <= 80
- && ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) >= 10))
- {
- add_map = true;
- }
+ && ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) >= 10)
+ || (highest > 0x60000000
+ && (set->max_column_hint || highest > 0x70000000)))
+ add_map = true;
else
max_column_hint = set->max_column_hint;
if (add_map)
/* If the column number is ridiculous or we've allocated a huge
number of source_locations, give up on column numbers. */
max_column_hint = 0;
- if (highest >0x70000000)
+ if (highest > 0x70000000)
return 0;
column_bits = 0;
}
+2014-11-07 Joseph Myers <joseph@codesourcery.com>
+
+ * ja.po: Update.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
# Daisuke Yamashita <yamad@mb.infoweb.ne.jp>, 1999-2001
# Masahito Yamaga <yamaga@ipc.chiba-u.ac.jp>, 1999.
# IIDA Yosiaki <iida@secom.ne.jp>, 1999.
-# Yasuaki Taniguchi <yasuakit@gmail.com>, 2010, 2011.
# Takeshi Hamasaki <hmatrjp@users.sourceforge.jp>, 2012, 2013
+# Yasuaki Taniguchi <yasuakit@gmail.com>, 2010, 2011, 2014.
msgid ""
msgstr ""
-"Project-Id-Version: cpplib 4.8-b20130224\n"
+"Project-Id-Version: cpplib 4.9-b20140202\n"
"Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n"
"POT-Creation-Date: 2014-02-02 17:35+0000\n"
-"PO-Revision-Date: 2013-03-04 18:01+0900\n"
-"Last-Translator: Takeshi Hamasaki <hmatrjp@users.sourceforge.jp>\n"
+"PO-Revision-Date: 2014-11-07 08:19+0000\n"
+"Last-Translator: Yasuaki Taniguchi <yasuakit@gmail.com>\n"
"Language-Team: Japanese <translation-team-ja@lists.sourceforge.net>\n"
"Language: ja\n"
"MIME-Version: 1.0\n"
"Content-Type: text/plain; charset=UTF-8\n"
"Content-Transfer-Encoding: 8bit\n"
"Plural-Forms: nplurals=1; plural=0;\n"
-"X-Generator: Poedit 1.5.4\n"
#: charset.c:673
#, c-format
msgstr "整数定数に無効な接尾辞 \"%.*s\" があります"
#: expr.c:667
-#, fuzzy
-#| msgid "use of C++0x long long integer constant"
msgid "use of C++11 long long integer constant"
-msgstr "C++0x の long long 整数定数を使用しています"
+msgstr "C++11 の long long 整数定数を使用しています"
#: expr.c:668
msgid "use of C99 long long integer constant"
msgstr "虚数定数は GCC 拡張です"
#: expr.c:690
-#, fuzzy
-#| msgid "binary constants are a GCC extension"
msgid "binary constants are a C++1y feature or GCC extension"
-msgstr "二進定数は GCC 拡張です"
+msgstr "二進定数は C++1y の機能または GCC 拡張です"
#: expr.c:787
msgid "integer constant is too large for its type"
msgstr "生の文字列区切りが 16 文字より大きいです"
#: lex.c:1558
-#, fuzzy
-#| msgid "invalid character '%c' in raw string delimiter"
msgid "invalid new-line in raw string delimiter"
-msgstr "ç\94\9fã\81®æ\96\87å\97å\88\97å\8cºå\88\87ã\82\8aå\86\85ã\81«ç\84¡å\8a¹ã\81ªæ\96\87å\97 '%c' があります"
+msgstr "ç\94\9fã\81®æ\96\87å\97å\88\97å\8cºå\88\87ã\82\8aå\86\85ã\81«ç\84¡å\8a¹ã\81ªæ\94¹è¡\8cがあります"
#: lex.c:1562
#, c-format
msgstr "終端されていない生の文字列です"
#: lex.c:1654 lex.c:1783
-#, fuzzy
-#| msgid "invalid suffix on literal; C++11 requires a space between literal and identifier"
msgid "invalid suffix on literal; C++11 requires a space between literal and string macro"
-msgstr "リテラルの接尾辞が無効です。C++11 では、リテラルと識別子の間にスペースを入れる必要があります。"
+msgstr "リテラルの接尾辞が無効です。C++11 では、リテラルと文字列マクロの間にスペースを入れる必要があります。"
#: lex.c:1765
msgid "null character(s) preserved in literal"
#: macro.c:236 macro.c:333
#, c-format
msgid "macro \"%s\" might prevent reproducible builds"
-msgstr ""
+msgstr "マクロ \"%s\" は再生性可能なビルドを阻害するかもしれません"
#: macro.c:267
msgid "could not determine file timestamp"
+2014-12-03 Uros Bizjak <ubizjak@gmail.com>
+
+ * configure.tgt (x86_64-*-linux*): Tune -m32 multilib to generic.
+
+2014-11-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from mainline
+ 2014-11-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/63938
+ * libgomp.fortran/pr63938-1.f90: New test.
+ * libgomp.fortran/pr63938-2.f90: New test.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
config_path="linux/x86 linux posix"
case " ${CC} ${CFLAGS} " in
*" -m32 "*)
- XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686"
+ XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
;;
esac
;;
--- /dev/null
+! PR fortran/63938
+! { dg-do run }
+
+program pr63938_1
+ integer :: i, x(1)
+ x(1) = 0
+!$omp parallel do
+ do i = 1, 1000
+ !$omp atomic
+ x(1) = x(1) + 1
+ end do
+!$omp end parallel do
+ if (x(1) .ne. 1000) call abort
+end program pr63938_1
--- /dev/null
+! PR fortran/63938
+! { dg-do run }
+
+program pr63938_2
+ type t
+ integer :: x
+ end type
+ integer :: i
+ type(t) :: x
+ x%x = 0
+!$omp parallel do
+ do i = 1, 1000
+ !$omp atomic
+ x%x = x%x + 1
+ end do
+!$omp end parallel do
+ if (x%x .ne. 1000) call abort
+end program pr63938_2
+2014-12-03 Uros Bizjak <ubizjak@gmail.com>
+
+ * configure.tgt (x86_64): Tune -m32 multilib to generic.
+
2014-10-30 Release Manager
* GCC 4.9.2 released.
x86_64)
case " ${CC} ${CFLAGS} " in
*" -m32 "*)
- XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686"
+ XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
XCFLAGS="${XCFLAGS} -fomit-frame-pointer"
;;
esac
-2014-10-30 David Edelsohn
+2014-12-02 Matthias Klose <doko@ubuntu.com>
+
+ PR libstdc++/64103
+ Backport from mainline
+ 2014-11-03 Paolo Carlini <paolo.carlini@oracle.com>
+
+ * include/parallel/algo.h: Do not use default arguments in function
+ template redeclarations (definitions).
+
+ 2014-11-04 Jonathan Wakely <jwakely@redhat.com>
+
+ * include/parallel/numeric.h: Do not use default arguments in function
+ template redeclarations (definitions).
+
+2014-11-28 Tim Shen <timshen@google.com>
+
+ PR libstdc++/63497
+ include/bits/regex_executor.tcc (_Executor::_M_dfs,
+ _Executor::_M_word_boundary): Avoid dereferecing _M_current at _M_end
+ or other invalid position.
+
+2014-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Backport from mainline
+ 2014-09-10 Tony Wang <tony.wang@arm.com>
+
+ PR target/56846
+ * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION):
+ Return with CONTINUE_UNWINDING when the state pattern
+ contains: _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND
+
+2014-10-30 David Edelsohn <dje.gcc@gmail.com>
Backported from mainline.
2014-10-30 David Edelsohn <dje.gcc@gmail.com>
_M_dfs<__match_mode>(__state._M_next);
break;
case _S_opcode_match:
+ if (_M_current == _M_end)
+ break;
if (__dfs_mode)
{
- if (_M_current != _M_end && __state._M_matches(*_M_current))
+ if (__state._M_matches(*_M_current))
{
++_M_current;
_M_dfs<__match_mode>(__state._M_next);
bool _Executor<_BiIter, _Alloc, _TraitsT, __dfs_mode>::
_M_word_boundary(_State<_TraitsT> __state) const
{
- // By definition.
- bool __ans = false;
- auto __pre = _M_current;
- --__pre;
- if (!(_M_at_begin() && _M_at_end()))
+ bool __left_is_word = false;
+ if (_M_current != _M_begin
+ || (_M_flags & regex_constants::match_prev_avail))
{
- if (_M_at_begin())
- __ans = _M_is_word(*_M_current)
- && !(_M_flags & regex_constants::match_not_bow);
- else if (_M_at_end())
- __ans = _M_is_word(*__pre)
- && !(_M_flags & regex_constants::match_not_eow);
- else
- __ans = _M_is_word(*_M_current)
- != _M_is_word(*__pre);
+ auto __prev = _M_current;
+ if (_M_is_word(*std::prev(__prev)))
+ __left_is_word = true;
}
- return __ans;
+ bool __right_is_word =
+ _M_current != _M_end && _M_is_word(*_M_current);
+
+ if (__left_is_word == __right_is_word)
+ return false;
+ if (__left_is_word && !(_M_flags & regex_constants::match_not_eow))
+ return true;
+ if (__right_is_word && !(_M_flags & regex_constants::match_not_bow))
+ return true;
+ return false;
}
_GLIBCXX_END_NAMESPACE_VERSION
template<typename _RAIter, typename _Function>
_Function
__for_each_switch(_RAIter __begin, _RAIter __end,
- _Function __f, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ _Function __f, random_access_iterator_tag,
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
typename iterator_traits<_RAIter>::difference_type
__count_switch(_RAIter __begin, _RAIter __end,
const _Tp& __value, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_unbalanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
typedef iterator_traits<_RAIter> _TraitsType;
typedef typename _TraitsType::value_type _ValueType;
typename iterator_traits<_RAIter>::difference_type
__count_if_switch(_RAIter __begin, _RAIter __end,
_Predicate __pred, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_unbalanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
typedef iterator_traits<_RAIter> _TraitsType;
typedef typename _TraitsType::value_type _ValueType;
__transform1_switch(_RAIter1 __begin, _RAIter1 __end,
_RAIter2 __result, _UnaryOperation __unary_op,
random_access_iterator_tag, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
_RAIter3 __result, _BinaryOperation __binary_op,
random_access_iterator_tag, random_access_iterator_tag,
random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
(__end1 - __begin1) >=
__replace_switch(_RAIter __begin, _RAIter __end,
const _Tp& __old_value, const _Tp& __new_value,
random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
// XXX parallel version is where?
replace(__begin, __end, __old_value, __new_value,
__replace_if_switch(_RAIter __begin, _RAIter __end,
_Predicate __pred, const _Tp& __new_value,
random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
void
__generate_switch(_RAIter __begin, _RAIter __end,
_Generator __gen, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
inline _RAIter
__generate_n_switch(_RAIter __begin, _Size __n, _Generator __gen,
random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
// XXX parallel version is where?
return generate_n(__begin, __n, __gen, __gnu_parallel::sequential_tag());
_RAIter
__max_element_switch(_RAIter __begin, _RAIter __end,
_Compare __comp, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
_RAIter
__min_element_switch(_RAIter __begin, _RAIter __end,
_Compare __comp, random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
__accumulate_switch(__RAIter __begin, __RAIter __end,
_Tp __init, _BinaryOperation __binary_op,
random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_unbalanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
_BinaryFunction2 __binary_op2,
random_access_iterator_tag,
random_access_iterator_tag,
- __gnu_parallel::_Parallelism __parallelism_tag
- = __gnu_parallel::parallel_unbalanced)
+ __gnu_parallel::_Parallelism __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION((__last1 - __first1)
>= __gnu_parallel::_Settings::get().
random_access_iterator_tag,
random_access_iterator_tag,
__gnu_parallel::_Parallelism
- __parallelism_tag
- = __gnu_parallel::parallel_balanced)
+ __parallelism_tag)
{
if (_GLIBCXX_PARALLEL_CONDITION(
static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin)
projects / platform / upstream / gcc49.git / commitdiff