pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")

Fixes: 0bd50d719b00 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers")
Signed-off-by: Grace Kao <grace.kao@intel.com>
Reported-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 4c74fdd..1093a61 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
        struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
        struct irq_chip *chip = irq_desc_get_chip(desc);
        unsigned long pending;
+       unsigned long flags;
        u32 intr_line;
 
        chained_irq_enter(chip, desc);
 
+       raw_spin_lock_irqsave(&chv_lock, flags);
        pending = readl(pctrl->regs + CHV_INTSTAT);
+       raw_spin_unlock_irqrestore(&chv_lock, flags);
+
        for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
                unsigned int irq, offset;