radeon_screen.c \
radeon_screen.h \
radeon_bo_legacy.h \
- radeon_buffer.h
+ radeon_buffer.h \
+ common_context.h
##### TARGETS #####
void r200EmitAOS( r200ContextPtr rmesa,
- struct r200_dma_region **component,
+ struct radeon_dma_region **component,
GLuint nr,
GLuint offset )
{
(drmTextureRegionPtr)rmesa->sarea->tex_list[i],
& rmesa->sarea->tex_age[i],
& rmesa->swapped,
- sizeof( r200TexObj ),
+ sizeof( radeonTexObj ),
(destroy_texture_object_t *) r200DestroyTexObj );
}
rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
#error This driver requires a newer libdrm to compile
#endif
+#include "common_context.h"
+
struct r200_context;
typedef struct r200_context r200ContextRec;
typedef struct r200_context *r200ContextPtr;
-/* This union is used to avoid warnings/miscompilation
- with float to uint32_t casts due to strict-aliasing */
-typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
-
#include "r200_lock.h"
#include "radeon_screen.h"
#include "main/mm.h"
-/* Flags for software fallback cases */
-/* See correponding strings in r200_swtcl.c */
-#define R200_FALLBACK_TEXTURE 0x01
-#define R200_FALLBACK_DRAW_BUFFER 0x02
-#define R200_FALLBACK_STENCIL 0x04
-#define R200_FALLBACK_RENDER_MODE 0x08
-#define R200_FALLBACK_DISABLE 0x10
-#define R200_FALLBACK_BORDER_MODE 0x20
-
-/* The blit width for texture uploads
- */
-#define BLIT_WIDTH_BYTES 1024
-
-/* Use the templated vertex format:
- */
-#define COLOR_IS_RGBA
-#define TAG(x) r200##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
-
typedef void (*r200_tri_func)( r200ContextPtr,
- r200Vertex *,
- r200Vertex *,
- r200Vertex * );
+ radeonVertex *,
+ radeonVertex *,
+ radeonVertex * );
typedef void (*r200_line_func)( r200ContextPtr,
- r200Vertex *,
- r200Vertex * );
+ radeonVertex *,
+ radeonVertex * );
typedef void (*r200_point_func)( r200ContextPtr,
- r200Vertex * );
+ radeonVertex * );
struct r200_vertex_program {
int fogmode;
};
-struct r200_colorbuffer_state {
- GLuint clear;
-#if 000
- GLint drawOffset, drawPitch;
-#endif
- int roundEnable;
-};
-
-
-struct r200_depthbuffer_state {
- GLuint clear;
- GLfloat scale;
-};
-
-#if 000
-struct r200_pixel_state {
- GLint readOffset, readPitch;
-};
-#endif
-
-struct r200_scissor_state {
- drm_clip_rect_t rect;
- GLboolean enabled;
-
- GLuint numClipRects; /* Cliprects active */
- GLuint numAllocedClipRects; /* Cliprects available */
- drm_clip_rect_t *pClipRects;
-};
-
-struct r200_stencilbuffer_state {
- GLboolean hwBuffer;
- GLuint clear; /* rb3d_stencilrefmask value */
-};
-
-struct r200_stipple_state {
- GLuint mask[32];
-};
-
-
-
-#define TEX_0 0x1
-#define TEX_1 0x2
-#define TEX_2 0x4
-#define TEX_3 0x8
-#define TEX_4 0x10
-#define TEX_5 0x20
-#define TEX_ALL 0x3f
-
-typedef struct r200_tex_obj r200TexObj, *r200TexObjPtr;
-
-/* Texture object in locally shared texture space.
- */
-struct r200_tex_obj {
- driTextureObject base;
-
- GLuint bufAddr; /* Offset to start of locally
- shared texture block */
-
- GLuint dirty_state; /* Flags (1 per texunit) for
- whether or not this texobj
- has dirty hardware state
- (pp_*) that needs to be
- brought into the
- texunit. */
-
- drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
- /* Six, for the cube faces */
- GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
-
- GLuint pp_txfilter; /* hardware register values */
- GLuint pp_txformat;
- GLuint pp_txformat_x;
- GLuint pp_txoffset; /* Image location in texmem.
- All cube faces follow. */
- GLuint pp_txsize; /* npot only */
- GLuint pp_txpitch; /* npot only */
- GLuint pp_border_color;
- GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
-
- GLboolean border_fallback;
-
- GLuint tile_bits; /* hw texture tile bits used on this texture */
-};
+#define R200_TEX_ALL 0x3f
struct r200_texture_env_state {
- r200TexObjPtr texobj;
+ radeonTexObjPtr texobj;
GLuint outputreg;
GLuint unitneeded;
};
struct r200_state_atom *next, *prev;
const char *name; /* for debug */
int cmd_size; /* size in bytes */
+ GLuint is_tcl;
GLuint idx;
int *cmd; /* one or more cmd's */
int *lastcmd; /* one or more cmd's */
GLboolean dirty;
GLboolean (*check)( GLcontext *, int ); /* is this state active? */
};
-
-
/* Trying to keep these relatively short as the variables are becoming
* extravagently long. Drop the driver name prefix off the front of
struct r200_state {
/* Derived state for internal purposes:
*/
- struct r200_colorbuffer_state color;
- struct r200_depthbuffer_state depth;
+ struct radeon_colorbuffer_state color;
+ struct radeon_depthbuffer_state depth;
#if 00
struct r200_pixel_state pixel;
#endif
- struct r200_scissor_state scissor;
- struct r200_stencilbuffer_state stencil;
- struct r200_stipple_state stipple;
+ struct radeon_scissor_state scissor;
+ struct radeon_stencilbuffer_state stencil;
+ struct radeon_stipple_state stipple;
struct r200_texture_state texture;
GLuint envneeded;
};
-/* Need refcounting on dma buffers:
- */
-struct r200_dma_buffer {
- int refcount; /* the number of retained regions in buf */
- drmBufPtr buf;
-};
-
#define GET_START(rvb) (rmesa->r200Screen->gart_buffer_offset + \
(rvb)->address - rmesa->dma.buf0_address + \
(rvb)->start)
-/* A retained region, eg vertices for indexed vertices.
- */
-struct r200_dma_region {
- struct r200_dma_buffer *buf;
- char *address; /* == buf->address */
- int start, end, ptr; /* offsets from start of buf */
- int aos_start;
- int aos_stride;
- int aos_size;
-};
-
-
-struct r200_dma {
- /* Active dma region. Allocations for vertices and retained
- * regions come from here. Also used for emitting random vertices,
- * these may be flushed by calling flush_current();
- */
- struct r200_dma_region current;
-
- void (*flush)( r200ContextPtr );
-
- char *buf0_address; /* start of buf[0], for index calcs */
- GLuint nr_released_bufs; /* flush after so many buffers released */
-};
-
struct r200_dri_mirror {
__DRIcontextPrivate *context; /* DRI context */
__DRIscreenPrivate *screen; /* DRI screen */
GLuint hw_primitive;
/* hw can handle 12 components max */
- struct r200_dma_region *aos_components[12];
+ struct radeon_dma_region *aos_components[12];
GLuint nr_aos_components;
GLuint *Elts;
- struct r200_dma_region indexed_verts;
- struct r200_dma_region vertex_data[15];
+ struct radeon_dma_region indexed_verts;
+ struct radeon_dma_region vertex_data[15];
};
*/
GLboolean needproj;
- struct r200_dma_region indexed_verts;
-};
-
-
-struct r200_ioctl {
- GLuint vertex_offset;
- GLuint vertex_size;
+ struct radeon_dma_region indexed_verts;
};
-#define R200_MAX_PRIMS 64
-
-
-
-struct r200_prim {
- GLuint start;
- GLuint end;
- GLuint prim;
-};
/* A maximum total of 29 elements per vertex: 3 floats for position, 3
* floats for normal, 4 floats for color, 4 bytes for secondary color,
/* Vertex buffers
*/
- struct r200_ioctl ioctl;
- struct r200_dma dma;
+ struct radeon_ioctl ioctl;
+ struct radeon_dma dma;
struct r200_store store;
/* A full state emit as of the first state emit in the main store, in case
* the context is lost.
#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx))
-static INLINE GLuint r200PackColor( GLuint cpp,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a )
-{
- switch ( cpp ) {
- case 2:
- return PACK_COLOR_565( r, g, b );
- case 4:
- return PACK_COLOR_8888( a, r, g, b );
- default:
- return 0;
- }
-}
-
-
extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv );
extern GLboolean r200CreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
CLAMPED_FLOAT_TO_UBYTE(con_byte[2], ctx->ATIFragmentShader.GlobalConstants[i][2]);
CLAMPED_FLOAT_TO_UBYTE(con_byte[3], ctx->ATIFragmentShader.GlobalConstants[i][3]);
}
- rmesa->hw.atf.cmd[ATF_TFACTOR_0 + i] = r200PackColor (
+ rmesa->hw.atf.cmd[ATF_TFACTOR_0 + i] = radeonPackColor (
4, con_byte[0], con_byte[1], con_byte[2], con_byte[3] );
}
}
void r200RefillCurrentDmaRegion( r200ContextPtr rmesa )
{
- struct r200_dma_buffer *dmabuf;
+ struct radeon_dma_buffer *dmabuf;
int fd = rmesa->dri.fd;
int index = 0;
int size = 0;
if (R200_DEBUG & DEBUG_DMA)
fprintf(stderr, "Allocated buffer %d\n", index);
- dmabuf = CALLOC_STRUCT( r200_dma_buffer );
+ dmabuf = CALLOC_STRUCT( radeon_dma_buffer );
dmabuf->buf = &rmesa->r200Screen->buffers->list[index];
dmabuf->refcount = 1;
}
void r200ReleaseDmaRegion( r200ContextPtr rmesa,
- struct r200_dma_region *region,
+ struct radeon_dma_region *region,
const char *caller )
{
if (R200_DEBUG & DEBUG_IOCTL)
* space in current, grab a new buffer (and discard what was left of current)
*/
void r200AllocDmaRegion( r200ContextPtr rmesa,
- struct r200_dma_region *region,
+ struct radeon_dma_region *region,
int bytes,
int alignment )
{
GLuint min_nr );
extern void r200EmitAOS( r200ContextPtr rmesa,
- struct r200_dma_region **regions,
+ struct radeon_dma_region **regions,
GLuint n,
GLuint offset );
extern void r200RefillCurrentDmaRegion( r200ContextPtr rmesa );
extern void r200AllocDmaRegion( r200ContextPtr rmesa,
- struct r200_dma_region *region,
+ struct radeon_dma_region *region,
int bytes,
int alignment );
extern void r200ReleaseDmaRegion( r200ContextPtr rmesa,
- struct r200_dma_region *region,
+ struct radeon_dma_region *region,
const char *caller );
extern void r200CopyBuffer( __DRIdrawablePrivate *drawable,
*
*/
static void emit_ubyte_rgba3( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
}
static void emit_ubyte_rgba4( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
static void emit_ubyte_rgba( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int size,
int stride,
static void emit_vecfog( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
static void emit_vec4( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
static void emit_vec8( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
}
static void emit_vec12( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
}
static void emit_vec16( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int stride,
int count )
static void emit_vector( GLcontext *ctx,
- struct r200_dma_region *rvb,
+ struct radeon_dma_region *rvb,
char *data,
int size,
int stride,
{
r200ContextPtr rmesa = R200_CONTEXT( ctx );
struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb;
- struct r200_dma_region **component = rmesa->tcl.aos_components;
+ struct radeon_dma_region **component = rmesa->tcl.aos_components;
GLuint nr = 0;
GLuint vfmt0 = 0, vfmt1 = 0;
GLuint count = VB->Count;
CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
if (rmesa->r200Screen->drmSupportsBlendColor)
- rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = r200PackColor( 4, color[0], color[1], color[2], color[3] );
+ rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] );
}
/**
case GL_FOG_COLOR:
R200_STATECHANGE( rmesa, ctx );
UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color );
- i = r200PackColor( 4, col[0], col[1], col[2], 0 );
+ i = radeonPackColor( 4, col[0], col[1], col[2], 0 );
rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_COLOR_MASK;
rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= i;
break;
GLboolean b, GLboolean a )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
- GLuint mask = r200PackColor( rmesa->r200Screen->cpp,
+ GLuint mask = radeonPackColor( rmesa->r200Screen->cpp,
ctx->Color.ColorMask[RCOMP],
ctx->Color.ColorMask[GCOMP],
ctx->Color.ColorMask[BCOMP],
CLAMPED_FLOAT_TO_UBYTE(color[1], c[1]);
CLAMPED_FLOAT_TO_UBYTE(color[2], c[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], c[3]);
- rmesa->state.color.clear = r200PackColor( rmesa->r200Screen->cpp,
+ rmesa->state.color.clear = radeonPackColor( rmesa->r200Screen->cpp,
color[0], color[1],
color[2], color[3] );
}
rmesa->dma.flush = NULL;
if (rmesa->dma.current.buf) {
- struct r200_dma_region *current = &rmesa->dma.current;
+ struct radeon_dma_region *current = &rmesa->dma.current;
GLuint current_offset = (rmesa->r200Screen->gart_buffer_offset +
current->buf->buf->idx * RADEON_BUFFER_SIZE +
current->start);
#define LOCAL_VARS \
r200ContextPtr rmesa = R200_CONTEXT(ctx); \
const char *r200verts = (char *)rmesa->swtcl.verts;
-#define VERT(x) (r200Vertex *)(r200verts + ((x) * vertsize * sizeof(int)))
-#define VERTEX r200Vertex
+#define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int)))
+#define VERTEX radeonVertex
#define DO_DEBUG_VERTS (1 && (R200_DEBUG & DEBUG_VERTS))
#undef TAG
#define VERT_SET_RGBA( v, c ) \
do { \
- r200_color_t *color = (r200_color_t *)&((v)->ui[coloroffset]); \
+ radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
#define VERT_SET_SPEC( v, c ) \
do { \
if (specoffset) { \
- r200_color_t *spec = (r200_color_t *)&((v)->ui[specoffset]); \
+ radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
#define VERT_COPY_SPEC( v0, v1 ) \
do { \
if (specoffset) { \
- r200_color_t *spec0 = (r200_color_t *)&((v0)->ui[specoffset]); \
- r200_color_t *spec1 = (r200_color_t *)&((v1)->ui[specoffset]); \
+ radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
+ radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
spec0->red = spec1->red; \
spec0->green = spec1->green; \
spec0->blue = spec1->blue; \
r200ContextPtr rmesa = R200_CONTEXT(ctx);
const GLfloat *rc = ctx->Current.RasterColor;
GLint row, col;
- r200Vertex vert;
+ radeonVertex vert;
GLuint orig_vte;
GLuint h;
GLuint count );
extern void r200_translate_vertex( GLcontext *ctx,
- const r200Vertex *src,
+ const radeonVertex *src,
SWvertex *dst );
-extern void r200_print_vertex( GLcontext *ctx, const r200Vertex *v );
+extern void r200_print_vertex( GLcontext *ctx, const radeonVertex *v );
extern void r200_import_float_colors( GLcontext *ctx );
extern void r200_import_float_spec_colors( GLcontext *ctx );
* \param twrap Wrap mode for the \a t texture coordinate
*/
-static void r200SetTexWrap( r200TexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap )
+static void r200SetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap )
{
GLboolean is_clamp = GL_FALSE;
GLboolean is_clamp_to_border = GL_FALSE;
t->border_fallback = (is_clamp && is_clamp_to_border);
}
-static void r200SetTexMaxAnisotropy( r200TexObjPtr t, GLfloat max )
+static void r200SetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
{
t->pp_txfilter &= ~R200_MAX_ANISO_MASK;
* \param magf Texture magnification mode
*/
-static void r200SetTexFilter( r200TexObjPtr t, GLenum minf, GLenum magf )
+static void r200SetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
{
GLuint anisotropy = (t->pp_txfilter & R200_MAX_ANISO_MASK);
}
}
-static void r200SetTexBorderColor( r200TexObjPtr t, GLubyte c[4] )
+static void r200SetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
{
- t->pp_border_color = r200PackColor( 4, c[0], c[1], c[2], c[3] );
+ t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
}
* texture after it was swapped out or teximaged again.
*/
-static r200TexObjPtr r200AllocTexObj( struct gl_texture_object *texObj )
+static radeonTexObjPtr r200AllocTexObj( struct gl_texture_object *texObj )
{
- r200TexObjPtr t;
+ radeonTexObjPtr t;
- t = CALLOC_STRUCT( r200_tex_obj );
+ t = CALLOC_STRUCT( radeon_tex_obj );
texObj->DriverData = t;
if ( t != NULL ) {
if ( R200_DEBUG & DEBUG_TEXTURE ) {
GLubyte c[4];
GLuint envColor;
UNCLAMPED_FLOAT_TO_RGBA_CHAN( c, texUnit->EnvColor );
- envColor = r200PackColor( 4, c[0], c[1], c[2], c[3] );
+ envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) {
R200_STATECHANGE( rmesa, tf );
rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor;
struct gl_texture_object *texObj,
GLenum pname, const GLfloat *params )
{
- r200TexObjPtr t = (r200TexObjPtr) texObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr) texObj->DriverData;
if ( R200_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
fprintf( stderr, "%s( %s )\n", __FUNCTION__,
/* Mark this texobj as dirty (one bit per tex unit)
*/
- t->dirty_state = TEX_ALL;
+ t->dirty_state = R200_TEX_ALL;
}
extern void r200UpdateTextureState( GLcontext *ctx );
-extern int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face );
+extern int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face );
-extern void r200DestroyTexObj( r200ContextPtr rmesa, r200TexObjPtr t );
+extern void r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t );
extern void r200InitTextureFuncs( struct dd_function_table *functions );
* include NULLing out hardware state that points to the texture.
*/
void
-r200DestroyTexObj( r200ContextPtr rmesa, r200TexObjPtr t )
+r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t )
{
if ( R200_DEBUG & DEBUG_TEXTURE ) {
fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__,
static void r200UploadGARTClientSubImage( r200ContextPtr rmesa,
- r200TexObjPtr t,
+ radeonTexObjPtr t,
struct gl_texture_image *texImage,
GLint hwlevel,
GLint x, GLint y,
}
static void r200UploadRectSubImage( r200ContextPtr rmesa,
- r200TexObjPtr t,
+ radeonTexObjPtr t,
struct gl_texture_image *texImage,
GLint x, GLint y,
GLint width, GLint height )
/* Data not in GART memory, or bad pitch.
*/
for (done = 0; done < height ; ) {
- struct r200_dma_region region;
+ struct radeon_dma_region region;
int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch );
int src_pitch;
char *tex;
* Upload the texture image associated with texture \a t at the specified
* level at the address relative to \a start.
*/
-static void uploadSubImage( r200ContextPtr rmesa, r200TexObjPtr t,
+static void uploadSubImage( r200ContextPtr rmesa, radeonTexObjPtr t,
GLint hwlevel,
GLint x, GLint y, GLint width, GLint height,
GLuint face )
* \param face Cube map face to be uploaded. Zero for non-cube maps.
*/
-int r200UploadTexImages( r200ContextPtr rmesa, r200TexObjPtr t, GLuint face )
+int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face )
{
const int numLevels = t->base.lastLevel - t->base.firstLevel + 1;
/* Mark this texobj as dirty on all units:
*/
- t->dirty_state = TEX_ALL;
+ t->dirty_state = R200_TEX_ALL;
}
/* Let the world know we've used this memory recently.
static void r200SetTexImages( r200ContextPtr rmesa,
struct gl_texture_object *tObj )
{
- r200TexObjPtr t = (r200TexObjPtr)tObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData;
const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel];
GLint curOffset, blitWidth;
GLint i, texelBytes;
t->pp_txpitch -= 32;
}
- t->dirty_state = TEX_ALL;
+ t->dirty_state = R200_TEX_ALL;
/* FYI: r200UploadTexImages( rmesa, t ) used to be called here */
}
r200ContextPtr rmesa = pDRICtx->driverPrivate;
struct gl_texture_object *tObj =
_mesa_lookup_texture(rmesa->glCtx, texname);
- r200TexObjPtr t;
+ radeonTexObjPtr t;
if (!tObj)
return;
- t = (r200TexObjPtr) tObj->DriverData;
+ t = (radeonTexObjPtr) tObj->DriverData;
t->image_override = GL_TRUE;
static void import_tex_obj_state( r200ContextPtr rmesa,
int unit,
- r200TexObjPtr texobj )
+ radeonTexObjPtr texobj )
{
/* do not use RADEON_DB_STATE to avoid stale texture caches */
int *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
r200ContextPtr rmesa = R200_CONTEXT(ctx);
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
struct gl_texture_object *tObj = texUnit->_Current;
- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
/* Need to load the 2d images associated with this unit.
*/
if ( t->base.dirty_images[0] ) {
R200_FIREVERTICES( rmesa );
r200SetTexImages( rmesa, tObj );
- r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 );
+ r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
if ( !t->base.memBlock && !t->image_override )
return GL_FALSE;
}
r200ContextPtr rmesa = R200_CONTEXT(ctx);
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
struct gl_texture_object *tObj = texUnit->_Current;
- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
/* Need to load the 3d images associated with this unit.
*/
if ( t->base.dirty_images[0] ) {
R200_FIREVERTICES( rmesa );
r200SetTexImages( rmesa, tObj );
- r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 );
+ r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
if ( !t->base.memBlock )
return GL_FALSE;
}
r200ContextPtr rmesa = R200_CONTEXT(ctx);
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
struct gl_texture_object *tObj = texUnit->_Current;
- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
GLuint face;
/* Need to load the 2d images associated with this unit.
/* upload (per face) */
for (face = 0; face < 6; face++) {
if (t->base.dirty_images[face]) {
- r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, face );
+ r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, face );
}
}
r200ContextPtr rmesa = R200_CONTEXT(ctx);
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
struct gl_texture_object *tObj = texUnit->_Current;
- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
if (!(t->pp_txformat & R200_TXFORMAT_NON_POWER2)) {
t->pp_txformat |= R200_TXFORMAT_NON_POWER2;
if ( t->base.dirty_images[0] ) {
R200_FIREVERTICES( rmesa );
r200SetTexImages( rmesa, tObj );
- r200UploadTexImages( rmesa, (r200TexObjPtr) tObj->DriverData, 0 );
+ r200UploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
if ( !t->base.memBlock &&
!t->image_override &&
!rmesa->prefer_gart_client_texturing )
r200ContextPtr rmesa = R200_CONTEXT(ctx);
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
struct gl_texture_object *tObj = texUnit->_Current;
- r200TexObjPtr t = (r200TexObjPtr) tObj->DriverData;
+ radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
/* Fallback if there's a texture border */
if ( tObj->Image[0][tObj->BaseLevel]->Border > 0 )
--- /dev/null
+/* This union is used to avoid warnings/miscompilation
+ with float to uint32_t casts due to strict-aliasing */
+typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
+
+#include "main/mm.h"
+#include "math/m_vector.h"
+
+
+#define TEX_0 0x1
+#define TEX_1 0x2
+#define TEX_2 0x4
+#define TEX_3 0x8
+#define TEX_4 0x10
+#define TEX_5 0x20
+
+/* Rasterizing fallbacks */
+/* See correponding strings in r200_swtcl.c */
+#define RADEON_FALLBACK_TEXTURE 0x0001
+#define RADEON_FALLBACK_DRAW_BUFFER 0x0002
+#define RADEON_FALLBACK_STENCIL 0x0004
+#define RADEON_FALLBACK_RENDER_MODE 0x0008
+#define RADEON_FALLBACK_BLEND_EQ 0x0010
+#define RADEON_FALLBACK_BLEND_FUNC 0x0020
+#define RADEON_FALLBACK_DISABLE 0x0040
+#define RADEON_FALLBACK_BORDER_MODE 0x0080
+
+#define R200_FALLBACK_TEXTURE 0x01
+#define R200_FALLBACK_DRAW_BUFFER 0x02
+#define R200_FALLBACK_STENCIL 0x04
+#define R200_FALLBACK_RENDER_MODE 0x08
+#define R200_FALLBACK_DISABLE 0x10
+#define R200_FALLBACK_BORDER_MODE 0x20
+
+/* The blit width for texture uploads
+ */
+#define BLIT_WIDTH_BYTES 1024
+
+/* Use the templated vertex format:
+ */
+#define COLOR_IS_RGBA
+#define TAG(x) radeon##x
+#include "tnl_dd/t_dd_vertex.h"
+#undef TAG
+
+struct radeon_colorbuffer_state {
+ GLuint clear;
+ int roundEnable;
+};
+
+struct radeon_depthbuffer_state {
+ GLuint clear;
+ GLfloat scale;
+};
+
+struct radeon_scissor_state {
+ drm_clip_rect_t rect;
+ GLboolean enabled;
+
+ GLuint numClipRects; /* Cliprects active */
+ GLuint numAllocedClipRects; /* Cliprects available */
+ drm_clip_rect_t *pClipRects;
+};
+
+struct radeon_stencilbuffer_state {
+ GLboolean hwBuffer;
+ GLuint clear; /* rb3d_stencilrefmask value */
+};
+
+struct radeon_stipple_state {
+ GLuint mask[32];
+};
+
+struct radeon_state_atom {
+ struct radeon_state_atom *next, *prev;
+ const char *name; /* for debug */
+ int cmd_size; /* size in bytes */
+ GLuint is_tcl;
+ int *cmd; /* one or more cmd's */
+ int *lastcmd; /* one or more cmd's */
+ GLboolean dirty; /* dirty-mark in emit_state_list */
+ GLboolean(*check) (GLcontext *); /* is this state active? */
+};
+
+typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
+
+/* Texture object in locally shared texture space.
+ */
+struct radeon_tex_obj {
+ driTextureObject base;
+
+ GLuint bufAddr; /* Offset to start of locally
+ shared texture block */
+
+ GLuint dirty_state; /* Flags (1 per texunit) for
+ whether or not this texobj
+ has dirty hardware state
+ (pp_*) that needs to be
+ brought into the
+ texunit. */
+
+ drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
+ /* Six, for the cube faces */
+
+ GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
+
+ GLuint pp_txfilter; /* hardware register values */
+ GLuint pp_txformat;
+ GLuint pp_txformat_x;
+ GLuint pp_txoffset; /* Image location in texmem.
+ All cube faces follow. */
+ GLuint pp_txsize; /* npot only */
+ GLuint pp_txpitch; /* npot only */
+ GLuint pp_border_color;
+ GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
+
+ GLboolean border_fallback;
+
+ GLuint tile_bits; /* hw texture tile bits used on this texture */
+};
+
+/* Need refcounting on dma buffers:
+ */
+struct radeon_dma_buffer {
+ int refcount; /* the number of retained regions in buf */
+ drmBufPtr buf;
+};
+
+/* A retained region, eg vertices for indexed vertices.
+ */
+struct radeon_dma_region {
+ struct radeon_dma_buffer *buf;
+ char *address; /* == buf->address */
+ int start, end, ptr; /* offsets from start of buf */
+ int aos_start;
+ int aos_stride;
+ int aos_size;
+};
+
+
+struct radeon_dma {
+ /* Active dma region. Allocations for vertices and retained
+ * regions come from here. Also used for emitting random vertices,
+ * these may be flushed by calling flush_current();
+ */
+ struct radeon_dma_region current;
+
+ void (*flush)( void * );
+
+ char *buf0_address; /* start of buf[0], for index calcs */
+ GLuint nr_released_bufs; /* flush after so many buffers released */
+};
+
+struct radeon_ioctl {
+ GLuint vertex_offset;
+ GLuint vertex_size;
+};
+
+#define RADEON_MAX_PRIMS 64
+
+struct radeon_prim {
+ GLuint start;
+ GLuint end;
+ GLuint prim;
+};
+
+static INLINE GLuint radeonPackColor(GLuint cpp,
+ GLubyte r, GLubyte g,
+ GLubyte b, GLubyte a)
+{
+ switch (cpp) {
+ case 2:
+ return PACK_COLOR_565(r, g, b);
+ case 4:
+ return PACK_COLOR_8888(a, r, g, b);
+ default:
+ return 0;
+ }
+}
typedef struct radeon_context radeonContextRec;
typedef struct radeon_context *radeonContextPtr;
-/* This union is used to avoid warnings/miscompilation
- with float to uint32_t casts due to strict-aliasing */
-typedef union {
- GLfloat f;
- uint32_t ui32;
-} float_ui32_type;
-
#include "radeon_lock.h"
#include "radeon_screen.h"
-#include "main/mm.h"
-
-#include "math/m_vector.h"
-
-#define TEX_0 0x1
-#define TEX_1 0x2
-#define TEX_2 0x4
-#define TEX_ALL 0x7
-
-/* Rasterizing fallbacks */
-/* See correponding strings in r200_swtcl.c */
-#define RADEON_FALLBACK_TEXTURE 0x0001
-#define RADEON_FALLBACK_DRAW_BUFFER 0x0002
-#define RADEON_FALLBACK_STENCIL 0x0004
-#define RADEON_FALLBACK_RENDER_MODE 0x0008
-#define RADEON_FALLBACK_BLEND_EQ 0x0010
-#define RADEON_FALLBACK_BLEND_FUNC 0x0020
-#define RADEON_FALLBACK_DISABLE 0x0040
-#define RADEON_FALLBACK_BORDER_MODE 0x0080
-
-/* The blit width for texture uploads
- */
-#define BLIT_WIDTH_BYTES 1024
-/* Use the templated vertex format:
- */
-#define COLOR_IS_RGBA
-#define TAG(x) radeon##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
+#include "common_context.h"
+
+#define R100_TEX_ALL 0x7
typedef void (*radeon_tri_func) (radeonContextPtr,
radeonVertex *,
typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
-struct radeon_colorbuffer_state {
- GLuint clear;
- int roundEnable;
-};
-struct radeon_depthbuffer_state {
- GLuint clear;
- GLfloat scale;
-};
-
-struct radeon_scissor_state {
- drm_clip_rect_t rect;
- GLboolean enabled;
-
- GLuint numClipRects; /* Cliprects active */
- GLuint numAllocedClipRects; /* Cliprects available */
- drm_clip_rect_t *pClipRects;
-};
-
-struct radeon_stencilbuffer_state {
- GLboolean hwBuffer;
- GLuint clear; /* rb3d_stencilrefmask value */
-};
-
-struct radeon_stipple_state {
- GLuint mask[32];
-};
/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */
#define RADEON_ST_BIT(unit) \
#define RADEON_Q_BIT(unit) \
(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit))
-typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
-
-/* Texture object in locally shared texture space.
- */
-struct radeon_tex_obj {
- driTextureObject base;
-
- GLuint bufAddr; /* Offset to start of locally
- shared texture block */
-
- GLuint dirty_state; /* Flags (1 per texunit) for
- whether or not this texobj
- has dirty hardware state
- (pp_*) that needs to be
- brought into the
- texunit. */
-
- drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
- /* Six, for the cube faces */
-
- GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
-
- GLuint pp_txfilter; /* hardware register values */
- GLuint pp_txformat;
- GLuint pp_txoffset; /* Image location in texmem.
- All cube faces follow. */
- GLuint pp_txsize; /* npot only */
- GLuint pp_txpitch; /* npot only */
- GLuint pp_border_color;
- GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
-
- GLboolean border_fallback;
-
- GLuint tile_bits; /* hw texture tile bits used on this texture */
-};
-
struct radeon_texture_env_state {
radeonTexObjPtr texobj;
GLenum format;
struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS];
};
-struct radeon_state_atom {
- struct radeon_state_atom *next, *prev;
- const char *name; /* for debug */
- int cmd_size; /* size in bytes */
- GLuint is_tcl;
- int *cmd; /* one or more cmd's */
- int *lastcmd; /* one or more cmd's */
- GLboolean dirty; /* dirty-mark in emit_state_list */
- GLboolean(*check) (GLcontext *); /* is this state active? */
-};
-
/* Trying to keep these relatively short as the variables are becoming
* extravagently long. Drop the driver name prefix off the front of
* everything - I think we know which driver we're in by now, and keep the
struct radeon_texture_state texture;
};
-/* Need refcounting on dma buffers:
- */
-struct radeon_dma_buffer {
- int refcount; /* the number of retained regions in buf */
- drmBufPtr buf;
-};
-
#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
(rvb)->address - rmesa->dma.buf0_address + \
(rvb)->start)
-/* A retained region, eg vertices for indexed vertices.
- */
-struct radeon_dma_region {
- struct radeon_dma_buffer *buf;
- char *address; /* == buf->address */
- int start, end, ptr; /* offsets from start of buf */
- int aos_start;
- int aos_stride;
- int aos_size;
-};
-
-struct radeon_dma {
- /* Active dma region. Allocations for vertices and retained
- * regions come from here. Also used for emitting random vertices,
- * these may be flushed by calling flush_current();
- */
- struct radeon_dma_region current;
-
- void (*flush) (radeonContextPtr);
-
- char *buf0_address; /* start of buf[0], for index calcs */
- GLuint nr_released_bufs; /* flush after so many buffers released */
-};
-
struct radeon_dri_mirror {
__DRIcontextPrivate *context; /* DRI context */
__DRIscreenPrivate *screen; /* DRI screen */
struct radeon_dma_region indexed_verts;
};
-struct radeon_ioctl {
- GLuint vertex_offset;
- GLuint vertex_size;
-};
-#define RADEON_MAX_PRIMS 64
-
-struct radeon_prim {
- GLuint start;
- GLuint end;
- GLuint prim;
-};
/* A maximum total of 20 elements per vertex: 3 floats for position, 3
* floats for normal, 4 floats for color, 4 bytes for secondary color,
#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
-static INLINE GLuint radeonPackColor(GLuint cpp,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a)
-{
- switch (cpp) {
- case 2:
- return PACK_COLOR_565(r, g, b);
- case 4:
- return PACK_COLOR_8888(a, r, g, b);
- default:
- return 0;
- }
-}
#define RADEON_OLD_PACKETS 1
screen->kernel_mm = 1;
screen->chip_flags = 0;
+ ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
+ &screen->irq);
+
ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID,
&device_id);
if (ret) {
/* Mark this texobj as dirty (one bit per tex unit)
*/
- t->dirty_state = TEX_ALL;
+ t->dirty_state = R100_TEX_ALL;
}
/* Mark this texobj as dirty on all units:
*/
- t->dirty_state = TEX_ALL;
+ t->dirty_state = R100_TEX_ALL;
}
t->pp_txpitch -= 32;
}
- t->dirty_state = TEX_ALL;
+ t->dirty_state = R100_TEX_ALL;
/* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */
}
projects / profile / ivi / mesa.git / commitdiff