radeon/vce: adapt new firmware interface changes
authorChristian König <christian.koenig@amd.com>
Thu, 26 Mar 2015 09:00:09 +0000 (10:00 +0100)
committerChristian König <christian.koenig@amd.com>
Fri, 22 May 2015 08:17:24 +0000 (10:17 +0200)
v2: make this also compatible with original released firmware
v3 (chk): switch to original idea of separate files for fw versions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2)
src/gallium/drivers/radeon/Makefile.sources
src/gallium/drivers/radeon/radeon_vce.c
src/gallium/drivers/radeon/radeon_vce.h
src/gallium/drivers/radeon/radeon_vce_50.c [new file with mode: 0644]

index c655fe5..f63790c 100644 (file)
@@ -12,6 +12,7 @@ C_SOURCES := \
        radeon_uvd.c \
        radeon_uvd.h \
        radeon_vce_40_2_2.c \
+       radeon_vce_50.c \
        radeon_vce.c \
        radeon_vce.h \
        radeon_video.c \
index 9913c8b..a656737 100644 (file)
 #include "radeon_video.h"
 #include "radeon_vce.h"
 
+#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
+#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
+#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
+
 /**
  * flush commands to the hardware
  */
@@ -444,7 +448,19 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
 
        reset_cpb(enc);
 
-       radeon_vce_40_2_2_init(enc);
+       switch (rscreen->info.vce_fw_version) {
+       case FW_40_2_2:
+               radeon_vce_40_2_2_init(enc);
+               break;
+
+       case FW_50_0_1:
+       case FW_50_1_2:
+               radeon_vce_50_init(enc);
+               break;
+
+       default:
+               goto error;
+       }
 
        return &enc->base;
 
@@ -464,5 +480,7 @@ error:
  */
 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
 {
-       return rscreen->info.vce_fw_version == ((40 << 24) | (2 << 16) | (2 << 8));
+       return rscreen->info.vce_fw_version == FW_40_2_2 ||
+               rscreen->info.vce_fw_version == FW_50_0_1 ||
+               rscreen->info.vce_fw_version == FW_50_1_2;
 }
index 9fcaeca..8319ef4 100644 (file)
@@ -121,4 +121,7 @@ bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
 /* init vce fw 40.2.2 specific callbacks */
 void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
 
+/* init vce fw 50 specific callbacks */
+void radeon_vce_50_init(struct rvce_encoder *enc);
+
 #endif
diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c b/src/gallium/drivers/radeon/radeon_vce_50.c
new file mode 100644 (file)
index 0000000..84a2bfb
--- /dev/null
@@ -0,0 +1,228 @@
+/**************************************************************************
+ *
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/*
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ *
+ */
+
+#include <stdio.h>
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "r600_pipe_common.h"
+#include "radeon_video.h"
+#include "radeon_vce.h"
+
+static void task_info(struct rvce_encoder *enc, uint32_t taskOperation)
+{
+       RVCE_BEGIN(0x00000002); // task info
+       RVCE_CS(0xffffffff); // offsetOfNextTaskInfo
+       RVCE_CS(taskOperation); // taskOperation
+       RVCE_CS(0x00000000); // referencePictureDependency
+       RVCE_CS(0x00000000); // collocateFlagDependency
+       RVCE_CS(0x00000000); // feedbackIndex
+       RVCE_CS(0x00000000); // videoBitstreamRingIndex
+       RVCE_END();
+}
+
+static void rate_control(struct rvce_encoder *enc)
+{
+       RVCE_BEGIN(0x04000005); // rate control
+       RVCE_CS(enc->pic.rate_ctrl.rate_ctrl_method); // encRateControlMethod
+       RVCE_CS(enc->pic.rate_ctrl.target_bitrate); // encRateControlTargetBitRate
+       RVCE_CS(enc->pic.rate_ctrl.peak_bitrate); // encRateControlPeakBitRate
+       RVCE_CS(enc->pic.rate_ctrl.frame_rate_num); // encRateControlFrameRateNum
+       RVCE_CS(0x00000000); // encGOPSize
+       RVCE_CS(enc->pic.quant_i_frames); // encQP_I
+       RVCE_CS(enc->pic.quant_p_frames); // encQP_P
+       RVCE_CS(enc->pic.quant_b_frames); // encQP_B
+       RVCE_CS(enc->pic.rate_ctrl.vbv_buffer_size); // encVBVBufferSize
+       RVCE_CS(enc->pic.rate_ctrl.frame_rate_den); // encRateControlFrameRateDen
+       RVCE_CS(0x00000000); // encVBVBufferLevel
+       RVCE_CS(0x00000000); // encMaxAUSize
+       RVCE_CS(0x00000000); // encQPInitialMode
+       RVCE_CS(enc->pic.rate_ctrl.target_bits_picture); // encTargetBitsPerPicture
+       RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_integer); // encPeakBitsPerPictureInteger
+       RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_fraction); // encPeakBitsPerPictureFractional
+       RVCE_CS(0x00000000); // encMinQP
+       RVCE_CS(0x00000033); // encMaxQP
+       RVCE_CS(0x00000000); // encSkipFrameEnable
+       RVCE_CS(0x00000000); // encFillerDataEnable
+       RVCE_CS(0x00000000); // encEnforceHRD
+       RVCE_CS(0x00000000); // encBPicsDeltaQP
+       RVCE_CS(0x00000000); // encReferenceBPicsDeltaQP
+       RVCE_CS(0x00000000); // encRateControlReInitDisable
+       RVCE_CS(0x00000000); // encLCVBRInitQPFlag
+       RVCE_CS(0x00000000); // encLCVBRSATDBasedNonlinearBitBudgetFlag
+       RVCE_END();
+}
+
+static void encode(struct rvce_encoder *enc)
+{
+       int i;
+       unsigned luma_offset, chroma_offset;
+
+       task_info(enc, 0x00000003);
+
+       RVCE_BEGIN(0x05000001); // context buffer
+       RVCE_READWRITE(enc->cpb.res->cs_buf, enc->cpb.res->domains); // encodeContextAddressHi
+       RVCE_CS(0x00000000); // encodeContextAddressLo
+       RVCE_END();
+
+       RVCE_BEGIN(0x05000004); // video bitstream buffer
+       RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT); // videoBitstreamRingAddressHi
+       RVCE_CS(0x00000000); // videoBitstreamRingAddressLo
+       RVCE_CS(enc->bs_size); // videoBitstreamRingSize
+       RVCE_END();
+
+       RVCE_BEGIN(0x03000001); // encode
+       RVCE_CS(enc->pic.frame_num ? 0x0 : 0x11); // insertHeaders
+       RVCE_CS(0x00000000); // pictureStructure
+       RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
+       RVCE_CS(0x00000000); // forceRefreshMap
+       RVCE_CS(0x00000000); // insertAUD
+       RVCE_CS(0x00000000); // endOfSequence
+       RVCE_CS(0x00000000); // endOfStream
+       RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM); // inputPictureLumaAddressHi
+       RVCE_CS(enc->luma->level[0].offset); // inputPictureLumaAddressLo
+       RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM); // inputPictureChromaAddressHi
+       RVCE_CS(enc->chroma->level[0].offset); // inputPictureChromaAddressLo
+       RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
+       RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
+       RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
+       RVCE_CS(0x00010000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
+       RVCE_CS(0x00000000); // encInputPicTileConfig
+       RVCE_CS(enc->pic.picture_type); // encPicType
+       RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag
+       RVCE_CS(0x00000000); // encIdrPicId
+       RVCE_CS(0x00000000); // encMGSKeyPic
+       RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag
+       RVCE_CS(0x00000000); // encTemporalLayerIndex
+       RVCE_CS(0x00000000); // num_ref_idx_active_override_flag
+       RVCE_CS(0x00000000); // num_ref_idx_l0_active_minus1
+       RVCE_CS(0x00000000); // num_ref_idx_l1_active_minus1
+
+       i = enc->pic.frame_num - enc->pic.ref_idx_l0;
+       if (i > 1 && enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) {
+               RVCE_CS(0x00000001); // encRefListModificationOp
+               RVCE_CS(i - 1);      // encRefListModificationNum
+       } else {
+               RVCE_CS(0x00000000); // encRefListModificationOp
+               RVCE_CS(0x00000000); // encRefListModificationNum
+       }
+
+       for (i = 0; i < 3; ++i) {
+               RVCE_CS(0x00000000); // encRefListModificationOp
+               RVCE_CS(0x00000000); // encRefListModificationNum
+       }
+       for (i = 0; i < 4; ++i) {
+               RVCE_CS(0x00000000); // encDecodedPictureMarkingOp
+               RVCE_CS(0x00000000); // encDecodedPictureMarkingNum
+               RVCE_CS(0x00000000); // encDecodedPictureMarkingIdx
+               RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingOp
+               RVCE_CS(0x00000000); // encDecodedRefBasePictureMarkingNum
+       }
+
+       // encReferencePictureL0[0]
+       RVCE_CS(0x00000000); // pictureStructure
+       if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
+          enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
+               struct rvce_cpb_slot *l0 = l0_slot(enc);
+               rvce_frame_offset(enc, l0, &luma_offset, &chroma_offset);
+               RVCE_CS(l0->picture_type); // encPicType
+               RVCE_CS(l0->frame_num); // frameNumber
+               RVCE_CS(l0->pic_order_cnt); // pictureOrderCount
+               RVCE_CS(luma_offset); // lumaOffset
+               RVCE_CS(chroma_offset); // chromaOffset
+       } else {
+               RVCE_CS(0x00000000); // encPicType
+               RVCE_CS(0x00000000); // frameNumber
+               RVCE_CS(0x00000000); // pictureOrderCount
+               RVCE_CS(0xffffffff); // lumaOffset
+               RVCE_CS(0xffffffff); // chromaOffset
+       }
+
+       // encReferencePictureL0[1]
+       RVCE_CS(0x00000000); // pictureStructure
+       RVCE_CS(0x00000000); // encPicType
+       RVCE_CS(0x00000000); // frameNumber
+       RVCE_CS(0x00000000); // pictureOrderCount
+       RVCE_CS(0xffffffff); // lumaOffset
+       RVCE_CS(0xffffffff); // chromaOffset
+
+       // encReferencePictureL1[0]
+       RVCE_CS(0x00000000); // pictureStructure
+       if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
+               struct rvce_cpb_slot *l1 = l1_slot(enc);
+               rvce_frame_offset(enc, l1, &luma_offset, &chroma_offset);
+               RVCE_CS(l1->picture_type); // encPicType
+               RVCE_CS(l1->frame_num); // frameNumber
+               RVCE_CS(l1->pic_order_cnt); // pictureOrderCount
+               RVCE_CS(luma_offset); // lumaOffset
+               RVCE_CS(chroma_offset); // chromaOffset
+       } else {
+               RVCE_CS(0x00000000); // encPicType
+               RVCE_CS(0x00000000); // frameNumber
+               RVCE_CS(0x00000000); // pictureOrderCount
+               RVCE_CS(0xffffffff); // lumaOffset
+               RVCE_CS(0xffffffff); // chromaOffset
+       }
+
+       rvce_frame_offset(enc, current_slot(enc), &luma_offset, &chroma_offset);
+       RVCE_CS(luma_offset); // encReconstructedLumaOffset
+       RVCE_CS(chroma_offset); // encReconstructedChromaOffset
+       RVCE_CS(0x00000000); // encColocBufferOffset
+       RVCE_CS(0x00000000); // encReconstructedRefBasePictureLumaOffset
+       RVCE_CS(0x00000000); // encReconstructedRefBasePictureChromaOffset
+       RVCE_CS(0x00000000); // encReferenceRefBasePictureLumaOffset
+       RVCE_CS(0x00000000); // encReferenceRefBasePictureChromaOffset
+       RVCE_CS(0x00000000); // pictureCount
+       RVCE_CS(enc->pic.frame_num); // frameNumber
+       RVCE_CS(enc->pic.pic_order_cnt); // pictureOrderCount
+       RVCE_CS(0x00000000); // numIPicRemainInRCGOP
+       RVCE_CS(0x00000000); // numPPicRemainInRCGOP
+       RVCE_CS(0x00000000); // numBPicRemainInRCGOP
+       RVCE_CS(0x00000000); // numIRPicRemainInRCGOP
+       RVCE_CS(0x00000000); // enableIntraRefresh
+       RVCE_END();
+}
+
+void radeon_vce_50_init(struct rvce_encoder *enc)
+{
+       radeon_vce_40_2_2_init(enc);
+
+       /* only the two below are different */
+       enc->rate_control = rate_control;
+       enc->encode = encode;
+}