;;
;; Other constraints:
;;
-;; T an operand that can be accessed with 68HC1X direct addressing
-;; mode. For 68HC11 this includes the pseudo soft registers and
-;; any memory operand that is a direct addressing (.page0).
+;; Q an operand which is in memory but whose address is constant
+;; (ie, a (MEM (SYMBOL_REF x))). This constraint is used by
+;; bset/bclr instructions together with linker relaxation. The
+;; operand can be translated to a page0 addressing mode if the
+;; symbol address is in page0 (0..255).
+;;
+;; R an operand which is in memory and whose address is expressed
+;; with 68HC11/68HC12 indexed addressing mode. In general this
+;; is any valid (MEM) except a (MEM (SYMBOL_REF x)).
+;;
+;; U an operand which is in memory and if it uses the 68HC12 indexed
+;; addressing mode, the offset is in the range -16..+15. This is
+;; used by 68HC12 movb/movw instructions since they do not accept
+;; the full 16-bit offset range (as other insn do).
;;
;;
;; Immediate integer operand constraints:
;; some values in bad registers.
;;
;; 32/64-bit Patterns:
-;; The 68HC11 does not support 32/64-bit operations. Most of the
+;; The 68HC11 does not support 32/64-bit operations. Most of the
;; 32/64-bit patterns are defined to split the instruction in
-;; 16-bits patterns. Providing split patterns generates better code
+;; 16-bits patterns. Providing split patterns generates better code
;; than letting GCC implement the 32/64-bit operation itself.
;;
;;
;; them correctly (it would treat the X, Y or D register as dead sometimes).
;;
;; o Some split pattern generate instructions that operate on 'a' or 'b'
-;; register directory (high part and low part of D respectively).
+;; register directly (high part and low part of D respectively).
;; Such split pattern must also be valid when z_replacement_completed == 2
;; because flow/cse is not aware that D is composed of {a, b}.
;;
"#")
(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=D")
- (and:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "general_operand" "Dimu")))]
+ [(set (match_operand:SI 0 "register_operand" "=D,!u")
+ (and:SI (match_operand:SI 1 "register_operand" "%0,0")
+ (match_operand:SI 2 "general_operand" "Dimu,imu")))
+ (clobber (match_scratch:HI 3 "=X,d"))]
""
"#")
-(define_insn "andhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,!u,d,!*A")
- (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
- (match_operand:HI 2 "general_operand" "i,i,!um*A,!ium*A")))]
+(define_expand "andhi3"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (and:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "general_operand" "")))]
""
+ "")
+
+(define_insn "*andhi3_mem"
+ [(set (match_operand:HI 0 "memory_operand" "=Q,R")
+ (and:HI (match_dup 0)
+ (match_operand:HI 1 "immediate_operand" "i,i")))
+ (clobber (match_scratch:HI 2 "=xy,X"))]
+ "TARGET_RELAX && !TARGET_M6812"
"*
{
- if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
- return \"#\";
+ int val = INTVAL (operands[1]) & 0x0FFFF;
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (val == 0x0ffff)
{
- int val = INTVAL (operands[2]) & 0x0FFFF;
- char lowpart_zero = 0;
- char lowpart_unknown = 0;
- char highpart_zero = 0;
- char highpart_unknown = 0;
+ cc_status = cc_prev_status;
+ return \"\";
+ }
- if (val == 0xFFFF)
- {
- cc_status = cc_prev_status;
- return \"\";
- }
+ CC_STATUS_INIT;
- /* First, try to clear the low and high part.
- If that's possible, the second 'and' will give
- the good status flags and we can avoid a tsthi. */
- if ((val & 0x0FF) == 0)
- {
- if (D_REG_P (operands[0]))
- output_asm_insn (\"clrb\", operands);
- else
- output_asm_insn (\"clr\\t%b0\", operands);
- lowpart_zero = 1;
- }
- if ((val & 0x0FF00) == 0)
- {
- if (D_REG_P (operands[0]))
- output_asm_insn (\"clra\", operands);
- else
- output_asm_insn (\"clr\\t%h0\", operands);
- highpart_zero = 1;
- }
+ /* The bclr instruction uses an inverted mask. */
+ operands[1] = gen_rtx (CONST_INT, VOIDmode, (~val) & 0x0FFFF);
- if ((val & 0x0FF) == 0x0FF)
- {
- lowpart_unknown = 1;
- }
- else if ((val & 0x0FF) != 0 && !H_REG_P (operands[0]))
- {
- rtx ops[2];
+ /* When destination is a global variable, generate a .relax instruction
+ and load the address in the clobber register. That load can be
+ eliminated by the linker if the address is in page0. */
+ if (which_alternative == 0)
+ {
+ rtx ops[3];
- ops[0] = operands[0];
- ops[1] = gen_rtx (CONST_INT, VOIDmode, (~val) & 0x0FF);
- output_asm_insn (\"bclr\\t%b0, %1\", ops);
- }
- else if ((val & 0x0FF) != 0)
- {
- output_asm_insn (\"andb\\t%b2\", operands);
- }
+ ops[0] = operands[2];
+ ops[1] = XEXP (operands[0], 0);
+ ops[2] = gen_label_rtx ();
+ output_asm_insn (\".relax\\t%l2\", ops);
+ m68hc11_gen_movhi (insn, ops);
+ if ((val & 0x0FF) != 0x0FF)
+ output_asm_insn (\"bclr\\t1,%2, %b1\", operands);
- if ((val & 0x0FF00) == 0x0FF00)
- {
- highpart_unknown = 1;
- }
- else if (((val & 0x0FF00) != 0) && !H_REG_P (operands[0]))
- {
- rtx ops[2];
+ if ((val & 0x0FF00) != 0x0FF00)
+ output_asm_insn (\"bclr\\t0,%2, %h1\", operands);
- ops[0] = operands[0];
- ops[1] = gen_rtx (CONST_INT, VOIDmode, ((~val) & 0x0FF00) >> 8);
- output_asm_insn (\"bclr\\t%h0, %1\", ops);
- }
- else if ((val & 0x0FF00) != 0)
- {
- output_asm_insn (\"anda\\t%h2\", operands);
- }
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ CODE_LABEL_NUMBER (ops[2]));
+ return \"\";
+ }
+
+ if ((val & 0x0FF) != 0x0FF)
+ output_asm_insn (\"bclr\\t%b0, %b1\", operands);
+
+ if ((val & 0x0FF00) != 0x0FF00)
+ output_asm_insn (\"bclr\\t%h0, %h1\", operands);
- if (highpart_unknown || lowpart_unknown)
- CC_STATUS_INIT;
- else if (highpart_zero == 0 && lowpart_zero == 0)
- CC_STATUS_INIT;
+ return \"\";
+}")
+
+(define_insn "*andhi3_const"
+ [(set (match_operand:HI 0 "reg_or_some_mem_operand" "=R,d,?*A")
+ (and:HI (match_operand:HI 1 "reg_or_some_mem_operand" "%0,0,0")
+ (match_operand:HI 2 "const_int_operand" "")))]
+ ""
+ "*
+{
+ int val = INTVAL (operands[2]) & 0x0FFFF;
+ int lowpart_zero = 0;
+ int highpart_zero = 0;
+ int lowpart_unknown = 0;
+ int highpart_unknown = 0;
+
+ if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
+ return \"#\";
+ if (val == 0x0ffff)
+ {
+ cc_status = cc_prev_status;
return \"\";
}
+ /* First, try to clear the low and high part.
+ If that's possible, the second 'and' will give
+ the good status flags and we can avoid a tsthi. */
+ if ((val & 0x0FF) == 0)
+ {
+ if (D_REG_P (operands[0]))
+ output_asm_insn (\"clrb\", operands);
+ else
+ output_asm_insn (\"clr\\t%b0\", operands);
+ lowpart_zero = 1;
+ }
+ if ((val & 0x0FF00) == 0)
+ {
+ if (D_REG_P (operands[0]))
+ output_asm_insn (\"clra\", operands);
+ else
+ output_asm_insn (\"clr\\t%h0\", operands);
+ highpart_zero = 1;
+ }
+
+ if ((val & 0x0FF) == 0x0FF)
+ {
+ lowpart_unknown = 1;
+ }
+ else if ((val & 0x0FF) != 0 && !H_REG_P (operands[0]))
+ {
+ rtx ops[2];
+
+ ops[0] = operands[0];
+ ops[1] = gen_rtx (CONST_INT, VOIDmode, (~val) & 0x0FF);
+ output_asm_insn (\"bclr\\t%b0, %1\", ops);
+ }
+ else if ((val & 0x0FF) != 0)
+ {
+ output_asm_insn (\"andb\\t%b2\", operands);
+ }
+
+ if ((val & 0x0FF00) == 0x0FF00)
+ {
+ highpart_unknown = 1;
+ }
+ else if (((val & 0x0FF00) != 0) && !H_REG_P (operands[0]))
+ {
+ rtx ops[2];
+
+ ops[0] = operands[0];
+ ops[1] = gen_rtx (CONST_INT, VOIDmode, ((~val) & 0x0FF00) >> 8);
+ output_asm_insn (\"bclr\\t%h0, %1\", ops);
+ }
+ else if ((val & 0x0FF00) != 0)
+ {
+ output_asm_insn (\"anda\\t%h2\", operands);
+ }
+
+ if (highpart_unknown || lowpart_unknown)
+ CC_STATUS_INIT;
+ else if (highpart_zero == 0 && lowpart_zero == 0)
+ CC_STATUS_INIT;
+
+ return \"\";
+}")
+
+(define_insn "*andhi3_gen"
+ [(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
+ (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
+ (match_operand:HI 2 "general_operand" "mi,!u*A,!um*A")))]
+ ""
+ "*
+{
+ if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
+ return \"#\";
+
CC_STATUS_INIT;
return \"andb\\t%b2\\n\\tanda\\t%h2\";
}")
-(define_insn "andqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,!u,d,d,?*A,?*A,!*q")
- (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "i,i,!um,?*A,!ium,?*A*d,!ium*A")))]
+(define_expand "andqi3"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (and:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn "*andqi3_mem"
+ [(set (match_operand:QI 0 "memory_operand" "=Q,R")
+ (and:QI (match_dup 0)
+ (match_operand:QI 1 "const_int_operand" "i,i")))
+ (clobber (match_scratch:HI 2 "=xy,X"))]
+ "TARGET_RELAX && !TARGET_M6812"
+ "*
+{
+ int val = INTVAL (operands[1]) & 0x0FF;
+
+ if (val == 0x0ff)
+ {
+ cc_status = cc_prev_status;
+ return \"\";
+ }
+
+ /* The bclr instruction uses an inverted mask. */
+ operands[1] = gen_rtx (CONST_INT, VOIDmode, (~val) & 0x0FF);
+
+ /* When destination is a global variable, generate a .relax instruction
+ and load the address in the clobber register. That load can be
+ eliminated by the linker if the address is in page0. */
+ if (which_alternative == 0)
+ {
+ rtx ops[3];
+
+ ops[0] = operands[2];
+ ops[1] = XEXP (operands[0], 0);
+ ops[2] = gen_label_rtx ();
+ output_asm_insn (\".relax\\t%l2\", ops);
+ m68hc11_gen_movhi (insn, ops);
+ output_asm_insn (\"bclr\\t0,%2, %1\", operands);
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ CODE_LABEL_NUMBER (ops[2]));
+ return \"\";
+ }
+ return \"bclr\\t%b0, %1\";
+}")
+
+(define_insn "*andqi3_const"
+ [(set (match_operand:QI 0 "reg_or_some_mem_operand" "=R,d,?*A*q")
+ (and:QI (match_operand:QI 1 "reg_or_some_mem_operand" "%0,0,0")
+ (match_operand:QI 2 "const_int_operand" "")))]
""
"*
{
+ int val = INTVAL (operands[2]) & 0x0FF;
+
if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
return \"#\";
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (val == 0x0ff)
{
- int val = INTVAL (operands[2]) & 0x0FF;
+ cc_status = cc_prev_status;
+ return \"\";
+ }
+ if (!H_REG_P (operands[0]))
+ {
+ rtx ops[2];
- if (val == 0xFF)
- {
- cc_status = cc_prev_status;
- return \"\";
- }
- if (val == 0)
- {
- if (D_REG_P (operands[0]) || DB_REG_P (operands[0]))
- return \"clrb\";
- else if (DA_REG_P (operands[0]))
- return \"clra\";
- else
- return \"clr\\t%b0\";
- }
- if (!H_REG_P (operands[0]))
- {
- rtx ops[2];
- ops[0] = operands[0];
- ops[1] = gen_rtx (CONST_INT, VOIDmode, (~val) & 0x0FF);
- output_asm_insn (\"bclr\\t%b0, %b1\", ops);
- return \"\";
- }
+ ops[0] = operands[0];
+ ops[1] = gen_rtx (CONST_INT, VOIDmode, (~val) & 0x0FF);
+ output_asm_insn (\"bclr\\t%b0, %b1\", ops);
+ return \"\";
}
if (D_REG_P (operands[0]) || DB_REG_P (operands[0]))
return \"andb\\t%b2\";
fatal_insn (\"Invalid operand in the instruction\", insn);
}")
+(define_insn "*andqi3_gen"
+ [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
+ (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "mi,!u,?*A,!um,?*A*d,!um*A")))]
+ ""
+ "*
+{
+ if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
+ return \"#\";
+
+ if (D_REG_P (operands[0]) || DB_REG_P (operands[0]))
+ return \"andb\\t%b2\";
+ else if (DA_REG_P (operands[0]))
+ return \"anda\\t%b2\";
+ else
+ fatal_insn (\"Invalid operand in the instruction\", insn);
+}")
+
;;--------------------------------------------------------------------
;;- Bit set or instructions.
;;--------------------------------------------------------------------
"#")
(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=D")
- (ior:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "general_operand" "Dimu")))]
+ [(set (match_operand:SI 0 "register_operand" "=D,!u")
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
+ (match_operand:SI 2 "general_operand" "Dimu,imu")))
+ (clobber (match_scratch:HI 3 "=X,d"))]
""
"#")
-(define_insn "iorhi3"
- [(set (match_operand:HI 0 "register_operand" "=d,!u,d,!*A")
- (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
- (match_operand:HI 2 "general_operand" "i,i,!um*A,!ium*A")))]
+(define_expand "iorhi3"
+ [(set (match_operand:HI 0 "register_operand" "")
+ (ior:HI (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "general_operand" "")))]
""
+ "")
+
+(define_insn "*iorhi3_mem"
+ [(set (match_operand:HI 0 "memory_operand" "=Q,R")
+ (ior:HI (match_dup 0)
+ (match_operand:HI 1 "const_int_operand" "")))
+ (clobber (match_scratch:HI 2 "=xy,X"))]
+ "TARGET_RELAX && !TARGET_M6812"
"*
{
- if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
- return \"#\";
+ int val = INTVAL (operands[1]) & 0x0FFFF;
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (val == 0)
{
- int val = INTVAL (operands[2]) & 0x0FFFF;
+ cc_status = cc_prev_status;
+ return \"\";
+ }
+ CC_STATUS_INIT;
+ if (which_alternative == 0)
+ {
+ rtx ops[3];
- if (val == 0)
- {
- cc_status = cc_prev_status;
- return \"\";
- }
+ ops[0] = operands[2];
+ ops[1] = XEXP (operands[0], 0);
+ ops[2] = gen_label_rtx ();
+ output_asm_insn (\".relax\\t%l2\", ops);
+ m68hc11_gen_movhi (insn, ops);
if ((val & 0x0FF) != 0)
- {
- if (!H_REG_P (operands[0]))
- output_asm_insn (\"bset\\t%b0, %b2\", operands);
- else
- output_asm_insn (\"orab\\t%b2\", operands);
- }
+ output_asm_insn (\"bset\\t1,%2, %b1\", operands);
if ((val & 0x0FF00) != 0)
- {
- if (!H_REG_P (operands[0]))
- output_asm_insn (\"bset\\t%h0, %h2\", operands);
- else
- output_asm_insn (\"oraa\\t%h2\", operands);
- }
+ output_asm_insn (\"bset\\t0,%2, %h1\", operands);
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ CODE_LABEL_NUMBER (ops[2]));
+ return \"\";
+ }
- CC_STATUS_INIT;
+ if ((val & 0x0FF) != 0)
+ output_asm_insn (\"bset\\t%b0, %b1\", operands);
+
+ if ((val & 0x0FF00) != 0)
+ output_asm_insn (\"bset\\t%h0, %h1\", operands);
+
+ return \"\";
+}")
+
+(define_insn "*iorhi3_const"
+ [(set (match_operand:HI 0 "reg_or_some_mem_operand" "=R,d,?*A")
+ (ior:HI (match_operand:HI 1 "reg_or_some_mem_operand" "%0,0,0")
+ (match_operand:HI 2 "const_int_operand" "")))]
+ ""
+ "*
+{
+ int val = INTVAL (operands[2]) & 0x0FFFF;
+
+ if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
+ return \"#\";
+
+ if (val == 0)
+ {
+ cc_status = cc_prev_status;
return \"\";
}
+ if ((val & 0x0FF) != 0)
+ {
+ if (!H_REG_P (operands[0]))
+ output_asm_insn (\"bset\\t%b0, %b2\", operands);
+ else
+ output_asm_insn (\"orab\\t%b2\", operands);
+ }
+
+ if ((val & 0x0FF00) != 0)
+ {
+ if (!H_REG_P (operands[0]))
+ output_asm_insn (\"bset\\t%h0, %h2\", operands);
+ else
+ output_asm_insn (\"oraa\\t%h2\", operands);
+ }
+
CC_STATUS_INIT;
- return \"orab\\t%b2\\n\\toraa\\t%h2\";
+ return \"\";
}")
-(define_insn "iorqi3"
- [(set (match_operand:QI 0 "register_operand" "=d,!u,d,d,?*A,?*A,!*q")
- (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "i,i,!um,!*A,!ium,?*A*d,!ium*A")))]
+(define_insn "*iorhi3_gen"
+ [(set (match_operand:HI 0 "register_operand" "=d,d,!*A")
+ (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0")
+ (match_operand:HI 2 "general_operand" "mi,!u*A,!um*A")))]
""
"*
{
if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
return \"#\";
- if (GET_CODE (operands[2]) == CONST_INT)
+ CC_STATUS_INIT;
+ return \"orab\\t%b2\\n\\toraa\\t%h2\";
+}")
+
+(define_expand "iorqi3"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (ior:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "general_operand" "")))]
+ ""
+ "")
+
+(define_insn "*iorqi3_mem"
+ [(set (match_operand:QI 0 "memory_operand" "=Q,R")
+ (ior:QI (match_dup 0)
+ (match_operand:QI 1 "const_int_operand" "")))
+ (clobber (match_scratch:HI 2 "=xy,X"))]
+ "TARGET_RELAX && !TARGET_M6812"
+ "*
+{
+ int val = INTVAL (operands[1]) & 0x0FF;
+
+ if (val == 0)
{
- int val = INTVAL (operands[2]) & 0x0FF;
+ cc_status = cc_prev_status;
+ return \"\";
+ }
+ if (which_alternative == 0)
+ {
+ rtx ops[3];
- if (val == 0)
- {
- cc_status = cc_prev_status;
- return \"\";
- }
- if (!H_REG_P (operands[0]))
- {
- return \"bset\\t%b0, %2\";
- }
+ ops[0] = operands[2];
+ ops[1] = XEXP (operands[0], 0);
+ ops[2] = gen_label_rtx ();
+ output_asm_insn (\".relax\\t%l2\", ops);
+ m68hc11_gen_movhi (insn, ops);
+ output_asm_insn (\"bset\\t0,%2, %1\", operands);
+ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ CODE_LABEL_NUMBER (ops[2]));
+ return \"\";
+ }
+ return \"bset\\t%b0, %1\";
+}")
+
+(define_insn "*iorqi3_const"
+ [(set (match_operand:QI 0 "reg_or_some_mem_operand" "=R,d,?*A*q")
+ (ior:QI (match_operand:QI 1 "reg_or_some_mem_operand" "%0,0,0")
+ (match_operand:QI 2 "const_int_operand" "")))]
+ ""
+ "*
+{
+ int val = INTVAL (operands[2]) & 0x0FF;
+
+ if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
+ return \"#\";
+
+ if (val == 0)
+ {
+ cc_status = cc_prev_status;
+ return \"\";
+ }
+ if (!H_REG_P (operands[0]))
+ {
+ return \"bset\\t%b0, %2\";
}
+
+ if (D_REG_P (operands[0]) || DB_REG_P (operands[0]))
+ return \"orab\\t%b2\";
+ else if (DA_REG_P (operands[0]))
+ return \"oraa\\t%b2\";
+ else
+ fatal_insn (\"Invalid operand in the instruction\", insn);
+}")
+
+(define_insn "*iorqi3_gen"
+ [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
+ (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "mi,!u,!*A,!um,?*A*d,!um*A")))]
+ ""
+ "*
+{
+ if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
+ return \"#\";
+
if (D_REG_P (operands[0]) || DB_REG_P (operands[0]))
return \"orab\\t%b2\";
else if (DA_REG_P (operands[0]))
fatal_insn (\"Invalid operand in the instruction\", insn);
}")
+
;;--------------------------------------------------------------------
;;- xor instructions.
;;--------------------------------------------------------------------
"#")
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=D")
- (xor:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "general_operand" "Dimu")))]
+ [(set (match_operand:SI 0 "register_operand" "=D,!u")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
+ (match_operand:SI 2 "general_operand" "Dimu,imu")))
+ (clobber (match_scratch:HI 3 "=X,d"))]
""
"#")
(define_insn "xorqi3"
[(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
(xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "i,!um,!*A,!ium,?*A*d,!ium*A")))]
+ (match_operand:QI 2 "general_operand" "im,!u,!*A,!ium,?*A*d,!ium*A")))]
""
"*
{
projects / platform / upstream / linaro-gcc.git / commitdiff