drm/amdgpu: use AMDGPU_NUM_VMID when possible

Replace hardcoded vmid number with AMDGPU_NUM_VMID macro.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 157ae30..ba10867 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4844,7 +4844,7 @@ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index f2490f9..a368724 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1896,7 +1896,7 @@ static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 9a90553..3763921 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3749,7 +3749,7 @@ static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6051943..fc9bb94 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2520,7 +2520,7 @@ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 5317efc..11fedcf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -432,7 +432,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                return 0;
        }
 
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 
                ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
                                &queried_pasid);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 95a9117..998d6c8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -530,7 +530,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
         * the VMs are determined by the application and setup and assigned
         * on the fly in the vm part of radeon_gart.c
         */
-       for (i = 1; i < 16; i++) {
+       for (i = 1; i < AMDGPU_NUM_VMID; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
                               table_addr >> 12);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index d9cb887..d06e3f5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -677,7 +677,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        /* set vm size, must be a multiple of 4 */
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
-       for (i = 1; i < 16; i++) {
+       for (i = 1; i < AMDGPU_NUM_VMID; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
                               table_addr >> 12);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 65d7bc1..e8d0710 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -903,7 +903,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        /* set vm size, must be a multiple of 4 */
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
-       for (i = 1; i < 16; i++) {
+       for (i = 1; i < AMDGPU_NUM_VMID; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
                               table_addr >> 12);

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 0309d84..d7b39c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -344,7 +344,7 @@ static void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
        u32 i;
 
        /* Disable all tables */
-       for (i = 0; i < 16; i++)
+       for (i = 0; i < AMDGPU_NUM_VMID; i++)
                WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 57d5f8f..092ff2c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -421,7 +421,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
        u32 i;
 
        /* Disable all tables */
-       for (i = 0; i < 16; i++)
+       for (i = 0; i < AMDGPU_NUM_VMID; i++)
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index fa77eae..b72c8e4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -376,7 +376,7 @@ static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
        u32 i;
 
        /* Disable all tables */
-       for (i = 0; i < 16; i++)
+       for (i = 0; i < AMDGPU_NUM_VMID; i++)
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 66748bb..4a31737 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -405,7 +405,7 @@ static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 
        for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
                /* Disable all tables */
-               for (i = 0; i < 16; i++)
+               for (i = 0; i < AMDGPU_NUM_VMID; i++)
                        WREG32_SOC15_OFFSET(MMHUB, 0,
                                            mmVML2VC0_VM_CONTEXT0_CNTL,
                                            j * MMHUB_INSTANCE_REGISTER_OFFSET +