drm/nouveau/nvdec/gm107: rename from gp102 implementation
authorBen Skeggs <bskeggs@redhat.com>
Tue, 14 Jan 2020 20:34:21 +0000 (06:34 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 15 Jan 2020 00:50:27 +0000 (10:50 +1000)
NVDEC is available from GM107, and we currently only have a stub
implementation anyway, let's make it explicit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c [moved from drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gp102.c with 85% similarity]

index ae3c294..1b3183e 100644 (file)
@@ -11,5 +11,5 @@ struct nvkm_nvdec {
        struct nvkm_falcon falcon;
 };
 
-int gp102_nvdec_new(struct nvkm_device *, int, struct nvkm_nvdec **);
+int gm107_nvdec_new(struct nvkm_device *, int, struct nvkm_nvdec **);
 #endif
index d63478b..9dbbdbb 100644 (file)
@@ -2227,7 +2227,7 @@ nv132_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp102_gr_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2264,7 +2264,7 @@ nv134_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp104_gr_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2301,7 +2301,7 @@ nv136_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp104_gr_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2338,7 +2338,7 @@ nv137_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp107_gr_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2375,7 +2375,7 @@ nv138_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp108_gr_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = gp108_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2443,7 +2443,7 @@ nv140_chipset = {
        .dma = gv100_dma_new,
        .fifo = gv100_fifo_new,
        .gr = gv100_gr_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = gp108_sec2_new,
 };
 
@@ -2478,7 +2478,7 @@ nv162_chipset = {
        .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu102_fifo_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = tu102_sec2_new,
 };
 
@@ -2513,7 +2513,7 @@ nv164_chipset = {
        .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu102_fifo_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = tu102_sec2_new,
 };
 
@@ -2548,7 +2548,7 @@ nv166_chipset = {
        .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu102_fifo_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = tu102_sec2_new,
 };
 
@@ -2583,7 +2583,7 @@ nv167_chipset = {
        .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu102_fifo_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = tu102_sec2_new,
 };
 
@@ -2618,7 +2618,7 @@ nv168_chipset = {
        .disp = tu102_disp_new,
        .dma = gv100_dma_new,
        .fifo = tu102_fifo_new,
-       .nvdec[0] = gp102_nvdec_new,
+       .nvdec[0] = gm107_nvdec_new,
        .sec2 = tu102_sec2_new,
 };
 
index cdf6318..9a0fd98 100644 (file)
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: MIT
 nvkm-y += nvkm/engine/nvdec/base.o
-nvkm-y += nvkm/engine/nvdec/gp102.o
+nvkm-y += nvkm/engine/nvdec/gm107.o
@@ -22,7 +22,7 @@
 #include "priv.h"
 
 static const struct nvkm_falcon_func
-gp102_nvdec_flcn = {
+gm107_nvdec_flcn = {
        .load_imem = nvkm_falcon_v1_load_imem,
        .load_dmem = nvkm_falcon_v1_load_dmem,
        .read_dmem = nvkm_falcon_v1_read_dmem,
@@ -36,26 +36,26 @@ gp102_nvdec_flcn = {
 };
 
 static const struct nvkm_nvdec_func
-gp102_nvdec = {
-       .flcn = &gp102_nvdec_flcn,
+gm107_nvdec = {
+       .flcn = &gm107_nvdec_flcn,
 };
 
 static int
-gp102_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,
+gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,
                 const struct nvkm_nvdec_fwif *fwif)
 {
        return 0;
 }
 
 static const struct nvkm_nvdec_fwif
-gp102_nvdec_fwif[] = {
-       { -1, gp102_nvdec_nofw, &gp102_nvdec },
+gm107_nvdec_fwif[] = {
+       { -1, gm107_nvdec_nofw, &gm107_nvdec },
        {}
 };
 
 int
-gp102_nvdec_new(struct nvkm_device *device, int index,
+gm107_nvdec_new(struct nvkm_device *device, int index,
                struct nvkm_nvdec **pnvdec)
 {
-       return nvkm_nvdec_new_(gp102_nvdec_fwif, device, index, pnvdec);
+       return nvkm_nvdec_new_(gm107_nvdec_fwif, device, index, pnvdec);
 }