If srcAccessMask in pipeline barrier is VK_ACCESS_TRANSFER_WRITE_BIT the
srcStageMask must be VK_PIPELINE_STAGE_TRANSFER_BIT
Components: Vulkan
VK-GL-CTS issue: 3963
Affected tests:
dEQP-VK.api.buffer_marker.compute.default_mem.*
Change-Id: I0a5957d714c4c5cb9f2855421cd78683b7b7b819
VK_ACCESS_HOST_READ_BIT,
};
- vk.cmdPipelineBarrier(*cmdBuffer, params.stage, VK_PIPELINE_STAGE_HOST_BIT, 0, 1, &memoryDep, 0, DE_NULL, 0, DE_NULL);
+ vk.cmdPipelineBarrier(*cmdBuffer, VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_HOST_BIT, 0, 1, &memoryDep, 0, DE_NULL, 0, DE_NULL);
VK_CHECK(vk.endCommandBuffer(*cmdBuffer));