r600g: remove the unneeded bo from COLOR[0-9]_INFO

The COLOR[0-7]_INFO registers doesn't neeed a bo.

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index ac2e898..da4f270 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -787,7 +787,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
                                (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
        r600_pipe_state_add_reg(rstate,
                                R_0280A0_CB_COLOR0_INFO + cb * 4,
-                               color_info, 0xFFFFFFFF, bo[0]);
+                               color_info, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate,
                                R_028060_CB_COLOR0_SIZE + cb * 4,
                                S_028060_PITCH_TILE_MAX(pitch) |

diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 662455b..6be05bd 100644 (file)
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -199,7 +199,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -210,7 +210,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -221,7 +221,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -232,7 +232,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -243,7 +243,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -254,7 +254,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -263,7 +263,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
@@ -274,7 +274,7 @@ static const struct r600_reg r600_context_reg_list[] = {
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
        {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+       {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, 0, 0, 0xFFFFFFFF},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
        {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},