void prcm_init(void);
void per_clocks_enable(void);
void ehci_clocks_enable(void);
-
void memif_init(void);
void sdrc_init(void);
-void do_sdrc_init(u32, u32);
-
void get_board_mem_timings(struct board_sdrc_timings *timings);
int identify_nand_chip(int *mfr, int *id);
void emif4_init(void);
u32 wait_on_value(u32, u32, void *, u32);
void cancel_out(u32 *num, u32 *den, u32 den_limit);
void sdelay(unsigned long);
-void make_cs1_contiguous(void);
int omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_set_aux_cr_secure(u32 acr);
u32 warm_reset(void);
-
void save_omap_boot_params(void);
#endif
}
/*
+ * get_sdr_cs_size -
+ * - Get size of chip select 0/1
+ */
+static u32 get_sdr_cs_size(u32 cs)
+{
+ u32 size;
+
+ /* get ram size field */
+ size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size <<= 21; /* multiply by 2 MiB to find size in MB */
+ return size;
+}
+
+/*
* make_cs1_contiguous -
* - When we have CS1 populated we want to have it mapped after cs0 to allow
* command line mem=xyz use all memory with out discontinuous support
* compiled in. We could do it in the ATAG, but there really is two banks...
*/
-void make_cs1_contiguous(void)
+static void make_cs1_contiguous(void)
{
u32 size, a_add_low, a_add_high;
}
-
-/*
- * get_sdr_cs_size -
- * - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size;
-
- /* get ram size field */
- size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
- size &= 0x3FF; /* remove unwanted bits */
- size <<= 21; /* multiply by 2 MiB to find size in MB */
- return size;
-}
-
/*
* get_sdr_cs_offset -
* - Get offset of cs from cs0 start
* true and a possible 2nd time depending on memory configuration from
* stack+global context.
*/
-void do_sdrc_init(u32 cs, u32 early)
+static void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
struct board_sdrc_timings timings;