Pull Amlogic clk driver updates from Jerome Brunet:
- Use determine_rate() for the pll ops instead of round_rate()
- Restrict gp0/1 and audio plls range on g12a/sm1
- Improve axg-audio controller error on deferral
- Add NNA clocks on g12a
* tag 'clk-meson-v5.14-1' of https://github.com/BayLibre/clk-meson:
clk: meson: g12a: Add missing NNA source clocks for g12b
clk: meson: axg-audio: improve deferral handling
clk: meson: g12a: fix gp0 and hifi ranges
clk: meson: pll: switch to determine_rate for the PLL ops