intel/dev: Add (disabled) device info for MTL
authorJordan Justen <jordan.l.justen@intel.com>
Tue, 26 Jan 2021 07:01:52 +0000 (23:01 -0800)
committerMarge Bot <emma+marge@anholt.net>
Thu, 1 Dec 2022 16:22:47 +0000 (16:22 +0000)
Reworks:
 * Jordan: INTEL_PLATFORM_MTL_M/INTEL_PLATFORM_MTL_P
 * Lionel: .has_coarse_pixel_primitive_and_cb
 * Jordan: .has_mesh_shading & .has_ray_tracing
 * Paulo: .has_64bit_float
 * José: .has_integer_dword_mul (BSpec: 47431)
 * Jordan: Comment pci device ids for now similar to DG2:
   * 70a4e646852 ("intel: Add *disabled* device ids for DG2")
   * ad565f6b70d ("intel/dev: Enable first set of DG2 PCI IDs")

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19658>

include/pci_ids/iris_pci_ids.h
src/intel/dev/intel_device_info.c

index 8fdae14..fd8c32a 100644 (file)
@@ -244,3 +244,9 @@ CHIPSET(0x56b2, dg2_g12, "DG2", "Intel(R) Graphics")
 CHIPSET(0x56b3, dg2_g12, "DG2", "Intel(R) Graphics")
 CHIPSET(0x56c0, dg2_g10, "ATS-M", "Intel(R) Data Center GPU Flex Series 170 Graphics")
 CHIPSET(0x56c1, dg2_g11, "ATS-M", "Intel(R) Data Center GPU Flex Series 140 Graphics")
+
+/* CHIPSET(0x7d40, mtl_m, "MTL", "Intel(R) Graphics") */
+/* CHIPSET(0x7d45, mtl_p, "MTL", "Intel(R) Graphics") */
+/* CHIPSET(0x7d55, mtl_p, "MTL", "Intel(R) Graphics") */
+/* CHIPSET(0x7d60, mtl_m, "MTL", "Intel(R) Graphics") */
+/* CHIPSET(0x7dd5, mtl_p, "MTL", "Intel(R) Graphics") */
index 40e0f06..5d32853 100644 (file)
@@ -73,6 +73,7 @@ static const struct {
    { "sg1", 0x4907 },
    { "rpl", 0xa780 },
    { "dg2", 0x5690 },
+   { "mtl", 0x7d60 },
 };
 
 /**
@@ -1083,6 +1084,28 @@ static const struct intel_device_info intel_device_info_dg2_g12 = {
    .platform = INTEL_PLATFORM_DG2_G12,
 };
 
+#define MTL_FEATURES                                            \
+   /* (Sub)slice info comes from the kernel topology info */    \
+   XEHP_FEATURES(0, 1, 0),                                      \
+   .num_subslices = dual_subslices(1),                          \
+   .has_local_mem = false,                                      \
+   .apply_hwconfig = true,                                      \
+   .has_64bit_float = true,                                     \
+   .has_integer_dword_mul = false,                              \
+   .has_coarse_pixel_primitive_and_cb = true,                   \
+   .has_mesh_shading = true,                                    \
+   .has_ray_tracing = true
+
+UNUSED static const struct intel_device_info intel_device_info_mtl_m = {
+   MTL_FEATURES,
+   .platform = INTEL_PLATFORM_MTL_M,
+};
+
+UNUSED static const struct intel_device_info intel_device_info_mtl_p = {
+   MTL_FEATURES,
+   .platform = INTEL_PLATFORM_MTL_P,
+};
+
 static void
 reset_masks(struct intel_device_info *devinfo)
 {