clk: sunxi: Implement EMAC, GMAC clocks, resets

- Implement EMAC, GMAC clocks via ccu_clk_gate for
  all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
  supported Allwinner SoCs.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index fa6e3ee..4ec3c2a 100644 (file)
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a31_gates[] = {
        [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
        [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
        [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
+       [CLK_AHB1_EMAC]         = GATE(0x060, BIT(17)),
        [CLK_AHB1_SPI0]         = GATE(0x060, BIT(20)),
        [CLK_AHB1_SPI1]         = GATE(0x060, BIT(21)),
        [CLK_AHB1_SPI2]         = GATE(0x060, BIT(22)),
@@ -57,6 +58,7 @@ static struct ccu_reset a31_resets[] = {
        [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
        [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
        [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
+       [RST_AHB1_EMAC]         = RESET(0x2c0, BIT(17)),
        [RST_AHB1_SPI0]         = RESET(0x2c0, BIT(20)),
        [RST_AHB1_SPI1]         = RESET(0x2c0, BIT(21)),
        [RST_AHB1_SPI2]         = RESET(0x2c0, BIT(22)),

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 322d6cd..f94e8aa 100644 (file)
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,7 @@ static const struct ccu_clk_gate a64_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(23)),
@@ -49,6 +50,7 @@ static const struct ccu_reset a64_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),

diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 36f7e14..2be87a3 100644 (file)
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -16,6 +16,7 @@ static struct ccu_clk_gate a83t_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
@@ -47,6 +48,7 @@ static struct ccu_reset a83t_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),

diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 5f99ef7..f5ae1e9 100644 (file)
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -16,6 +16,7 @@ static struct ccu_clk_gate h3_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_SPI1]          = GATE(0x060, BIT(21)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(23)),
@@ -55,6 +56,7 @@ static struct ccu_reset h3_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),

diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 71f0c78..0bb00f4 100644 (file)
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -26,6 +26,8 @@ static struct ccu_clk_gate h6_gates[] = {
 
        [CLK_BUS_SPI0]          = GATE(0x96c, BIT(0)),
        [CLK_BUS_SPI1]          = GATE(0x96c, BIT(1)),
+
+       [CLK_BUS_EMAC]          = GATE(0x97c, BIT(0)),
 };
 
 static struct ccu_reset h6_resets[] = {
@@ -39,6 +41,8 @@ static struct ccu_reset h6_resets[] = {
 
        [RST_BUS_SPI0]          = RESET(0x96c, BIT(16)),
        [RST_BUS_SPI1]          = RESET(0x96c, BIT(17)),
+
+       [RST_BUS_EMAC]          = RESET(0x97c, BIT(16)),
 };
 
 static const struct ccu_desc h6_ccu_desc = {

diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 9290728..30beac9 100644 (file)
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -29,6 +29,8 @@ static struct ccu_clk_gate r40_gates[] = {
        [CLK_BUS_OHCI1]         = GATE(0x060, BIT(30)),
        [CLK_BUS_OHCI2]         = GATE(0x060, BIT(31)),
 
+       [CLK_BUS_GMAC]          = GATE(0x064, BIT(17)),
+
        [CLK_BUS_UART0]         = GATE(0x06c, BIT(16)),
        [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
@@ -60,6 +62,7 @@ static struct ccu_reset r40_resets[] = {
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
        [RST_BUS_MMC3]          = RESET(0x2c0, BIT(11)),
+       [RST_BUS_GMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_SPI1]          = RESET(0x2c0, BIT(21)),
        [RST_BUS_SPI2]          = RESET(0x2c0, BIT(22)),