ARM: dts: imx6: Add unit address and reg for the anatop nodes
authorFabio Estevam <fabio.estevam@nxp.com>
Wed, 29 Nov 2017 18:54:36 +0000 (16:54 -0200)
committerShawn Guo <shawnguo@kernel.org>
Tue, 26 Dec 2017 08:15:44 +0000 (16:15 +0800)
Add unit address and reg for the anatop nodes in order to fix the
following build warnings with W=1:

arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-1p1 missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-3p0 missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-2p5 missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu missing or empty reg/ranges property
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (simple_bus_reg): Node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc missing or empty reg/ranges property

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6sl.dtsi
arch/arm/boot/dts/imx6sx.dtsi
arch/arm/boot/dts/imx6ul.dtsi

index 63975a4..59ff866 100644 (file)
                                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 54 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
 
-                               regulator-1p1 {
+                               regulator-1p1@20c8110 {
+                                       reg = <0x20c8110>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd1p1";
                                        regulator-min-microvolt = <1000000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               regulator-3p0 {
+                               regulator-3p0@20c8120 {
+                                       reg = <0x20c8120>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2800000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               regulator-2p5 {
+                               regulator-2p5@20c8130 {
+                                       reg = <0x20c8130>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd2p5";
                                        regulator-min-microvolt = <2250000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               reg_arm: regulator-vddcore {
+                               reg_arm: regulator-vddcore@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddarm";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_pu: regulator-vddpu {
+                               reg_pu: regulator-vddpu@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddpu";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_soc: regulator-vddsoc {
+                               reg_soc: regulator-vddsoc@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;
index 3365182..ae8df3c 100644 (file)
                                interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 54 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 127 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
 
-                               regulator-1p1 {
+                               regulator-1p1@20c8110 {
+                                       reg = <0x20c8110>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd1p1";
                                        regulator-min-microvolt = <800000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               regulator-3p0 {
+                               regulator-3p0@20c8120 {
+                                       reg = <0x20c8120>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2800000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               regulator-2p5 {
+                               regulator-2p5@20c8130 {
+                                       reg = <0x20c8130>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd2p5";
                                        regulator-min-microvolt = <2100000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               reg_arm: regulator-vddcore {
+                               reg_arm: regulator-vddcore@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddarm";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_pu: regulator-vddpu {
+                               reg_pu: regulator-vddpu@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddpu";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_soc: regulator-vddsoc {
+                               reg_soc: regulator-vddsoc@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;
index 4500380..07ba518 100644 (file)
                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
 
-                               regulator-1p1 {
+                               regulator-1p1@20c8110 {
+                                       reg = <0x20c8110>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd1p1";
                                        regulator-min-microvolt = <800000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               regulator-3p0 {
+                               regulator-3p0@20c8120 {
+                                       reg = <0x20c8120>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2800000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               regulator-2p5 {
+                               regulator-2p5@20c8130 {
+                                       reg = <0x20c8130>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd2p5";
                                        regulator-min-microvolt = <2100000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               reg_arm: regulator-vddcore {
+                               reg_arm: regulator-vddcore@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddarm";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_pcie: regulator-vddpcie {
+                               reg_pcie: regulator-vddpcie@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddpcie";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_soc: regulator-vddsoc {
+                               reg_soc: regulator-vddsoc@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;
index ed55e0c..1b14e4d 100644 (file)
                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
 
-                               reg_3p0: regulator-3p0 {
+                               reg_3p0: regulator-3p0@20c8110 {
+                                       reg = <0x20c8110>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2625000>;
                                        anatop-enable-bit = <0>;
                                };
 
-                               reg_arm: regulator-vddcore {
+                               reg_arm: regulator-vddcore@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "cpu";
                                        regulator-min-microvolt = <725000>;
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_soc: regulator-vddsoc {
+                               reg_soc: regulator-vddsoc@20c8140 {
+                                       reg = <0x20c8140>;
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;