ARM: ux500: select L2X0 cache on ux500

The cache controller needs to be enabled for the
cortex-a9 specific errata that are also selected
to work.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 34b6314..41b38bb 100644 (file)
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,6 +8,7 @@ config UX500_SOC_COMMON
        select ARM_ERRATA_753970
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369
+       select CACHE_L2X0
 
 config UX500_SOC_DB5500
        bool