arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 17 Feb 2023 18:52:24 +0000 (18:52 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 11 May 2023 14:03:07 +0000 (23:03 +0900)
[ Upstream commit 5da750ddd96454757a3b467e968e3fb70bb12bc8 ]

From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI
channels have been updated,

SPI 329 - SSIF0 is now marked as reserved
SPI 333 - SSIF1 is now marked as reserved
SPI 335 - SSIF2 is now marked as reserved
SPI 336 - SSIF2 is now marked as reserved
SPI 341 - SSIF3 is now marked as reserved

This patch drops the above IRQs from SoC DTSI.

Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/renesas/r9a07g044.dtsi

index 2283d4f..7dbf6a6 100644 (file)
                        reg = <0 0x10049c00 0 0x400>;
                        interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
-                       interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+                                    <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "int_req", "dma_rx", "dma_tx";
                        clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
                                 <&audio_clk1>, <&audio_clk2>;
                        reg = <0 0x1004a000 0 0x400>;
                        interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
-                       interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+                                    <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "int_req", "dma_rx", "dma_tx";
                        clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
                                 <&audio_clk1>, <&audio_clk2>;
                                     "renesas,rz-ssi";
                        reg = <0 0x1004a400 0 0x400>;
                        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
-                       interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+                       interrupt-names = "int_req", "dma_rt";
                        clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
                                 <&audio_clk1>, <&audio_clk2>;
                        reg = <0 0x1004a800 0 0x400>;
                        interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
-                       interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
+                                    <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "int_req", "dma_rx", "dma_tx";
                        clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
                                 <&audio_clk1>, <&audio_clk2>;