drm/amd/display: filter out invalid bits in pipe_fuses

[Why]
Reading pipe_fuses from register may have invalid bits set, which may
 affect the num_pipes erroneously.

[How]
Add read_pipes_fuses() call and filter bits based on expected number
 of pipes.

Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index a876e6e..22dd1eb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -2079,6 +2079,14 @@ static struct resource_funcs dcn32_res_pool_funcs = {
        .restore_mall_state = dcn32_restore_mall_state,
 };
 
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+       uint32_t value = REG_READ(CC_DC_PIPE_DIS);
+       /* DCN32 support max 4 pipes */
+       value = value & 0xf;
+       return value;
+}
+
 
 static bool dcn32_resource_construct(
        uint8_t num_virtual_links,
@@ -2122,7 +2130,7 @@ static bool dcn32_resource_construct(
        pool->base.res_cap = &res_cap_dcn32;
        /* max number of pipes for ASIC before checking for pipe fuses */
        num_pipes  = pool->base.res_cap->num_timing_generator;
-       pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
+       pipe_fuses = read_pipe_fuses(ctx);
 
        for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
                if (pipe_fuses & 1 << i)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index e5ab7f3..a60ddb3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -1632,6 +1632,14 @@ static struct resource_funcs dcn321_res_pool_funcs = {
        .restore_mall_state = dcn32_restore_mall_state,
 };
 
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+       uint32_t value = REG_READ(CC_DC_PIPE_DIS);
+       /* DCN321 support max 4 pipes */
+       value = value & 0xf;
+       return value;
+}
+
 
 static bool dcn321_resource_construct(
        uint8_t num_virtual_links,
@@ -1674,7 +1682,7 @@ static bool dcn321_resource_construct(
        pool->base.res_cap = &res_cap_dcn321;
        /* max number of pipes for ASIC before checking for pipe fuses */
        num_pipes  = pool->base.res_cap->num_timing_generator;
-       pipe_fuses = REG_READ(CC_DC_PIPE_DIS);
+       pipe_fuses = read_pipe_fuses(ctx);
 
        for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
                if (pipe_fuses & 1 << i)