cpu: exynos4: add ace sha base address
authorPrzemyslaw Marczak <p.marczak@samsung.com>
Tue, 25 Mar 2014 09:58:20 +0000 (10:58 +0100)
committerTom Rini <trini@ti.com>
Fri, 28 Mar 2014 19:06:31 +0000 (15:06 -0400)
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/include/asm/arch-exynos/cpu.h

index bccce63..fdf73b5 100644 (file)
@@ -25,8 +25,9 @@
 #define EXYNOS4_SYSTIMER_BASE          0x10050000
 #define EXYNOS4_WATCHDOG_BASE          0x10060000
 #define EXYNOS4_TZPC_BASE              0x10110000
-#define EXYNOS4_MIU_BASE               0x10600000
 #define EXYNOS4_DMC_CTRL_BASE          0x10400000
+#define EXYNOS4_MIU_BASE               0x10600000
+#define EXYNOS4_ACE_SFR_BASE           0x10830000
 #define EXYNOS4_GPIO_PART2_BASE                0x11000000
 #define EXYNOS4_GPIO_PART1_BASE                0x11400000
 #define EXYNOS4_FIMD_BASE              0x11C00000
@@ -48,7 +49,6 @@
 #define EXYNOS4_GPIO_PART4_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
-#define EXYNOS4_ACE_SFR_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DMC_PHY_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_AUDIOSS_BASE           DEVICE_NOT_AVAILABLE
 #define EXYNOS4_USB_HOST_XHCI_BASE     DEVICE_NOT_AVAILABLE
@@ -68,6 +68,7 @@
 #define EXYNOS4X12_TZPC_BASE           0x10110000
 #define EXYNOS4X12_DMC_CTRL_BASE       0x10600000
 #define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
+#define EXYNOS4X12_ACE_SFR_BASE                0x10830000
 #define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
 #define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
 #define EXYNOS4X12_FIMD_BASE           0x11C00000
@@ -87,7 +88,6 @@
 #define EXYNOS4X12_I2S_BASE            DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_ACE_SFR_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_DMC_PHY_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_AUDIOSS_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4X12_USB_HOST_XHCI_BASE  DEVICE_NOT_AVAILABLE
 #define EXYNOS5_SYSREG_BASE            0x10050000
 #define EXYNOS5_TZPC_BASE              0x10100000
 #define EXYNOS5_WATCHDOG_BASE          0x101D0000
-#define EXYNOS5_ACE_SFR_BASE            0x10830000
+#define EXYNOS5_ACE_SFR_BASE           0x10830000
 #define EXYNOS5_DMC_PHY_BASE           0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE                0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE          0x10DD0000