stm32mp: limit size of cacheable DDR in pre-reloc stage

In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 478fd2f17d0e15bf39e81d2bf64b382a1b1d100a..f538d7cb838ead8d447714d4622f54755855e531 100644 (file)
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -93,6 +93,19 @@ config SYS_TEXT_BASE
 config NR_DRAM_BANKS
        default 1
 
+config DDR_CACHEABLE_SIZE
+       hex "Size of the DDR marked cacheable in pre-reloc stage"
+       default 0x10000000 if TFABOOT
+       default 0x40000000
+       help
+               Define the size of the DDR marked as cacheable in U-Boot
+               pre-reloc stage.
+               This option can be useful to avoid speculatif access
+               to secured area of DDR used by TF-A or OP-TEE before U-Boot
+               initialization.
+               The areas marked "no-map" in device tree should be located
+               before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
+
 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
        hex "Partition on MMC2 to use to load U-Boot from"
        depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index f19e5c3f33a094c6bf2c7cb39ad89448f7ae42d8..6785ab6b5823b84fe9dafdca347ff3731efcca3e 100644 (file)
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -230,7 +230,8 @@ static void early_enable_caches(void)
                        round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
                        DCACHE_DEFAULT_OPTION);
        else
-               mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+               mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+                                               CONFIG_DDR_CACHEABLE_SIZE,
                                                DCACHE_DEFAULT_OPTION);
 }
 

diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c
index e84bdad7bfc06ab7329877638271df2f7e04c43a..b679b0a64544a5364fe4a10602594ee8b0209874 100644 (file)
--- a/arch/arm/mach-stm32mp/spl.c
+++ b/arch/arm/mach-stm32mp/spl.c
@@ -138,7 +138,8 @@ void board_init_f(ulong dummy)
         * to avoid speculative access and issue in get_ram_size()
         */
        if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
-               mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
+               mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
+                                               CONFIG_DDR_CACHEABLE_SIZE,
                                                DCACHE_DEFAULT_OPTION);
 }