;; MVE mode iterator.
(define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF])
+(define_mode_iterator MVE_vecs [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
(define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF])
(define_mode_iterator MVE_0 [V8HF V4SF])
(define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI])
(V4HI "HI") (V8HI "HI")
(V4HF "HF") (V8HF "HF")
(V4BF "BF") (V8BF "BF")
- (V2SI "SI") (V4SI "SI")
- (V2SF "SF") (V4SF "SF")
- (DI "DI") (V2DI "DI")])
+ (V2SI "SI") (V4SI "SI")
+ (V2SF "SF") (V4SF "SF")
+ (DI "DI") (V2DI "DI")
+ (V2DF "DF")])
;; As above but in lower case.
(define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi")
(set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*")
(set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")])
-(define_insn "*mve_mov<mode>"
- [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w")
- (vec_duplicate:MVE_types
- (match_operand:SI 1 "nonmemory_operand" "r,i")))]
+(define_insn "*mve_vdup<mode>"
+ [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w")
+ (vec_duplicate:MVE_vecs
+ (match_operand:<V_elem> 1 "s_register_operand" "r")))]
"TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
-{
- if (which_alternative == 0)
- return "vdup.<V_sz_elem>\t%q0, %1";
- return "vmov.<V_sz_elem>\t%q0, %1";
-}
- [(set_attr "length" "4,4")
- (set_attr "type" "mve_move,mve_move")])
+ "vdup.<V_sz_elem>\t%q0, %1"
+ [(set_attr "length" "4")
+ (set_attr "type" "mve_move")])
;;
;; [vst4q])
[(set_attr "type" "mve_move")
(set_attr "length" "8")])
-(define_insn "*mve_vec_duplicate<mode>"
- [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w")
- (vec_duplicate:MVE_VLD_ST (match_operand:<V_elem> 1 "general_operand" "r")))]
- "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT"
- "vdup.<V_sz_elem>\t%q0, %1"
- [(set_attr "type" "mve_move")])
-
;; CDE instructions on MVE registers.
(define_insn "arm_vcx1qv16qi"