pq: fix sr registers load fail on txl [1/1]
authorBencheng Jing <bencheng.jing@amlogic.com>
Thu, 6 Dec 2018 08:53:17 +0000 (16:53 +0800)
committerLuan Yuan <luan.yuan@amlogic.com>
Mon, 17 Dec 2018 09:24:05 +0000 (17:24 +0800)
PD#SWPL-2941

Problem:
sr top ctrl is closed when video off

Solution:
txl and txl sr top don't close

Verify:
TxL

Change-Id: Ia8e7e3bd93dd328497af66cf9758e3021cafe22c
Signed-off-by: Bencheng Jing <bencheng.jing@amlogic.com>
drivers/amlogic/media/enhancement/amvecm/amvecm.c
drivers/amlogic/media/video_sink/video.c

index c1789ab..027c4d0 100644 (file)
@@ -5421,7 +5421,10 @@ void init_pq_setting(void)
        }
        /*probe close sr0 peaking for switch on video*/
        WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1);
-       WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 0, 0, 1);
+       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
+               WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 0, 0, 1);
+       else
+               WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1, 0, 1);
        /*default dnlp off*/
        WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0],
                0, 1, 1);
index 59aa48b..cab9f2f 100644 (file)
@@ -6331,8 +6331,11 @@ SET_FILTER:
                                vpp_misc_set &= ~(VPP_VD2_PREBLEND |
                                        VPP_VD2_POSTBLEND | VPP_PREBLEND_EN);
                        /*auto disable sr when video off*/
-                       VSYNC_WR_MPEG_REG(VPP_SRSHARP0_CTRL, 0);
-                       VSYNC_WR_MPEG_REG(VPP_SRSHARP1_CTRL, 0);
+                       if (!is_meson_txl_cpu() &&
+                               !is_meson_txlx_cpu()) {
+                               VSYNC_WR_MPEG_REG(VPP_SRSHARP0_CTRL, 0);
+                               VSYNC_WR_MPEG_REG(VPP_SRSHARP1_CTRL, 0);
+                       }
                        video_onoff_state = VIDEO_ENABLE_STATE_IDLE;
                        video_onoff_time = jiffies_to_msecs(jiffies);
                        vpu_delay_work_flag |=