Impl GT_DIV in genCodeForTreeNode for Ryujit ARM32

Implement GT_DIV in genCodeForTreeNode for ryujit ARM32.
The case of "Zero Exception of Integer Division" is not yet implemented.

Commit migrated from https://github.com/dotnet/coreclr/commit/c9782caf4b9a0ec9cc891e843d27ac98913cf0f9

diff --git a/src/coreclr/src/jit/codegenarm.cpp b/src/coreclr/src/jit/codegenarm.cpp
index a7bd931..70fe531 100644 (file)
--- a/src/coreclr/src/jit/codegenarm.cpp
+++ b/src/coreclr/src/jit/codegenarm.cpp
@@ -492,10 +492,39 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode)
 
         case GT_DIV:
         {
-            NYI("GT_DIV");
-        }
+            genConsumeOperands(treeNode->AsOp());
+
+            noway_assert(targetReg != REG_NA);
+
+            GenTreePtr  dst    = treeNode;
+            GenTreePtr  src1   = treeNode->gtGetOp1();
+            GenTreePtr  src2   = treeNode->gtGetOp2();
+            instruction ins    = genGetInsForOper(treeNode->OperGet(), targetType);
+            emitAttr    attr   = emitTypeSize(treeNode);
+            regNumber   result = REG_NA;
+
+            // dst can only be a reg
+            assert(!dst->isContained());
+
+            // src can be only reg
+            assert(!src1->isContained() || !src2->isContained());
+
+            if (varTypeIsFloating(targetType))
+            {
+                // Floating point divide never raises an exception
+
+                emit->emitIns_R_R_R(ins, attr, dst->gtRegNum, src1->gtRegNum, src2->gtRegNum);
+            }
+            else // an signed integer divide operation
+            {
+                // TODO-ARM-Bug: handle zero division exception.
+
+                emit->emitIns_R_R_R(ins, attr, dst->gtRegNum, src1->gtRegNum, src2->gtRegNum);
+            }
+
             genProduceReg(treeNode);
-            break;
+        }
+        break;
 
         case GT_INTRINSIC:
         {
@@ -964,6 +993,9 @@ instruction CodeGen::genGetInsForOper(genTreeOps oper, var_types type)
         case GT_MUL:
             ins = INS_MUL;
             break;
+        case GT_DIV:
+            ins = INS_sdiv;
+            break;
         case GT_LSH:
             ins = INS_SHIFT_LEFT_LOGICAL;
             break;