sbc35_a9g20: update board to the new AT91 organization
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thu, 4 Aug 2011 02:22:20 +0000 (02:22 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 3 Sep 2011 20:40:44 +0000 (22:40 +0200)
Cc: Albin Tonnerre <tonnerrealbin@gmail.com>
Cc: Gregory Hermant <gregory.hermant@calao-systems.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Removed SBC35 from MAKEALL

MAKEALL
Makefile
board/calao/sbc35_a9g20/sbc35_a9g20.c
boards.cfg
include/configs/sbc35_a9g20.h

diff --git a/MAKEALL b/MAKEALL
index 3b98f03..0ec6685 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -446,7 +446,6 @@ LIST_ARMV7="                \
 LIST_at91="$(boards_by_soc at91)\
        at91sam9m10g45ek        \
        pm9g45                  \
-       SBC35_A9G20             \
        TNY_A9260               \
        TNY_A9G20               \
 "
index 03d80b7..47dc73f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -827,13 +827,6 @@ pm9g45_config      :       unconfig
        @mkdir -p $(obj)include
        @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
 
-SBC35_A9G20_NANDFLASH_config \
-SBC35_A9G20_EEPROM_config \
-SBC35_A9G20_config     :       unconfig
-       @mkdir -p $(obj)include
-       @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
-       @$(MKCONFIG) -n $@ -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
-
 TNY_A9G20_NANDFLASH_config \
 TNY_A9G20_EEPROM_config \
 TNY_A9G20_config \
index 9df45c0..5f448d9 100644 (file)
  */
 
 #include <common.h>
-#include <asm/arch/at91sam9260.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
-#include <asm/arch/hardware.h>
+
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -50,33 +49,36 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_CMD_NAND
 static void sbc35_a9g20_nand_hw_init(void)
 {
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+       struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
        unsigned long csa;
 
        /* Enable CS3 */
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA,
-                      csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = readl(&matrix->ebicsa);
+       csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+       writel(csa, &matrix->ebicsa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-       at91_sys_write(AT91_SMC_MODE(3),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+               &smc->cs[3].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+               AT91_SMC_MODE_EXNW_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
-                      AT91_SMC_DBW_16 |
+               AT91_SMC_MODE_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
-                      AT91_SMC_DBW_8 |
+               AT91_SMC_MODE_DBW_8 |
 #endif
-                      AT91_SMC_TDF_(2));
+               AT91_SMC_MODE_TDF_CYCLE(2),
+               &smc->cs[3].mode);
 
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+       writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
        /* Configure RDY/BSY */
        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -89,10 +91,13 @@ static void sbc35_a9g20_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void sbc35_a9g20_macb_hw_init(void)
 {
-       unsigned long rstc;
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+       struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+       unsigned long erstl;
 
-       /* Enable clock */
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+       /* Enable EMAC clock */
+       writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
        /*
         * Disable pull-up on:
@@ -111,24 +116,23 @@ static void sbc35_a9g20_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA25) |
               pin_to_mask(AT91_PIN_PA26) |
               pin_to_mask(AT91_PIN_PA28),
-              pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
+              &pioa->pudr);
 
-       rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+       erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 
        /* Need to reset PHY -> 500ms reset */
-       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-                                    (AT91_RSTC_ERSTL & (0x0D << 8)) |
-                                    AT91_RSTC_URSTEN);
+       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+               AT91_RSTC_MR_URSTEN, &rstc->mr);
 
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 
        /* Wait for end hardware reset */
-       while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+               ;
 
        /* Restore NRST value */
-       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-                                    (rstc) |
-                                    AT91_RSTC_URSTEN);
+       writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
+               &rstc->mr);
 
        /* Re-enable pull-up */
        writel(pin_to_mask(AT91_PIN_PA14) |
@@ -137,7 +141,7 @@ static void sbc35_a9g20_macb_hw_init(void)
               pin_to_mask(AT91_PIN_PA25) |
               pin_to_mask(AT91_PIN_PA26) |
               pin_to_mask(AT91_PIN_PA28),
-              pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+              &pioa->puer);
 
        at91_macb_hw_init();
 }
@@ -150,9 +154,9 @@ int board_init(void)
 
        gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
        /* adress of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-       at91_serial_hw_init();
+       at91_seriald_hw_init();
        sbc35_a9g20_nand_hw_init();
 #ifdef CONFIG_ATMEL_SPI
        at91_spi0_hw_init(1 << 4 | 1 << 5);
@@ -166,11 +170,9 @@ int board_init(void)
 
 int dram_init(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM;
-       if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
-               return -1;
-
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size(
+               (void *)CONFIG_SYS_SDRAM_BASE,
+               CONFIG_SYS_SDRAM_SIZE);
        return 0;
 }
 
@@ -184,7 +186,7 @@ int board_eth_init(bd_t *bis)
 {
        int rc = 0;
 #ifdef CONFIG_MACB
-       rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+       rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 #endif
        return rc;
 }
index c253f03..89d4c7a 100644 (file)
@@ -102,6 +102,8 @@ at91sam9xeek_dataflash_cs0   arm         arm926ejs   at91sam9260ek       atmel
 at91sam9xeek_dataflash_cs1   arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
 snapper9260                  arm         arm926ejs   -                   bluewater      at91        snapper9260:AT91SAM9260
 snapper9g20                  arm         arm926ejs   snapper9260         bluewater      at91        snapper9260:AT91SAM9G20
+sbc35_a9g20_nandflash        arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
+sbc35_a9g20_eeprom           arm         arm926ejs   sbc35_a9g20         calao          at91        sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
 cpu9260                      arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260
 cpu9260_nand                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,NANDBOOT
 cpu9260_128M                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,CPU9260_128M
index 00f4dc9..967a991 100644 (file)
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <asm/sizes.h>
 
-#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
-#define CONFIG_SBC35_A9G20
-#endif
-
-#define CONFIG_AT91SAM9G20
-
-#if defined(CONFIG_SBC35_A9G20_NANDFLASH)
+#if defined(CONFIG_SYS_USE_NANDFLASH)
 #define CONFIG_ENV_IS_IN_NAND
 #else
 #define CONFIG_ENV_IS_IN_EEPROM
 #endif
 
 /* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK     32768           /* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK     12000000        /* 12.000 MHz crystal */
-#define CONFIG_SYS_HZ          1000
-
-#define CONFIG_ARM926EJS       1       /* This is an ARM926EJS Core    */
+#define CONFIG_SYS_HZ                  1000
 
 #define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
 
-#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS       1
-#define CONFIG_INITRD_TAG              1
-
+#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-/*
- * Hardware drivers
- */
-#define CONFIG_AT91_GPIO       1
+/* GPIO */
+#define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* Serial */
 #define CONFIG_ATMEL_USART
-#define CONFIG_USART0
-#undef CONFIG_USART1
-#undef CONFIG_USART2
-#undef CONFIG_USART3
+#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
+#define CONFIG_USART_ID                 ATMEL_ID_SYS
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
 
 #define CONFIG_BOOTDELAY       3
 
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-#define CONFIG_BOOTP_BOOTPATH          1
-#define CONFIG_BOOTP_GATEWAY           1
-#define CONFIG_BOOTP_HOSTNAME          1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
 
 /*
  * Command line configuration.
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_SOURCE
 
-#define CONFIG_CMD_PING                1
-#define CONFIG_CMD_DHCP                1
-#define CONFIG_CMD_USB         1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_USB
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS   1
-#define PHYS_SDRAM             0x20000000
-#define PHYS_SDRAM_SIZE                0x04000000      /* 64 megs */
+#define CONFIG_SYS_SDRAM_BASE  ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE  0x04000000      /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR        (ATMEL_BASE_SRAM1 + 0x1000 - \
+                                GENERATED_GBL_DATA_SIZE)
 
 /* SPI EEPROM */
 #define CONFIG_SPI
 #define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   0x40000000
-#define CONFIG_SYS_NAND_DBW_8                  1
+#define CONFIG_SYS_NAND_DBW_8
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NO_FLASH                    1
 
 /* Ethernet */
-#define CONFIG_MACB                    1
-#define CONFIG_RMII                    1
-#define CONFIG_NET_MULTI               1
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT         20
-#define CONFIG_RESET_PHY_R             1
-#define CONFIG_MACB_SEARCH_PHY         1
+#define CONFIG_RESET_PHY_R
+#define CONFIG_MACB_SEARCH_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
-#define CONFIG_USB_OHCI_NEW            1
-#define CONFIG_DOS_PARTITION           1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT   1
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE  0x00500000      /* AT91SAM9260_UHP_BASE */
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME  "at91sam9260"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
-#define CONFIG_USB_STORAGE             1
-#define CONFIG_CMD_FAT                 1
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
 
 #define CONFIG_SYS_LOAD_ADDR           0x22000000      /* load address */
 
-#define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END         0x23e00000
 
 /* Env in EEPROM, bootstrap + u-boot in NAND*/
                                "120M(rootfs),-(other) " \
                                "rw rootfstype=jffs2"
 
-#define CONFIG_BAUDRATE                        115200
-#define CONFIG_SYS_BAUDRATE_TABLE      {115200 , 19200, 38400, 57600, 9600 }
 
 #define CONFIG_SYS_PROMPT      "U-Boot> "
 #define CONFIG_SYS_CBSIZE      256