drm/i915: Fix DP link training pattern mask

An LTTPR can be trained with training pattern 4 even if the DPCD
revision is < 1.4, but drm_dp_training_pattern_mask() would change
pattern 4 to pattern 3 on those DPCD revisions.

Since intel_dp_training_pattern() makes already sure that the proper
training pattern is used, all that needs to be masked out is the
scrambling disable flag, which is or'd to the mask later based on the
training pattern.

v2:
- Use a helper instead of open-coding the masking. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007170917.1764556-2-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 85fa36c56c8aa5850a2a452a8d45b4a63d752c6a..35edbd8264437b0ca7fc937b820e11458114d309 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4254,13 +4254,12 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 {
        struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
        u32 temp;
 
        temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
        temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
-       switch (dp_train_pat & train_pat_mask) {
+       switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
        case DP_TRAINING_PATTERN_DISABLE:
                temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
                break;

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 329d129dec8fa217cfc3e957c5a64b73dc9e9aef..53150b0392cf2d1eba93449771ccdc8d69795229 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3829,7 +3829,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 
        *DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
-       switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+       switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
        case DP_TRAINING_PATTERN_DISABLE:
                *DP |= DP_LINK_TRAIN_OFF_CPT;
                break;
@@ -3860,7 +3860,7 @@ g4x_set_link_train(struct intel_dp *intel_dp,
 
        *DP &= ~DP_LINK_TRAIN_MASK;
 
-       switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+       switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
        case DP_TRAINING_PATTERN_DISABLE:
                *DP |= DP_LINK_TRAIN_OFF;
                break;
@@ -4562,12 +4562,12 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
                                       u8 dp_train_pat)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-       u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
 
-       if (dp_train_pat & train_pat_mask)
+       if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
+           DP_TRAINING_PATTERN_DISABLE)
                drm_dbg_kms(&dev_priv->drm,
                            "Using DP training pattern TPS%d\n",
-                           dp_train_pat & train_pat_mask);
+                           intel_dp_training_pattern_symbol(dp_train_pat));
 
        intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 51e8d46d9b7f588cfec8ae854472d750c4f370e3..b2ff88a152cd9d15c36b92a89d7cd792e7373391 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -100,7 +100,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
                                               dp_train_pat);
 
        buf[0] = dp_train_pat;
-       if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
+       if (intel_dp_training_pattern_symbol(dp_train_pat) ==
            DP_TRAINING_PATTERN_DISABLE) {
                /* don't write DP_TRAINING_LANEx_SET on disable */
                len = 1;

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 648a6d1f9fa2c7aac848d3486857899cc6332c33..bf9474e41aedf9a19e10ec7eed9ac151f9f2ab7c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -19,4 +19,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
                              const struct intel_crtc_state *crtc_state);
 
+/* Get the TPSx symbol type of the value programmed to DP_TRAINING_PATTERN_SET */
+static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
+{
+       return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
+}
+
 #endif /* __INTEL_DP_LINK_TRAINING_H__ */