radv: add rb+ support for GFX9
authorDave Airlie <airlied@redhat.com>
Mon, 5 Jun 2017 23:03:55 +0000 (09:03 +1000)
committerDave Airlie <airlied@redhat.com>
Mon, 5 Jun 2017 23:43:45 +0000 (09:43 +1000)
This adds some rb+ support, as on GFX9 we have to disable
it as per radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
src/amd/vulkan/radv_cmd_buffer.c
src/amd/vulkan/radv_device.c
src/amd/vulkan/radv_meta_clear.c
src/amd/vulkan/radv_private.h
src/amd/vulkan/si_cmd_buffer.c

index d078421..4fd0f4c 100644 (file)
@@ -366,6 +366,13 @@ radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
                          8);
        radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
        radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
+
+       if (cmd_buffer->device->physical_device->has_rbplus) {
+               radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
+               radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
+               radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
+               radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
+       }
 }
 
 static void
index 9d510ea..d32c972 100644 (file)
@@ -304,6 +304,12 @@ radv_physical_device_init(struct radv_physical_device *device,
 
        radv_get_device_uuid(drm_device, device->device_uuid);
 
+       if (device->rad_info.family == CHIP_STONEY ||
+           device->rad_info.chip_class >= GFX9) {
+               device->has_rbplus = true;
+               device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
+       }
+
        return VK_SUCCESS;
 
 fail:
index 66b77f4..f4cb787 100644 (file)
@@ -915,6 +915,11 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
        if (clear_rect->layerCount != iview->image->info.array_size)
                goto fail;
 
+       /* RB+ doesn't work with CMASK fast clear on Stoney. */
+       if (!iview->image->surface.dcc_size &&
+           cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY)
+               goto fail;
+
        /* DCC */
        ret = radv_format_pack_clear_color(iview->image->vk_format,
                                           clear_color, &clear_value);
index 6a6c1e2..ed80ba7 100644 (file)
@@ -273,6 +273,9 @@ struct radv_physical_device {
        int local_fd;
        struct wsi_device                       wsi_device;
        struct radv_extensions                      extensions;
+
+       bool has_rbplus; /* if RB+ register exist */
+       bool rbplus_allowed; /* if RB+ is allowed */
 };
 
 struct radv_instance {
index 3e0b8ee..397ea81 100644 (file)
@@ -452,7 +452,7 @@ si_emit_config(struct radv_physical_device *physical_device,
                radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
        }
 
-       if (physical_device->rad_info.family == CHIP_STONEY)
+       if (physical_device->has_rbplus)
                radeon_set_context_reg(cs, R_028C40_PA_SC_SHADER_CONTROL, 0);
 
        if (physical_device->rad_info.chip_class >= GFX9) {