[AArch64][PR target/84882] Add mno-strict-align
authorSudakshina Das <sudi.das@arm.com>
Wed, 23 May 2018 11:33:09 +0000 (11:33 +0000)
committerSudakshina Das <sudi@gcc.gnu.org>
Wed, 23 May 2018 11:33:09 +0000 (11:33 +0000)
*** gcc/ChangeLog ***

2018-05-23  Sudakshina Das  <sudi.das@arm.com>

PR target/84882
* common/config/aarch64/aarch64-common.c (aarch64_handle_option):
Check val before adding MASK_STRICT_ALIGN to opts->x_target_flags.
* config/aarch64/aarch64.opt (mstrict-align): Remove RejectNegative.
* config/aarch64/aarch64.c (aarch64_attributes): Mark allow_neg
as true for strict-align.
(aarch64_can_inline_p): Perform checks even when callee has no
attributes to check for strict alignment.
* doc/extend.texi (AArch64 Function Attributes): Document
no-strict-align.
* doc/invoke.texi: (AArch64 Options): Likewise.

*** gcc/testsuite/ChangeLog ***

2018-05-23  Sudakshina Das  <sudi.das@arm.com>

PR target/84882
* gcc.target/aarch64/pr84882.c: New test.
* gcc.target/aarch64/target_attr_18.c: Likewise.

From-SVN: r260604

gcc/ChangeLog
gcc/common/config/aarch64/aarch64-common.c
gcc/config/aarch64/aarch64.c
gcc/config/aarch64/aarch64.opt
gcc/doc/extend.texi
gcc/doc/invoke.texi
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/pr84882.c [new file with mode: 0644]
gcc/testsuite/gcc.target/aarch64/target_attr_18.c [new file with mode: 0644]

index 0050748..439b830 100644 (file)
@@ -1,3 +1,17 @@
+2018-05-23  Sudakshina Das  <sudi.das@arm.com>
+
+       PR target/84882
+       * common/config/aarch64/aarch64-common.c (aarch64_handle_option):
+       Check val before adding MASK_STRICT_ALIGN to opts->x_target_flags.
+       * config/aarch64/aarch64.opt (mstrict-align): Remove RejectNegative.
+       * config/aarch64/aarch64.c (aarch64_attributes): Mark allow_neg
+       as true for strict-align.
+       (aarch64_can_inline_p): Perform checks even when callee has no
+       attributes to check for strict alignment.
+       * doc/extend.texi (AArch64 Function Attributes): Document
+       no-strict-align.
+       * doc/invoke.texi: (AArch64 Options): Likewise.
+
 2018-05-23  Richard Sandiford  <richard.sandiford@linaro.org>
 
        PR tree-optimization/85853
index a9fc5f1..292fb81 100644 (file)
@@ -101,7 +101,10 @@ aarch64_handle_option (struct gcc_options *opts,
       return true;
 
     case OPT_mstrict_align:
-      opts->x_target_flags |= MASK_STRICT_ALIGN;
+      if (val)
+       opts->x_target_flags |= MASK_STRICT_ALIGN;
+      else
+       opts->x_target_flags &= ~MASK_STRICT_ALIGN;
       return true;
 
     case OPT_momit_leaf_frame_pointer:
index f60e0ad..1df8d62 100644 (file)
@@ -11298,7 +11298,7 @@ static const struct aarch64_attribute_info aarch64_attributes[] =
   { "fix-cortex-a53-843419", aarch64_attr_bool, true, NULL,
      OPT_mfix_cortex_a53_843419 },
   { "cmodel", aarch64_attr_enum, false, NULL, OPT_mcmodel_ },
-  { "strict-align", aarch64_attr_mask, false, NULL, OPT_mstrict_align },
+  { "strict-align", aarch64_attr_mask, true, NULL, OPT_mstrict_align },
   { "omit-leaf-frame-pointer", aarch64_attr_bool, true, NULL,
      OPT_momit_leaf_frame_pointer },
   { "tls-dialect", aarch64_attr_enum, false, NULL, OPT_mtls_dialect_ },
@@ -11661,16 +11661,13 @@ aarch64_can_inline_p (tree caller, tree callee)
   tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
   tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
 
-  /* If callee has no option attributes, then it is ok to inline.  */
-  if (!callee_tree)
-    return true;
-
   struct cl_target_option *caller_opts
        = TREE_TARGET_OPTION (caller_tree ? caller_tree
                                           : target_option_default_node);
 
-  struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
-
+  struct cl_target_option *callee_opts
+       = TREE_TARGET_OPTION (callee_tree ? callee_tree
+                                          : target_option_default_node);
 
   /* Callee's ISA flags should be a subset of the caller's.  */
   if ((caller_opts->x_aarch64_isa_flags & callee_opts->x_aarch64_isa_flags)
index 52eaf8c..1426b45 100644 (file)
@@ -85,7 +85,7 @@ Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_C
 Specify the code model.
 
 mstrict-align
-Target Report RejectNegative Mask(STRICT_ALIGN) Save
+Target Report Mask(STRICT_ALIGN) Save
 Don't assume that unaligned accesses are handled by the system.
 
 momit-leaf-frame-pointer
index b738b84..ab1db49 100644 (file)
@@ -3612,10 +3612,13 @@ this function.  The behavior and permissible arguments are the same as
 for the command line option @option{-mcmodel=}.
 
 @item strict-align
+@itemx no-strict-align
 @cindex @code{strict-align} function attribute, AArch64
-Indicates that the compiler should not assume that unaligned memory references
-are handled by the system.  The behavior is the same as for the command-line
-option @option{-mstrict-align}.
+@code{strict-align} indicates that the compiler should not assume that unaligned
+memory references are handled by the system.  To allow the compiler to assume
+that aligned memory references are handled by the system, the inverse attribute
+@code{no-strict-align} can be specified.  The behavior is same as for the
+command-line option @option{-mstrict-align} and @option{-mno-strict-align}.
 
 @item omit-leaf-frame-pointer
 @cindex @code{omit-leaf-frame-pointer} function attribute, AArch64
index beba295..30d2a31 100644 (file)
@@ -596,7 +596,7 @@ Objective-C and Objective-C++ Dialects}.
 @gccoptlist{-mabi=@var{name}  -mbig-endian  -mlittle-endian @gol
 -mgeneral-regs-only @gol
 -mcmodel=tiny  -mcmodel=small  -mcmodel=large @gol
--mstrict-align @gol
+-mstrict-align -mno-strict-align @gol
 -momit-leaf-frame-pointer @gol
 -mtls-dialect=desc  -mtls-dialect=traditional @gol
 -mtls-size=@var{size} @gol
@@ -14594,9 +14594,11 @@ Generate code for the large code model.  This makes no assumptions about
 addresses and sizes of sections.  Programs can be statically linked only.
 
 @item -mstrict-align
+@itemx -mno-strict-align
 @opindex mstrict-align
-Avoid generating memory accesses that may not be aligned on a natural object
-boundary as described in the architecture specification.
+@opindex mno-strict-align
+Avoid or allow generating memory accesses that may not be aligned on a natural
+object boundary as described in the architecture specification.
 
 @item -momit-leaf-frame-pointer
 @itemx -mno-omit-leaf-frame-pointer
index b40a391..aea02b9 100644 (file)
@@ -1,3 +1,9 @@
+2018-05-23  Sudakshina Das  <sudi.das@arm.com>
+
+       PR target/84882
+       * gcc.target/aarch64/pr84882.c: New test.
+       * gcc.target/aarch64/target_attr_18.c: Likewise.
+
 2018-05-23  Richard Sandiford  <richard.sandiford@linaro.org>
 
        PR tree-optimization/85853
diff --git a/gcc/testsuite/gcc.target/aarch64/pr84882.c b/gcc/testsuite/gcc.target/aarch64/pr84882.c
new file mode 100644 (file)
index 0000000..89b5d1a
--- /dev/null
@@ -0,0 +1,34 @@
+/* This is a copy of pr71727.c with scanning reversed.  */
+/* { dg-do compile } */
+/* { dg-options "-mstrict-align -O3 -mno-strict-align" } */
+
+struct test_struct_s
+{
+  long a;
+  long b;
+  long c;
+  long d;
+  unsigned long e;
+};
+
+
+char _a;
+struct test_struct_s xarray[128];
+
+void
+_start (void)
+{
+  struct test_struct_s *new_entry;
+
+  new_entry = &xarray[0];
+  new_entry->a = 1;
+  new_entry->b = 2;
+  new_entry->c = 3;
+  new_entry->d = 4;
+  new_entry->e = 5;
+
+  return;
+}
+/* Should have only 1 mov instead of 5 and should not use stp (store pair).  */
+/* { dg-final { scan-assembler-times "mov\tx" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-not "stp\tx\[0-9\]+, x\[0-9\]+," {target lp64} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_18.c b/gcc/testsuite/gcc.target/aarch64/target_attr_18.c
new file mode 100644 (file)
index 0000000..33b1d44
--- /dev/null
@@ -0,0 +1,21 @@
+/* This is a copy of target_attr_6.c to instead check no-strict-align.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps -mstrict-align" } */
+
+/* Inlining strict-align functions into non-strict align
+   functions is not allowed.  */
+
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+__attribute__ ((target ("no-strict-align")))
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+/* { dg-final { scan-assembler "bl.*bar" } } */