drm/amdgpu: add GCA 8.0 register headers

These are register headers for the GCA (Graphics and Compute Array)
block on the GPU.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
new file mode 100644 (file)
index 0000000..daf763b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h
@@ -0,0 +1,2811 @@
+/*
+ * GFX_8_0 Register documentation
+ *
+ * Copyright (C) 2014  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_8_0_D_H
+#define GFX_8_0_D_H
+
+#define mmCB_BLEND_RED                                                          0xa105
+#define mmCB_BLEND_GREEN                                                        0xa106
+#define mmCB_BLEND_BLUE                                                         0xa107
+#define mmCB_BLEND_ALPHA                                                        0xa108
+#define mmCB_DCC_CONTROL                                                        0xa109
+#define mmCB_COLOR_CONTROL                                                      0xa202
+#define mmCB_BLEND0_CONTROL                                                     0xa1e0
+#define mmCB_BLEND1_CONTROL                                                     0xa1e1
+#define mmCB_BLEND2_CONTROL                                                     0xa1e2
+#define mmCB_BLEND3_CONTROL                                                     0xa1e3
+#define mmCB_BLEND4_CONTROL                                                     0xa1e4
+#define mmCB_BLEND5_CONTROL                                                     0xa1e5
+#define mmCB_BLEND6_CONTROL                                                     0xa1e6
+#define mmCB_BLEND7_CONTROL                                                     0xa1e7
+#define mmCB_COLOR0_BASE                                                        0xa318
+#define mmCB_COLOR1_BASE                                                        0xa327
+#define mmCB_COLOR2_BASE                                                        0xa336
+#define mmCB_COLOR3_BASE                                                        0xa345
+#define mmCB_COLOR4_BASE                                                        0xa354
+#define mmCB_COLOR5_BASE                                                        0xa363
+#define mmCB_COLOR6_BASE                                                        0xa372
+#define mmCB_COLOR7_BASE                                                        0xa381
+#define mmCB_COLOR0_PITCH                                                       0xa319
+#define mmCB_COLOR1_PITCH                                                       0xa328
+#define mmCB_COLOR2_PITCH                                                       0xa337
+#define mmCB_COLOR3_PITCH                                                       0xa346
+#define mmCB_COLOR4_PITCH                                                       0xa355
+#define mmCB_COLOR5_PITCH                                                       0xa364
+#define mmCB_COLOR6_PITCH                                                       0xa373
+#define mmCB_COLOR7_PITCH                                                       0xa382
+#define mmCB_COLOR0_SLICE                                                       0xa31a
+#define mmCB_COLOR1_SLICE                                                       0xa329
+#define mmCB_COLOR2_SLICE                                                       0xa338
+#define mmCB_COLOR3_SLICE                                                       0xa347
+#define mmCB_COLOR4_SLICE                                                       0xa356
+#define mmCB_COLOR5_SLICE                                                       0xa365
+#define mmCB_COLOR6_SLICE                                                       0xa374
+#define mmCB_COLOR7_SLICE                                                       0xa383
+#define mmCB_COLOR0_VIEW                                                        0xa31b
+#define mmCB_COLOR1_VIEW                                                        0xa32a
+#define mmCB_COLOR2_VIEW                                                        0xa339
+#define mmCB_COLOR3_VIEW                                                        0xa348
+#define mmCB_COLOR4_VIEW                                                        0xa357
+#define mmCB_COLOR5_VIEW                                                        0xa366
+#define mmCB_COLOR6_VIEW                                                        0xa375
+#define mmCB_COLOR7_VIEW                                                        0xa384
+#define mmCB_COLOR0_INFO                                                        0xa31c
+#define mmCB_COLOR1_INFO                                                        0xa32b
+#define mmCB_COLOR2_INFO                                                        0xa33a
+#define mmCB_COLOR3_INFO                                                        0xa349
+#define mmCB_COLOR4_INFO                                                        0xa358
+#define mmCB_COLOR5_INFO                                                        0xa367
+#define mmCB_COLOR6_INFO                                                        0xa376
+#define mmCB_COLOR7_INFO                                                        0xa385
+#define mmCB_COLOR0_ATTRIB                                                      0xa31d
+#define mmCB_COLOR1_ATTRIB                                                      0xa32c
+#define mmCB_COLOR2_ATTRIB                                                      0xa33b
+#define mmCB_COLOR3_ATTRIB                                                      0xa34a
+#define mmCB_COLOR4_ATTRIB                                                      0xa359
+#define mmCB_COLOR5_ATTRIB                                                      0xa368
+#define mmCB_COLOR6_ATTRIB                                                      0xa377
+#define mmCB_COLOR7_ATTRIB                                                      0xa386
+#define mmCB_COLOR0_DCC_CONTROL                                                 0xa31e
+#define mmCB_COLOR1_DCC_CONTROL                                                 0xa32d
+#define mmCB_COLOR2_DCC_CONTROL                                                 0xa33c
+#define mmCB_COLOR3_DCC_CONTROL                                                 0xa34b
+#define mmCB_COLOR4_DCC_CONTROL                                                 0xa35a
+#define mmCB_COLOR5_DCC_CONTROL                                                 0xa369
+#define mmCB_COLOR6_DCC_CONTROL                                                 0xa378
+#define mmCB_COLOR7_DCC_CONTROL                                                 0xa387
+#define mmCB_COLOR0_CMASK                                                       0xa31f
+#define mmCB_COLOR1_CMASK                                                       0xa32e
+#define mmCB_COLOR2_CMASK                                                       0xa33d
+#define mmCB_COLOR3_CMASK                                                       0xa34c
+#define mmCB_COLOR4_CMASK                                                       0xa35b
+#define mmCB_COLOR5_CMASK                                                       0xa36a
+#define mmCB_COLOR6_CMASK                                                       0xa379
+#define mmCB_COLOR7_CMASK                                                       0xa388
+#define mmCB_COLOR0_CMASK_SLICE                                                 0xa320
+#define mmCB_COLOR1_CMASK_SLICE                                                 0xa32f
+#define mmCB_COLOR2_CMASK_SLICE                                                 0xa33e
+#define mmCB_COLOR3_CMASK_SLICE                                                 0xa34d
+#define mmCB_COLOR4_CMASK_SLICE                                                 0xa35c
+#define mmCB_COLOR5_CMASK_SLICE                                                 0xa36b
+#define mmCB_COLOR6_CMASK_SLICE                                                 0xa37a
+#define mmCB_COLOR7_CMASK_SLICE                                                 0xa389
+#define mmCB_COLOR0_FMASK                                                       0xa321
+#define mmCB_COLOR1_FMASK                                                       0xa330
+#define mmCB_COLOR2_FMASK                                                       0xa33f
+#define mmCB_COLOR3_FMASK                                                       0xa34e
+#define mmCB_COLOR4_FMASK                                                       0xa35d
+#define mmCB_COLOR5_FMASK                                                       0xa36c
+#define mmCB_COLOR6_FMASK                                                       0xa37b
+#define mmCB_COLOR7_FMASK                                                       0xa38a
+#define mmCB_COLOR0_FMASK_SLICE                                                 0xa322
+#define mmCB_COLOR1_FMASK_SLICE                                                 0xa331
+#define mmCB_COLOR2_FMASK_SLICE                                                 0xa340
+#define mmCB_COLOR3_FMASK_SLICE                                                 0xa34f
+#define mmCB_COLOR4_FMASK_SLICE                                                 0xa35e
+#define mmCB_COLOR5_FMASK_SLICE                                                 0xa36d
+#define mmCB_COLOR6_FMASK_SLICE                                                 0xa37c
+#define mmCB_COLOR7_FMASK_SLICE                                                 0xa38b
+#define mmCB_COLOR0_CLEAR_WORD0                                                 0xa323
+#define mmCB_COLOR1_CLEAR_WORD0                                                 0xa332
+#define mmCB_COLOR2_CLEAR_WORD0                                                 0xa341
+#define mmCB_COLOR3_CLEAR_WORD0                                                 0xa350
+#define mmCB_COLOR4_CLEAR_WORD0                                                 0xa35f
+#define mmCB_COLOR5_CLEAR_WORD0                                                 0xa36e
+#define mmCB_COLOR6_CLEAR_WORD0                                                 0xa37d
+#define mmCB_COLOR7_CLEAR_WORD0                                                 0xa38c
+#define mmCB_COLOR0_CLEAR_WORD1                                                 0xa324
+#define mmCB_COLOR1_CLEAR_WORD1                                                 0xa333
+#define mmCB_COLOR2_CLEAR_WORD1                                                 0xa342
+#define mmCB_COLOR3_CLEAR_WORD1                                                 0xa351
+#define mmCB_COLOR4_CLEAR_WORD1                                                 0xa360
+#define mmCB_COLOR5_CLEAR_WORD1                                                 0xa36f
+#define mmCB_COLOR6_CLEAR_WORD1                                                 0xa37e
+#define mmCB_COLOR7_CLEAR_WORD1                                                 0xa38d
+#define mmCB_COLOR0_DCC_BASE                                                    0xa325
+#define mmCB_COLOR1_DCC_BASE                                                    0xa334
+#define mmCB_COLOR2_DCC_BASE                                                    0xa343
+#define mmCB_COLOR3_DCC_BASE                                                    0xa352
+#define mmCB_COLOR4_DCC_BASE                                                    0xa361
+#define mmCB_COLOR5_DCC_BASE                                                    0xa370
+#define mmCB_COLOR6_DCC_BASE                                                    0xa37f
+#define mmCB_COLOR7_DCC_BASE                                                    0xa38e
+#define mmCB_TARGET_MASK                                                        0xa08e
+#define mmCB_SHADER_MASK                                                        0xa08f
+#define mmCB_HW_CONTROL                                                         0x2684
+#define mmCB_HW_CONTROL_1                                                       0x2685
+#define mmCB_HW_CONTROL_2                                                       0x2686
+#define mmCB_HW_CONTROL_3                                                       0x2683
+#define mmCB_DCC_CONFIG                                                         0x2687
+#define mmCB_PERFCOUNTER_FILTER                                                 0xdc00
+#define mmCB_PERFCOUNTER0_SELECT                                                0xdc01
+#define mmCB_PERFCOUNTER0_SELECT1                                               0xdc02
+#define mmCB_PERFCOUNTER1_SELECT                                                0xdc03
+#define mmCB_PERFCOUNTER2_SELECT                                                0xdc04
+#define mmCB_PERFCOUNTER3_SELECT                                                0xdc05
+#define mmCB_PERFCOUNTER0_LO                                                    0xd406
+#define mmCB_PERFCOUNTER1_LO                                                    0xd408
+#define mmCB_PERFCOUNTER2_LO                                                    0xd40a
+#define mmCB_PERFCOUNTER3_LO                                                    0xd40c
+#define mmCB_PERFCOUNTER0_HI                                                    0xd407
+#define mmCB_PERFCOUNTER1_HI                                                    0xd409
+#define mmCB_PERFCOUNTER2_HI                                                    0xd40b
+#define mmCB_PERFCOUNTER3_HI                                                    0xd40d
+#define mmCB_CGTT_SCLK_CTRL                                                     0xf0a8
+#define mmCB_DEBUG_BUS_1                                                        0x2699
+#define mmCB_DEBUG_BUS_2                                                        0x269a
+#define mmCB_DEBUG_BUS_3                                                        0x269b
+#define mmCB_DEBUG_BUS_4                                                        0x269c
+#define mmCB_DEBUG_BUS_5                                                        0x269d
+#define mmCB_DEBUG_BUS_6                                                        0x269e
+#define mmCB_DEBUG_BUS_7                                                        0x269f
+#define mmCB_DEBUG_BUS_8                                                        0x26a0
+#define mmCB_DEBUG_BUS_9                                                        0x26a1
+#define mmCB_DEBUG_BUS_10                                                       0x26a2
+#define mmCB_DEBUG_BUS_11                                                       0x26a3
+#define mmCB_DEBUG_BUS_12                                                       0x26a4
+#define mmCB_DEBUG_BUS_13                                                       0x26a5
+#define mmCB_DEBUG_BUS_14                                                       0x26a6
+#define mmCB_DEBUG_BUS_15                                                       0x26a7
+#define mmCB_DEBUG_BUS_16                                                       0x26a8
+#define mmCB_DEBUG_BUS_17                                                       0x26a9
+#define mmCB_DEBUG_BUS_18                                                       0x26aa
+#define mmCB_DEBUG_BUS_19                                                       0x26ab
+#define mmCB_DEBUG_BUS_20                                                       0x26ac
+#define mmCB_DEBUG_BUS_21                                                       0x26ad
+#define mmCB_DEBUG_BUS_22                                                       0x26ae
+#define mmCP_DFY_CNTL                                                           0x3020
+#define mmCP_DFY_STAT                                                           0x3021
+#define mmCP_DFY_ADDR_HI                                                        0x3022
+#define mmCP_DFY_ADDR_LO                                                        0x3023
+#define mmCP_DFY_DATA_0                                                         0x3024
+#define mmCP_DFY_DATA_1                                                         0x3025
+#define mmCP_DFY_DATA_2                                                         0x3026
+#define mmCP_DFY_DATA_3                                                         0x3027
+#define mmCP_DFY_DATA_4                                                         0x3028
+#define mmCP_DFY_DATA_5                                                         0x3029
+#define mmCP_DFY_DATA_6                                                         0x302a
+#define mmCP_DFY_DATA_7                                                         0x302b
+#define mmCP_DFY_DATA_8                                                         0x302c
+#define mmCP_DFY_DATA_9                                                         0x302d
+#define mmCP_DFY_DATA_10                                                        0x302e
+#define mmCP_DFY_DATA_11                                                        0x302f
+#define mmCP_DFY_DATA_12                                                        0x3030
+#define mmCP_DFY_DATA_13                                                        0x3031
+#define mmCP_DFY_DATA_14                                                        0x3032
+#define mmCP_DFY_DATA_15                                                        0x3033
+#define mmCP_DFY_CMD                                                            0x3034
+#define mmCP_CPC_MGCG_SYNC_CNTL                                                 0x3036
+#define mmCP_RB0_BASE                                                           0x3040
+#define mmCP_RB0_BASE_HI                                                        0x30b1
+#define mmCP_RB_BASE                                                            0x3040
+#define mmCP_RB1_BASE                                                           0x3060
+#define mmCP_RB1_BASE_HI                                                        0x30b2
+#define mmCP_RB2_BASE                                                           0x3065
+#define mmCP_RB0_CNTL                                                           0x3041
+#define mmCP_RB_CNTL                                                            0x3041
+#define mmCP_RB1_CNTL                                                           0x3061
+#define mmCP_RB2_CNTL                                                           0x3066
+#define mmCP_RB_RPTR_WR                                                         0x3042
+#define mmCP_RB0_RPTR_ADDR                                                      0x3043
+#define mmCP_RB_RPTR_ADDR                                                       0x3043
+#define mmCP_RB1_RPTR_ADDR                                                      0x3062
+#define mmCP_RB2_RPTR_ADDR                                                      0x3067
+#define mmCP_RB0_RPTR_ADDR_HI                                                   0x3044
+#define mmCP_RB_RPTR_ADDR_HI                                                    0x3044
+#define mmCP_RB1_RPTR_ADDR_HI                                                   0x3063
+#define mmCP_RB2_RPTR_ADDR_HI                                                   0x3068
+#define mmCP_RB0_WPTR                                                           0x3045
+#define mmCP_RB_WPTR                                                            0x3045
+#define mmCP_RB1_WPTR                                                           0x3064
+#define mmCP_RB2_WPTR                                                           0x3069
+#define mmCP_RB_WPTR_POLL_ADDR_LO                                               0x3046
+#define mmCP_RB_WPTR_POLL_ADDR_HI                                               0x3047
+#define mmGC_PRIV_MODE                                                          0x3048
+#define mmCP_INT_CNTL                                                           0x3049
+#define mmCP_INT_CNTL_RING0                                                     0x306a
+#define mmCP_INT_CNTL_RING1                                                     0x306b
+#define mmCP_INT_CNTL_RING2                                                     0x306c
+#define mmCP_INT_STATUS                                                         0x304a
+#define mmCP_INT_STATUS_RING0                                                   0x306d
+#define mmCP_INT_STATUS_RING1                                                   0x306e
+#define mmCP_INT_STATUS_RING2                                                   0x306f
+#define mmCP_DEVICE_ID                                                          0x304b
+#define mmCP_RING_PRIORITY_CNTS                                                 0x304c
+#define mmCP_ME0_PIPE_PRIORITY_CNTS                                             0x304c
+#define mmCP_RING0_PRIORITY                                                     0x304d
+#define mmCP_ME0_PIPE0_PRIORITY                                                 0x304d
+#define mmCP_RING1_PRIORITY                                                     0x304e
+#define mmCP_ME0_PIPE1_PRIORITY                                                 0x304e
+#define mmCP_RING2_PRIORITY                                                     0x304f
+#define mmCP_ME0_PIPE2_PRIORITY                                                 0x304f
+#define mmCP_ENDIAN_SWAP                                                        0x3050
+#define mmCP_RB_VMID                                                            0x3051
+#define mmCP_ME0_PIPE0_VMID                                                     0x3052
+#define mmCP_ME0_PIPE1_VMID                                                     0x3053
+#define mmCP_RB_DOORBELL_CONTROL                                                0x3059
+#define mmCP_RB_DOORBELL_RANGE_LOWER                                            0x305a
+#define mmCP_RB_DOORBELL_RANGE_UPPER                                            0x305b
+#define mmCP_MEC_DOORBELL_RANGE_LOWER                                           0x305c
+#define mmCP_MEC_DOORBELL_RANGE_UPPER                                           0x305d
+#define mmCP_PFP_UCODE_ADDR                                                     0xf814
+#define mmCP_PFP_UCODE_DATA                                                     0xf815
+#define mmCP_ME_RAM_RADDR                                                       0xf816
+#define mmCP_ME_RAM_WADDR                                                       0xf816
+#define mmCP_ME_RAM_DATA                                                        0xf817
+#define mmCGTT_CPC_CLK_CTRL                                                     0xf0b2
+#define mmCGTT_CPF_CLK_CTRL                                                     0xf0b1
+#define mmCGTT_CP_CLK_CTRL                                                      0xf0b0
+#define mmCP_CE_UCODE_ADDR                                                      0xf818
+#define mmCP_CE_UCODE_DATA                                                      0xf819
+#define mmCP_MEC_ME1_UCODE_ADDR                                                 0xf81a
+#define mmCP_MEC_ME1_UCODE_DATA                                                 0xf81b
+#define mmCP_MEC_ME2_UCODE_ADDR                                                 0xf81c
+#define mmCP_MEC_ME2_UCODE_DATA                                                 0xf81d
+#define mmCP_MEC1_F32_INT_DIS                                                   0x30bd
+#define mmCP_MEC2_F32_INT_DIS                                                   0x30be
+#define mmCP_VIRT_STATUS                                                        0x3038
+#define mmCP_PWR_CNTL                                                           0x3078
+#define mmCP_MEM_SLP_CNTL                                                       0x3079
+#define mmCP_ECC_FIRSTOCCURRENCE                                                0x307a
+#define mmCP_ECC_FIRSTOCCURRENCE_RING0                                          0x307b
+#define mmCP_ECC_FIRSTOCCURRENCE_RING1                                          0x307c
+#define mmCP_ECC_FIRSTOCCURRENCE_RING2                                          0x307d
+#define mmCP_CPF_DEBUG                                                          0x3080
+#define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
+#define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
+#define mmCPC_INT_CNTL                                                          0x30b4
+#define mmCP_ME1_PIPE0_INT_CNTL                                                 0x3085
+#define mmCP_ME1_PIPE1_INT_CNTL                                                 0x3086
+#define mmCP_ME1_PIPE2_INT_CNTL                                                 0x3087
+#define mmCP_ME1_PIPE3_INT_CNTL                                                 0x3088
+#define mmCP_ME2_PIPE0_INT_CNTL                                                 0x3089
+#define mmCP_ME2_PIPE1_INT_CNTL                                                 0x308a
+#define mmCP_ME2_PIPE2_INT_CNTL                                                 0x308b
+#define mmCP_ME2_PIPE3_INT_CNTL                                                 0x308c
+#define mmCPC_INT_STATUS                                                        0x30b5
+#define mmCP_ME1_PIPE0_INT_STATUS                                               0x308d
+#define mmCP_ME1_PIPE1_INT_STATUS                                               0x308e
+#define mmCP_ME1_PIPE2_INT_STATUS                                               0x308f
+#define mmCP_ME1_PIPE3_INT_STATUS                                               0x3090
+#define mmCP_ME2_PIPE0_INT_STATUS                                               0x3091
+#define mmCP_ME2_PIPE1_INT_STATUS                                               0x3092
+#define mmCP_ME2_PIPE2_INT_STATUS                                               0x3093
+#define mmCP_ME2_PIPE3_INT_STATUS                                               0x3094
+#define mmCP_ME1_INT_STAT_DEBUG                                                 0x3095
+#define mmCP_ME2_INT_STAT_DEBUG                                                 0x3096
+#define mmCP_ME1_PIPE_PRIORITY_CNTS                                             0x3099
+#define mmCP_ME1_PIPE0_PRIORITY                                                 0x309a
+#define mmCP_ME1_PIPE1_PRIORITY                                                 0x309b
+#define mmCP_ME1_PIPE2_PRIORITY                                                 0x309c
+#define mmCP_ME1_PIPE3_PRIORITY                                                 0x309d
+#define mmCP_ME2_PIPE_PRIORITY_CNTS                                             0x309e
+#define mmCP_ME2_PIPE0_PRIORITY                                                 0x309f
+#define mmCP_ME2_PIPE1_PRIORITY                                                 0x30a0
+#define mmCP_ME2_PIPE2_PRIORITY                                                 0x30a1
+#define mmCP_ME2_PIPE3_PRIORITY                                                 0x30a2
+#define mmCP_CE_PRGRM_CNTR_START                                                0x30a3
+#define mmCP_PFP_PRGRM_CNTR_START                                               0x30a4
+#define mmCP_ME_PRGRM_CNTR_START                                                0x30a5
+#define mmCP_MEC1_PRGRM_CNTR_START                                              0x30a6
+#define mmCP_MEC2_PRGRM_CNTR_START                                              0x30a7
+#define mmCP_CE_INTR_ROUTINE_START                                              0x30a8
+#define mmCP_PFP_INTR_ROUTINE_START                                             0x30a9
+#define mmCP_ME_INTR_ROUTINE_START                                              0x30aa
+#define mmCP_MEC1_INTR_ROUTINE_START                                            0x30ab
+#define mmCP_MEC2_INTR_ROUTINE_START                                            0x30ac
+#define mmCP_CONTEXT_CNTL                                                       0x30ad
+#define mmCP_MAX_CONTEXT                                                        0x30ae
+#define mmCP_IQ_WAIT_TIME1                                                      0x30af
+#define mmCP_IQ_WAIT_TIME2                                                      0x30b0
+#define mmCP_VMID_RESET                                                         0x30b3
+#define mmCP_VMID_PREEMPT                                                       0x30b6
+#define mmCP_VMID_STATUS                                                        0x30bf
+#define mmCPC_INT_CNTX_ID                                                       0x30b7
+#define mmCP_PQ_STATUS                                                          0x30b8
+#define mmCP_CPC_IC_BASE_LO                                                     0x30b9
+#define mmCP_CPC_IC_BASE_HI                                                     0x30ba
+#define mmCP_CPC_IC_BASE_CNTL                                                   0x30bb
+#define mmCP_CPC_IC_OP_CNTL                                                     0x30bc
+#define mmCP_CPC_STATUS                                                         0x2084
+#define mmCP_CPC_BUSY_STAT                                                      0x2085
+#define mmCP_CPC_STALLED_STAT1                                                  0x2086
+#define mmCP_CPF_STATUS                                                         0x2087
+#define mmCP_CPF_BUSY_STAT                                                      0x2088
+#define mmCP_CPF_STALLED_STAT1                                                  0x2089
+#define mmCP_CPC_GRBM_FREE_COUNT                                                0x208b
+#define mmCP_MEC_CNTL                                                           0x208d
+#define mmCP_MEC_ME1_HEADER_DUMP                                                0x208e
+#define mmCP_MEC_ME2_HEADER_DUMP                                                0x208f
+#define mmCP_CPC_SCRATCH_INDEX                                                  0x2090
+#define mmCP_CPC_SCRATCH_DATA                                                   0x2091
+#define mmCPG_PERFCOUNTER1_SELECT                                               0xd800
+#define mmCPG_PERFCOUNTER1_LO                                                   0xd000
+#define mmCPG_PERFCOUNTER1_HI                                                   0xd001
+#define mmCPG_PERFCOUNTER0_SELECT1                                              0xd801
+#define mmCPG_PERFCOUNTER0_SELECT                                               0xd802
+#define mmCPG_PERFCOUNTER0_LO                                                   0xd002
+#define mmCPG_PERFCOUNTER0_HI                                                   0xd003
+#define mmCPC_PERFCOUNTER1_SELECT                                               0xd803
+#define mmCPC_PERFCOUNTER1_LO                                                   0xd004
+#define mmCPC_PERFCOUNTER1_HI                                                   0xd005
+#define mmCPC_PERFCOUNTER0_SELECT1                                              0xd804
+#define mmCPC_PERFCOUNTER0_SELECT                                               0xd809
+#define mmCPC_PERFCOUNTER0_LO                                                   0xd006
+#define mmCPC_PERFCOUNTER0_HI                                                   0xd007
+#define mmCPF_PERFCOUNTER1_SELECT                                               0xd805
+#define mmCPF_PERFCOUNTER1_LO                                                   0xd008
+#define mmCPF_PERFCOUNTER1_HI                                                   0xd009
+#define mmCPF_PERFCOUNTER0_SELECT1                                              0xd806
+#define mmCPF_PERFCOUNTER0_SELECT                                               0xd807
+#define mmCPF_PERFCOUNTER0_LO                                                   0xd00a
+#define mmCPF_PERFCOUNTER0_HI                                                   0xd00b
+#define mmCP_CPC_HALT_HYST_COUNT                                                0x20a7
+#define mmCP_DRAW_OBJECT                                                        0xd810
+#define mmCP_DRAW_OBJECT_COUNTER                                                0xd811
+#define mmCP_DRAW_WINDOW_MASK_HI                                                0xd812
+#define mmCP_DRAW_WINDOW_HI                                                     0xd813
+#define mmCP_DRAW_WINDOW_LO                                                     0xd814
+#define mmCP_DRAW_WINDOW_CNTL                                                   0xd815
+#define mmCP_PRT_LOD_STATS_CNTL0                                                0x20ad
+#define mmCP_PRT_LOD_STATS_CNTL1                                                0x20ae
+#define mmCP_PRT_LOD_STATS_CNTL2                                                0x20af
+#define mmCP_CE_COMPARE_COUNT                                                   0x20c0
+#define mmCP_CE_DE_COUNT                                                        0x20c1
+#define mmCP_DE_CE_COUNT                                                        0x20c2
+#define mmCP_DE_LAST_INVAL_COUNT                                                0x20c3
+#define mmCP_DE_DE_COUNT                                                        0x20c4
+#define mmCP_EOP_DONE_EVENT_CNTL                                                0xc0d5
+#define mmCP_EOP_DONE_DATA_CNTL                                                 0xc0d6
+#define mmCP_EOP_DONE_CNTX_ID                                                   0xc0d7
+#define mmCP_EOP_DONE_ADDR_LO                                                   0xc000
+#define mmCP_EOP_DONE_ADDR_HI                                                   0xc001
+#define mmCP_EOP_DONE_DATA_LO                                                   0xc002
+#define mmCP_EOP_DONE_DATA_HI                                                   0xc003
+#define mmCP_EOP_LAST_FENCE_LO                                                  0xc004
+#define mmCP_EOP_LAST_FENCE_HI                                                  0xc005
+#define mmCP_STREAM_OUT_ADDR_LO                                                 0xc006
+#define mmCP_STREAM_OUT_ADDR_HI                                                 0xc007
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                                         0xc008
+#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                                         0xc009
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO                                          0xc00a
+#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI                                          0xc00b
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                                         0xc00c
+#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                                         0xc00d
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO                                          0xc00e
+#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI                                          0xc00f
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                                         0xc010
+#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                                         0xc011
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO                                          0xc012
+#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI                                          0xc013
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                                         0xc014
+#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                                         0xc015
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO                                          0xc016
+#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI                                          0xc017
+#define mmCP_PIPE_STATS_ADDR_LO                                                 0xc018
+#define mmCP_PIPE_STATS_ADDR_HI                                                 0xc019
+#define mmCP_VGT_IAVERT_COUNT_LO                                                0xc01a
+#define mmCP_VGT_IAVERT_COUNT_HI                                                0xc01b
+#define mmCP_VGT_IAPRIM_COUNT_LO                                                0xc01c
+#define mmCP_VGT_IAPRIM_COUNT_HI                                                0xc01d
+#define mmCP_VGT_GSPRIM_COUNT_LO                                                0xc01e
+#define mmCP_VGT_GSPRIM_COUNT_HI                                                0xc01f
+#define mmCP_VGT_VSINVOC_COUNT_LO                                               0xc020
+#define mmCP_VGT_VSINVOC_COUNT_HI                                               0xc021
+#define mmCP_VGT_GSINVOC_COUNT_LO                                               0xc022
+#define mmCP_VGT_GSINVOC_COUNT_HI                                               0xc023
+#define mmCP_VGT_HSINVOC_COUNT_LO                                               0xc024
+#define mmCP_VGT_HSINVOC_COUNT_HI                                               0xc025
+#define mmCP_VGT_DSINVOC_COUNT_LO                                               0xc026
+#define mmCP_VGT_DSINVOC_COUNT_HI                                               0xc027
+#define mmCP_PA_CINVOC_COUNT_LO                                                 0xc028
+#define mmCP_PA_CINVOC_COUNT_HI                                                 0xc029
+#define mmCP_PA_CPRIM_COUNT_LO                                                  0xc02a
+#define mmCP_PA_CPRIM_COUNT_HI                                                  0xc02b
+#define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
+#define mmCP_SC_PSINVOC_COUNT0_HI                                               0xc02d
+#define mmCP_SC_PSINVOC_COUNT1_LO                                               0xc02e
+#define mmCP_SC_PSINVOC_COUNT1_HI                                               0xc02f
+#define mmCP_VGT_CSINVOC_COUNT_LO                                               0xc030
+#define mmCP_VGT_CSINVOC_COUNT_HI                                               0xc031
+#define mmCP_PIPE_STATS_CONTROL                                                 0xc03d
+#define mmCP_STREAM_OUT_CONTROL                                                 0xc03e
+#define mmCP_STRMOUT_CNTL                                                       0xc03f
+#define mmSCRATCH_REG0                                                          0xc040
+#define mmSCRATCH_REG1                                                          0xc041
+#define mmSCRATCH_REG2                                                          0xc042
+#define mmSCRATCH_REG3                                                          0xc043
+#define mmSCRATCH_REG4                                                          0xc044
+#define mmSCRATCH_REG5                                                          0xc045
+#define mmSCRATCH_REG6                                                          0xc046
+#define mmSCRATCH_REG7                                                          0xc047
+#define mmSCRATCH_UMSK                                                          0xc050
+#define mmSCRATCH_ADDR                                                          0xc051
+#define mmCP_PFP_ATOMIC_PREOP_LO                                                0xc052
+#define mmCP_PFP_ATOMIC_PREOP_HI                                                0xc053
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO                                           0xc054
+#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI                                           0xc055
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO                                           0xc056
+#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI                                           0xc057
+#define mmCP_APPEND_ADDR_LO                                                     0xc058
+#define mmCP_APPEND_ADDR_HI                                                     0xc059
+#define mmCP_APPEND_DATA                                                        0xc05a
+#define mmCP_APPEND_LAST_CS_FENCE                                               0xc05b
+#define mmCP_APPEND_LAST_PS_FENCE                                               0xc05c
+#define mmCP_ATOMIC_PREOP_LO                                                    0xc05d
+#define mmCP_ME_ATOMIC_PREOP_LO                                                 0xc05d
+#define mmCP_ATOMIC_PREOP_HI                                                    0xc05e
+#define mmCP_ME_ATOMIC_PREOP_HI                                                 0xc05e
+#define mmCP_GDS_ATOMIC0_PREOP_LO                                               0xc05f
+#define mmCP_ME_GDS_ATOMIC0_PREOP_LO                                            0xc05f
+#define mmCP_GDS_ATOMIC0_PREOP_HI                                               0xc060
+#define mmCP_ME_GDS_ATOMIC0_PREOP_HI                                            0xc060
+#define mmCP_GDS_ATOMIC1_PREOP_LO                                               0xc061
+#define mmCP_ME_GDS_ATOMIC1_PREOP_LO                                            0xc061
+#define mmCP_GDS_ATOMIC1_PREOP_HI                                               0xc062
+#define mmCP_ME_GDS_ATOMIC1_PREOP_HI                                            0xc062
+#define mmCP_ME_MC_WADDR_LO                                                     0xc069
+#define mmCP_ME_MC_WADDR_HI                                                     0xc06a
+#define mmCP_ME_MC_WDATA_LO                                                     0xc06b
+#define mmCP_ME_MC_WDATA_HI                                                     0xc06c
+#define mmCP_ME_MC_RADDR_LO                                                     0xc06d
+#define mmCP_ME_MC_RADDR_HI                                                     0xc06e
+#define mmCP_SEM_WAIT_TIMER                                                     0xc06f
+#define mmCP_SIG_SEM_ADDR_LO                                                    0xc070
+#define mmCP_SIG_SEM_ADDR_HI                                                    0xc071
+#define mmCP_WAIT_SEM_ADDR_LO                                                   0xc075
+#define mmCP_WAIT_SEM_ADDR_HI                                                   0xc076
+#define mmCP_WAIT_REG_MEM_TIMEOUT                                               0xc074
+#define mmCP_COHER_START_DELAY                                                  0xc07b
+#define mmCP_COHER_CNTL                                                         0xc07c
+#define mmCP_COHER_SIZE                                                         0xc07d
+#define mmCP_COHER_SIZE_HI                                                      0xc08c
+#define mmCP_COHER_BASE                                                         0xc07e
+#define mmCP_COHER_BASE_HI                                                      0xc079
+#define mmCP_COHER_STATUS                                                       0xc07f
+#define mmCOHER_DEST_BASE_0                                                     0xa092
+#define mmCOHER_DEST_BASE_1                                                     0xa093
+#define mmCOHER_DEST_BASE_2                                                     0xa07e
+#define mmCOHER_DEST_BASE_3                                                     0xa07f
+#define mmCOHER_DEST_BASE_HI_0                                                  0xa07a
+#define mmCOHER_DEST_BASE_HI_1                                                  0xa07b
+#define mmCOHER_DEST_BASE_HI_2                                                  0xa07c
+#define mmCOHER_DEST_BASE_HI_3                                                  0xa07d
+#define mmCP_DMA_ME_SRC_ADDR                                                    0xc080
+#define mmCP_DMA_ME_SRC_ADDR_HI                                                 0xc081
+#define mmCP_DMA_ME_DST_ADDR                                                    0xc082
+#define mmCP_DMA_ME_DST_ADDR_HI                                                 0xc083
+#define mmCP_DMA_ME_CONTROL                                                     0xc078
+#define mmCP_DMA_ME_COMMAND                                                     0xc084
+#define mmCP_DMA_PFP_SRC_ADDR                                                   0xc085
+#define mmCP_DMA_PFP_SRC_ADDR_HI                                                0xc086
+#define mmCP_DMA_PFP_DST_ADDR                                                   0xc087
+#define mmCP_DMA_PFP_DST_ADDR_HI                                                0xc088
+#define mmCP_DMA_PFP_CONTROL                                                    0xc077
+#define mmCP_DMA_PFP_COMMAND                                                    0xc089
+#define mmCP_DMA_CNTL                                                           0xc08a
+#define mmCP_DMA_READ_TAGS                                                      0xc08b
+#define mmCP_PFP_IB_CONTROL                                                     0xc08d
+#define mmCP_PFP_LOAD_CONTROL                                                   0xc08e
+#define mmCP_SCRATCH_INDEX                                                      0xc08f
+#define mmCP_SCRATCH_DATA                                                       0xc090
+#define mmCP_RB_OFFSET                                                          0xc091
+#define mmCP_IB1_OFFSET                                                         0xc092
+#define mmCP_IB2_OFFSET                                                         0xc093
+#define mmCP_IB1_PREAMBLE_BEGIN                                                 0xc094
+#define mmCP_IB1_PREAMBLE_END                                                   0xc095
+#define mmCP_IB2_PREAMBLE_BEGIN                                                 0xc096
+#define mmCP_IB2_PREAMBLE_END                                                   0xc097
+#define mmCP_CE_IB1_OFFSET                                                      0xc098
+#define mmCP_CE_IB2_OFFSET                                                      0xc099
+#define mmCP_CE_COUNTER                                                         0xc09a
+#define mmCP_CE_RB_OFFSET                                                       0xc09b
+#define mmCP_PFP_COMPLETION_STATUS                                              0xc0ec
+#define mmCP_CE_COMPLETION_STATUS                                               0xc0ed
+#define mmCP_PRED_NOT_VISIBLE                                                   0xc0ee
+#define mmCP_PFP_METADATA_BASE_ADDR                                             0xc0f0
+#define mmCP_PFP_METADATA_BASE_ADDR_HI                                          0xc0f1
+#define mmCP_CE_METADATA_BASE_ADDR                                              0xc0f2
+#define mmCP_CE_METADATA_BASE_ADDR_HI                                           0xc0f3
+#define mmCP_DRAW_INDX_INDR_ADDR                                                0xc0f4
+#define mmCP_DRAW_INDX_INDR_ADDR_HI                                             0xc0f5
+#define mmCP_DISPATCH_INDR_ADDR                                                 0xc0f6
+#define mmCP_DISPATCH_INDR_ADDR_HI                                              0xc0f7
+#define mmCP_INDEX_BASE_ADDR                                                    0xc0f8
+#define mmCP_INDEX_BASE_ADDR_HI                                                 0xc0f9
+#define mmCP_INDEX_TYPE                                                         0xc0fa
+#define mmCP_GDS_BKUP_ADDR                                                      0xc0fb
+#define mmCP_GDS_BKUP_ADDR_HI                                                   0xc0fc
+#define mmCP_SAMPLE_STATUS                                                      0xc0fd
+#define mmCP_STALLED_STAT1                                                      0x219d
+#define mmCP_STALLED_STAT2                                                      0x219e
+#define mmCP_STALLED_STAT3                                                      0x219c
+#define mmCP_BUSY_STAT                                                          0x219f
+#define mmCP_STAT                                                               0x21a0
+#define mmCP_ME_HEADER_DUMP                                                     0x21a1
+#define mmCP_PFP_HEADER_DUMP                                                    0x21a2
+#define mmCP_GRBM_FREE_COUNT                                                    0x21a3
+#define mmCP_CE_HEADER_DUMP                                                     0x21a4
+#define mmCP_CSF_STAT                                                           0x21b4
+#define mmCP_CSF_CNTL                                                           0x21b5
+#define mmCP_ME_CNTL                                                            0x21b6
+#define mmCP_CNTX_STAT                                                          0x21b8
+#define mmCP_ME_PREEMPTION                                                      0x21b9
+#define mmCP_RB0_RPTR                                                           0x21c0
+#define mmCP_RB_RPTR                                                            0x21c0
+#define mmCP_RB1_RPTR                                                           0x21bf
+#define mmCP_RB2_RPTR                                                           0x21be
+#define mmCP_RB_WPTR_DELAY                                                      0x21c1
+#define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
+#define mmCP_CE_INIT_BASE_LO                                                    0xc0c3
+#define mmCP_CE_INIT_BASE_HI                                                    0xc0c4
+#define mmCP_CE_INIT_BUFSZ                                                      0xc0c5
+#define mmCP_CE_IB1_BASE_LO                                                     0xc0c6
+#define mmCP_CE_IB1_BASE_HI                                                     0xc0c7
+#define mmCP_CE_IB1_BUFSZ                                                       0xc0c8
+#define mmCP_CE_IB2_BASE_LO                                                     0xc0c9
+#define mmCP_CE_IB2_BASE_HI                                                     0xc0ca
+#define mmCP_CE_IB2_BUFSZ                                                       0xc0cb
+#define mmCP_IB1_BASE_LO                                                        0xc0cc
+#define mmCP_IB1_BASE_HI                                                        0xc0cd
+#define mmCP_IB1_BUFSZ                                                          0xc0ce
+#define mmCP_IB2_BASE_LO                                                        0xc0cf
+#define mmCP_IB2_BASE_HI                                                        0xc0d0
+#define mmCP_IB2_BUFSZ                                                          0xc0d1
+#define mmCP_ST_BASE_LO                                                         0xc0d2
+#define mmCP_ST_BASE_HI                                                         0xc0d3
+#define mmCP_ST_BUFSZ                                                           0xc0d4
+#define mmCP_ROQ_THRESHOLDS                                                     0x21bc
+#define mmCP_MEQ_STQ_THRESHOLD                                                  0x21bd
+#define mmCP_ROQ1_THRESHOLDS                                                    0x21d5
+#define mmCP_ROQ2_THRESHOLDS                                                    0x21d6
+#define mmCP_STQ_THRESHOLDS                                                     0x21d7
+#define mmCP_QUEUE_THRESHOLDS                                                   0x21d8
+#define mmCP_MEQ_THRESHOLDS                                                     0x21d9
+#define mmCP_ROQ_AVAIL                                                          0x21da
+#define mmCP_STQ_AVAIL                                                          0x21db
+#define mmCP_ROQ2_AVAIL                                                         0x21dc
+#define mmCP_MEQ_AVAIL                                                          0x21dd
+#define mmCP_CMD_INDEX                                                          0x21de
+#define mmCP_CMD_DATA                                                           0x21df
+#define mmCP_ROQ_RB_STAT                                                        0x21e0
+#define mmCP_ROQ_IB1_STAT                                                       0x21e1
+#define mmCP_ROQ_IB2_STAT                                                       0x21e2
+#define mmCP_STQ_STAT                                                           0x21e3
+#define mmCP_STQ_WR_STAT                                                        0x21e4
+#define mmCP_MEQ_STAT                                                           0x21e5
+#define mmCP_CEQ1_AVAIL                                                         0x21e6
+#define mmCP_CEQ2_AVAIL                                                         0x21e7
+#define mmCP_CE_ROQ_RB_STAT                                                     0x21e8
+#define mmCP_CE_ROQ_IB1_STAT                                                    0x21e9
+#define mmCP_CE_ROQ_IB2_STAT                                                    0x21ea
+#define mmCP_INT_STAT_DEBUG                                                     0x21f7
+#define mmCP_PERFMON_CNTL                                                       0xd808
+#define mmCP_PERFMON_CNTX_CNTL                                                  0xa0d8
+#define mmCP_RINGID                                                             0xa0d9
+#define mmCP_PIPEID                                                             0xa0d9
+#define mmCP_VMID                                                               0xa0da
+#define mmCP_HPD_ROQ_OFFSETS                                                    0x3240
+#define mmCP_HPD_STATUS0                                                        0x3241
+#define mmCP_MQD_BASE_ADDR                                                      0x3245
+#define mmCP_MQD_BASE_ADDR_HI                                                   0x3246
+#define mmCP_HQD_ACTIVE                                                         0x3247
+#define mmCP_HQD_VMID                                                           0x3248
+#define mmCP_HQD_PERSISTENT_STATE                                               0x3249
+#define mmCP_HQD_PIPE_PRIORITY                                                  0x324a
+#define mmCP_HQD_QUEUE_PRIORITY                                                 0x324b
+#define mmCP_HQD_QUANTUM                                                        0x324c
+#define mmCP_HQD_PQ_BASE                                                        0x324d
+#define mmCP_HQD_PQ_BASE_HI                                                     0x324e
+#define mmCP_HQD_PQ_RPTR                                                        0x324f
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
+#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR                                              0x3252
+#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                                           0x3253
+#define mmCP_HQD_PQ_DOORBELL_CONTROL                                            0x3254
+#define mmCP_HQD_PQ_WPTR                                                        0x3255
+#define mmCP_HQD_PQ_CONTROL                                                     0x3256
+#define mmCP_HQD_IB_BASE_ADDR                                                   0x3257
+#define mmCP_HQD_IB_BASE_ADDR_HI                                                0x3258
+#define mmCP_HQD_IB_RPTR                                                        0x3259
+#define mmCP_HQD_IB_CONTROL                                                     0x325a
+#define mmCP_HQD_IQ_TIMER                                                       0x325b
+#define mmCP_HQD_IQ_RPTR                                                        0x325c
+#define mmCP_HQD_DEQUEUE_REQUEST                                                0x325d
+#define mmCP_HQD_DMA_OFFLOAD                                                    0x325e
+#define mmCP_HQD_OFFLOAD                                                        0x325e
+#define mmCP_HQD_SEMA_CMD                                                       0x325f
+#define mmCP_HQD_MSG_TYPE                                                       0x3260
+#define mmCP_HQD_ATOMIC0_PREOP_LO                                               0x3261
+#define mmCP_HQD_ATOMIC0_PREOP_HI                                               0x3262
+#define mmCP_HQD_ATOMIC1_PREOP_LO                                               0x3263
+#define mmCP_HQD_ATOMIC1_PREOP_HI                                               0x3264
+#define mmCP_HQD_HQ_SCHEDULER0                                                  0x3265
+#define mmCP_HQD_HQ_STATUS0                                                     0x3265
+#define mmCP_HQD_HQ_SCHEDULER1                                                  0x3266
+#define mmCP_HQD_HQ_CONTROL0                                                    0x3266
+#define mmCP_MQD_CONTROL                                                        0x3267
+#define mmCP_HQD_HQ_STATUS1                                                     0x3268
+#define mmCP_HQD_HQ_CONTROL1                                                    0x3269
+#define mmCP_HQD_EOP_BASE_ADDR                                                  0x326a
+#define mmCP_HQD_EOP_BASE_ADDR_HI                                               0x326b
+#define mmCP_HQD_EOP_CONTROL                                                    0x326c
+#define mmCP_HQD_EOP_RPTR                                                       0x326d
+#define mmCP_HQD_EOP_WPTR                                                       0x326e
+#define mmCP_HQD_EOP_EVENTS                                                     0x326f
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO                                          0x3270
+#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI                                          0x3271
+#define mmCP_HQD_CTX_SAVE_CONTROL                                               0x3272
+#define mmCP_HQD_CNTL_STACK_OFFSET                                              0x3273
+#define mmCP_HQD_CNTL_STACK_SIZE                                                0x3274
+#define mmCP_HQD_WG_STATE_OFFSET                                                0x3275
+#define mmCP_HQD_CTX_SAVE_SIZE                                                  0x3276
+#define mmCP_HQD_GDS_RESOURCE_STATE                                             0x3277
+#define mmCP_HQD_ERROR                                                          0x3278
+#define mmCP_HQD_EOP_WPTR_MEM                                                   0x3279
+#define mmCP_HQD_EOP_DONES                                                      0x327a
+#define mmDB_Z_READ_BASE                                                        0xa012
+#define mmDB_STENCIL_READ_BASE                                                  0xa013
+#define mmDB_Z_WRITE_BASE                                                       0xa014
+#define mmDB_STENCIL_WRITE_BASE                                                 0xa015
+#define mmDB_DEPTH_INFO                                                         0xa00f
+#define mmDB_Z_INFO                                                             0xa010
+#define mmDB_STENCIL_INFO                                                       0xa011
+#define mmDB_DEPTH_SIZE                                                         0xa016
+#define mmDB_DEPTH_SLICE                                                        0xa017
+#define mmDB_DEPTH_VIEW                                                         0xa002
+#define mmDB_RENDER_CONTROL                                                     0xa000
+#define mmDB_COUNT_CONTROL                                                      0xa001
+#define mmDB_RENDER_OVERRIDE                                                    0xa003
+#define mmDB_RENDER_OVERRIDE2                                                   0xa004
+#define mmDB_EQAA                                                               0xa201
+#define mmDB_SHADER_CONTROL                                                     0xa203
+#define mmDB_DEPTH_BOUNDS_MIN                                                   0xa008
+#define mmDB_DEPTH_BOUNDS_MAX                                                   0xa009
+#define mmDB_STENCIL_CLEAR                                                      0xa00a
+#define mmDB_DEPTH_CLEAR                                                        0xa00b
+#define mmDB_HTILE_DATA_BASE                                                    0xa005
+#define mmDB_HTILE_SURFACE                                                      0xa2af
+#define mmDB_PRELOAD_CONTROL                                                    0xa2b2
+#define mmDB_STENCILREFMASK                                                     0xa10c
+#define mmDB_STENCILREFMASK_BF                                                  0xa10d
+#define mmDB_SRESULTS_COMPARE_STATE0                                            0xa2b0
+#define mmDB_SRESULTS_COMPARE_STATE1                                            0xa2b1
+#define mmDB_DEPTH_CONTROL                                                      0xa200
+#define mmDB_STENCIL_CONTROL                                                    0xa10b
+#define mmDB_ALPHA_TO_MASK                                                      0xa2dc
+#define mmDB_PERFCOUNTER0_SELECT                                                0xdc40
+#define mmDB_PERFCOUNTER1_SELECT                                                0xdc42
+#define mmDB_PERFCOUNTER2_SELECT                                                0xdc44
+#define mmDB_PERFCOUNTER3_SELECT                                                0xdc46
+#define mmDB_PERFCOUNTER0_SELECT1                                               0xdc41
+#define mmDB_PERFCOUNTER1_SELECT1                                               0xdc43
+#define mmDB_PERFCOUNTER0_LO                                                    0xd440
+#define mmDB_PERFCOUNTER1_LO                                                    0xd442
+#define mmDB_PERFCOUNTER2_LO                                                    0xd444
+#define mmDB_PERFCOUNTER3_LO                                                    0xd446
+#define mmDB_PERFCOUNTER0_HI                                                    0xd441
+#define mmDB_PERFCOUNTER1_HI                                                    0xd443
+#define mmDB_PERFCOUNTER2_HI                                                    0xd445
+#define mmDB_PERFCOUNTER3_HI                                                    0xd447
+#define mmDB_DEBUG                                                              0x260c
+#define mmDB_DEBUG2                                                             0x260d
+#define mmDB_DEBUG3                                                             0x260e
+#define mmDB_DEBUG4                                                             0x260f
+#define mmDB_CREDIT_LIMIT                                                       0x2614
+#define mmDB_WATERMARKS                                                         0x2615
+#define mmDB_SUBTILE_CONTROL                                                    0x2616
+#define mmDB_FREE_CACHELINES                                                    0x2617
+#define mmDB_FIFO_DEPTH1                                                        0x2618
+#define mmDB_FIFO_DEPTH2                                                        0x2619
+#define mmDB_CGTT_CLK_CTRL_0                                                    0xf0a4
+#define mmDB_ZPASS_COUNT_LOW                                                    0xc3fe
+#define mmDB_ZPASS_COUNT_HI                                                     0xc3ff
+#define mmDB_RING_CONTROL                                                       0x261b
+#define mmDB_READ_DEBUG_0                                                       0x2620
+#define mmDB_READ_DEBUG_1                                                       0x2621
+#define mmDB_READ_DEBUG_2                                                       0x2622
+#define mmDB_READ_DEBUG_3                                                       0x2623
+#define mmDB_READ_DEBUG_4                                                       0x2624
+#define mmDB_READ_DEBUG_5                                                       0x2625
+#define mmDB_READ_DEBUG_6                                                       0x2626
+#define mmDB_READ_DEBUG_7                                                       0x2627
+#define mmDB_READ_DEBUG_8                                                       0x2628
+#define mmDB_READ_DEBUG_9                                                       0x2629
+#define mmDB_READ_DEBUG_A                                                       0x262a
+#define mmDB_READ_DEBUG_B                                                       0x262b
+#define mmDB_READ_DEBUG_C                                                       0x262c
+#define mmDB_READ_DEBUG_D                                                       0x262d
+#define mmDB_READ_DEBUG_E                                                       0x262e
+#define mmDB_READ_DEBUG_F                                                       0x262f
+#define mmDB_OCCLUSION_COUNT0_LOW                                               0xc3c0
+#define mmDB_OCCLUSION_COUNT0_HI                                                0xc3c1
+#define mmDB_OCCLUSION_COUNT1_LOW                                               0xc3c2
+#define mmDB_OCCLUSION_COUNT1_HI                                                0xc3c3
+#define mmDB_OCCLUSION_COUNT2_LOW                                               0xc3c4
+#define mmDB_OCCLUSION_COUNT2_HI                                                0xc3c5
+#define mmDB_OCCLUSION_COUNT3_LOW                                               0xc3c6
+#define mmDB_OCCLUSION_COUNT3_HI                                                0xc3c7
+#define mmCC_RB_REDUNDANCY                                                      0x263c
+#define mmCC_RB_BACKEND_DISABLE                                                 0x263d
+#define mmGC_USER_RB_REDUNDANCY                                                 0x26de
+#define mmGC_USER_RB_BACKEND_DISABLE                                            0x26df
+#define mmGB_ADDR_CONFIG                                                        0x263e
+#define mmGB_BACKEND_MAP                                                        0x263f
+#define mmGB_GPU_ID                                                             0x2640
+#define mmCC_RB_DAISY_CHAIN                                                     0x2641
+#define mmGB_TILE_MODE0                                                         0x2644
+#define mmGB_TILE_MODE1                                                         0x2645
+#define mmGB_TILE_MODE2                                                         0x2646
+#define mmGB_TILE_MODE3                                                         0x2647
+#define mmGB_TILE_MODE4                                                         0x2648
+#define mmGB_TILE_MODE5                                                         0x2649
+#define mmGB_TILE_MODE6                                                         0x264a
+#define mmGB_TILE_MODE7                                                         0x264b
+#define mmGB_TILE_MODE8                                                         0x264c
+#define mmGB_TILE_MODE9                                                         0x264d
+#define mmGB_TILE_MODE10                                                        0x264e
+#define mmGB_TILE_MODE11                                                        0x264f
+#define mmGB_TILE_MODE12                                                        0x2650
+#define mmGB_TILE_MODE13                                                        0x2651
+#define mmGB_TILE_MODE14                                                        0x2652
+#define mmGB_TILE_MODE15                                                        0x2653
+#define mmGB_TILE_MODE16                                                        0x2654
+#define mmGB_TILE_MODE17                                                        0x2655
+#define mmGB_TILE_MODE18                                                        0x2656
+#define mmGB_TILE_MODE19                                                        0x2657
+#define mmGB_TILE_MODE20                                                        0x2658
+#define mmGB_TILE_MODE21                                                        0x2659
+#define mmGB_TILE_MODE22                                                        0x265a
+#define mmGB_TILE_MODE23                                                        0x265b
+#define mmGB_TILE_MODE24                                                        0x265c
+#define mmGB_TILE_MODE25                                                        0x265d
+#define mmGB_TILE_MODE26                                                        0x265e
+#define mmGB_TILE_MODE27                                                        0x265f
+#define mmGB_TILE_MODE28                                                        0x2660
+#define mmGB_TILE_MODE29                                                        0x2661
+#define mmGB_TILE_MODE30                                                        0x2662
+#define mmGB_TILE_MODE31                                                        0x2663
+#define mmGB_MACROTILE_MODE0                                                    0x2664
+#define mmGB_MACROTILE_MODE1                                                    0x2665
+#define mmGB_MACROTILE_MODE2                                                    0x2666
+#define mmGB_MACROTILE_MODE3                                                    0x2667
+#define mmGB_MACROTILE_MODE4                                                    0x2668
+#define mmGB_MACROTILE_MODE5                                                    0x2669
+#define mmGB_MACROTILE_MODE6                                                    0x266a
+#define mmGB_MACROTILE_MODE7                                                    0x266b
+#define mmGB_MACROTILE_MODE8                                                    0x266c
+#define mmGB_MACROTILE_MODE9                                                    0x266d
+#define mmGB_MACROTILE_MODE10                                                   0x266e
+#define mmGB_MACROTILE_MODE11                                                   0x266f
+#define mmGB_MACROTILE_MODE12                                                   0x2670
+#define mmGB_MACROTILE_MODE13                                                   0x2671
+#define mmGB_MACROTILE_MODE14                                                   0x2672
+#define mmGB_MACROTILE_MODE15                                                   0x2673
+#define mmGB_EDC_MODE                                                           0x307e
+#define mmCC_GC_EDC_CONFIG                                                      0x3098
+#define mmRAS_SIGNATURE_CONTROL                                                 0x3380
+#define mmRAS_SIGNATURE_MASK                                                    0x3381
+#define mmRAS_SX_SIGNATURE0                                                     0x3382
+#define mmRAS_SX_SIGNATURE1                                                     0x3383
+#define mmRAS_SX_SIGNATURE2                                                     0x3384
+#define mmRAS_SX_SIGNATURE3                                                     0x3385
+#define mmRAS_DB_SIGNATURE0                                                     0x338b
+#define mmRAS_PA_SIGNATURE0                                                     0x338c
+#define mmRAS_VGT_SIGNATURE0                                                    0x338d
+#define mmRAS_SQ_SIGNATURE0                                                     0x338e
+#define mmRAS_SC_SIGNATURE0                                                     0x338f
+#define mmRAS_SC_SIGNATURE1                                                     0x3390
+#define mmRAS_SC_SIGNATURE2                                                     0x3391
+#define mmRAS_SC_SIGNATURE3                                                     0x3392
+#define mmRAS_SC_SIGNATURE4                                                     0x3393
+#define mmRAS_SC_SIGNATURE5                                                     0x3394
+#define mmRAS_SC_SIGNATURE6                                                     0x3395
+#define mmRAS_SC_SIGNATURE7                                                     0x3396
+#define mmRAS_IA_SIGNATURE0                                                     0x3397
+#define mmRAS_IA_SIGNATURE1                                                     0x3398
+#define mmRAS_SPI_SIGNATURE0                                                    0x3399
+#define mmRAS_SPI_SIGNATURE1                                                    0x339a
+#define mmRAS_TA_SIGNATURE0                                                     0x339b
+#define mmRAS_TD_SIGNATURE0                                                     0x339c
+#define mmRAS_CB_SIGNATURE0                                                     0x339d
+#define mmRAS_BCI_SIGNATURE0                                                    0x339e
+#define mmRAS_BCI_SIGNATURE1                                                    0x339f
+#define mmRAS_TA_SIGNATURE1                                                     0x33a0
+#define mmGRBM_HYP_CAM_INDEX                                                    0xf83e
+#define mmGRBM_CAM_INDEX                                                        0xf83e
+#define mmGRBM_HYP_CAM_DATA                                                     0xf83f
+#define mmGRBM_CAM_DATA                                                         0xf83f
+#define mmGRBM_CNTL                                                             0x2000
+#define mmGRBM_SKEW_CNTL                                                        0x2001
+#define mmGRBM_PWR_CNTL                                                         0x2003
+#define mmGRBM_STATUS                                                           0x2004
+#define mmGRBM_STATUS2                                                          0x2002
+#define mmGRBM_STATUS_SE0                                                       0x2005
+#define mmGRBM_STATUS_SE1                                                       0x2006
+#define mmGRBM_STATUS_SE2                                                       0x200e
+#define mmGRBM_STATUS_SE3                                                       0x200f
+#define mmGRBM_SOFT_RESET                                                       0x2008
+#define mmGRBM_DEBUG_CNTL                                                       0x2009
+#define mmGRBM_DEBUG_DATA                                                       0x200a
+#define mmGRBM_GFX_INDEX                                                        0xc200
+#define mmGRBM_GFX_CLKEN_CNTL                                                   0x200c
+#define mmGRBM_WAIT_IDLE_CLOCKS                                                 0x200d
+#define mmGRBM_DEBUG                                                            0x2014
+#define mmGRBM_DEBUG_SNAPSHOT                                                   0x2015
+#define mmGRBM_READ_ERROR                                                       0x2016
+#define mmGRBM_READ_ERROR2                                                      0x2017
+#define mmGRBM_INT_CNTL                                                         0x2018
+#define mmGRBM_TRAP_OP                                                          0x2019
+#define mmGRBM_TRAP_ADDR                                                        0x201a
+#define mmGRBM_TRAP_ADDR_MSK                                                    0x201b
+#define mmGRBM_TRAP_WD                                                          0x201c
+#define mmGRBM_TRAP_WD_MSK                                                      0x201d
+#define mmGRBM_DSM_BYPASS                                                       0x201e
+#define mmGRBM_WRITE_ERROR                                                      0x201f
+#define mmGRBM_PERFCOUNTER0_SELECT                                              0xd840
+#define mmGRBM_PERFCOUNTER1_SELECT                                              0xd841
+#define mmGRBM_SE0_PERFCOUNTER_SELECT                                           0xd842
+#define mmGRBM_SE1_PERFCOUNTER_SELECT                                           0xd843
+#define mmGRBM_SE2_PERFCOUNTER_SELECT                                           0xd844
+#define mmGRBM_SE3_PERFCOUNTER_SELECT                                           0xd845
+#define mmGRBM_PERFCOUNTER0_LO                                                  0xd040
+#define mmGRBM_PERFCOUNTER0_HI                                                  0xd041
+#define mmGRBM_PERFCOUNTER1_LO                                                  0xd043
+#define mmGRBM_PERFCOUNTER1_HI                                                  0xd044
+#define mmGRBM_SE0_PERFCOUNTER_LO                                               0xd045
+#define mmGRBM_SE0_PERFCOUNTER_HI                                               0xd046
+#define mmGRBM_SE1_PERFCOUNTER_LO                                               0xd047
+#define mmGRBM_SE1_PERFCOUNTER_HI                                               0xd048
+#define mmGRBM_SE2_PERFCOUNTER_LO                                               0xd049
+#define mmGRBM_SE2_PERFCOUNTER_HI                                               0xd04a
+#define mmGRBM_SE3_PERFCOUNTER_LO                                               0xd04b
+#define mmGRBM_SE3_PERFCOUNTER_HI                                               0xd04c
+#define mmGRBM_SCRATCH_REG0                                                     0x2040
+#define mmGRBM_SCRATCH_REG1                                                     0x2041
+#define mmGRBM_SCRATCH_REG2                                                     0x2042
+#define mmGRBM_SCRATCH_REG3                                                     0x2043
+#define mmGRBM_SCRATCH_REG4                                                     0x2044
+#define mmGRBM_SCRATCH_REG5                                                     0x2045
+#define mmGRBM_SCRATCH_REG6                                                     0x2046
+#define mmGRBM_SCRATCH_REG7                                                     0x2047
+#define mmDEBUG_INDEX                                                           0x203c
+#define mmDEBUG_DATA                                                            0x203d
+#define mmGRBM_NOWHERE                                                          0x203f
+#define mmPA_CL_VPORT_XSCALE                                                    0xa10f
+#define mmPA_CL_VPORT_XOFFSET                                                   0xa110
+#define mmPA_CL_VPORT_YSCALE                                                    0xa111
+#define mmPA_CL_VPORT_YOFFSET                                                   0xa112
+#define mmPA_CL_VPORT_ZSCALE                                                    0xa113
+#define mmPA_CL_VPORT_ZOFFSET                                                   0xa114
+#define mmPA_CL_VPORT_XSCALE_1                                                  0xa115
+#define mmPA_CL_VPORT_XSCALE_2                                                  0xa11b
+#define mmPA_CL_VPORT_XSCALE_3                                                  0xa121
+#define mmPA_CL_VPORT_XSCALE_4                                                  0xa127
+#define mmPA_CL_VPORT_XSCALE_5                                                  0xa12d
+#define mmPA_CL_VPORT_XSCALE_6                                                  0xa133
+#define mmPA_CL_VPORT_XSCALE_7                                                  0xa139
+#define mmPA_CL_VPORT_XSCALE_8                                                  0xa13f
+#define mmPA_CL_VPORT_XSCALE_9                                                  0xa145
+#define mmPA_CL_VPORT_XSCALE_10                                                 0xa14b
+#define mmPA_CL_VPORT_XSCALE_11                                                 0xa151
+#define mmPA_CL_VPORT_XSCALE_12                                                 0xa157
+#define mmPA_CL_VPORT_XSCALE_13                                                 0xa15d
+#define mmPA_CL_VPORT_XSCALE_14                                                 0xa163
+#define mmPA_CL_VPORT_XSCALE_15                                                 0xa169
+#define mmPA_CL_VPORT_XOFFSET_1                                                 0xa116
+#define mmPA_CL_VPORT_XOFFSET_2                                                 0xa11c
+#define mmPA_CL_VPORT_XOFFSET_3                                                 0xa122
+#define mmPA_CL_VPORT_XOFFSET_4                                                 0xa128
+#define mmPA_CL_VPORT_XOFFSET_5                                                 0xa12e
+#define mmPA_CL_VPORT_XOFFSET_6                                                 0xa134
+#define mmPA_CL_VPORT_XOFFSET_7                                                 0xa13a
+#define mmPA_CL_VPORT_XOFFSET_8                                                 0xa140
+#define mmPA_CL_VPORT_XOFFSET_9                                                 0xa146
+#define mmPA_CL_VPORT_XOFFSET_10                                                0xa14c
+#define mmPA_CL_VPORT_XOFFSET_11                                                0xa152
+#define mmPA_CL_VPORT_XOFFSET_12                                                0xa158
+#define mmPA_CL_VPORT_XOFFSET_13                                                0xa15e
+#define mmPA_CL_VPORT_XOFFSET_14                                                0xa164
+#define mmPA_CL_VPORT_XOFFSET_15                                                0xa16a
+#define mmPA_CL_VPORT_YSCALE_1                                                  0xa117
+#define mmPA_CL_VPORT_YSCALE_2                                                  0xa11d
+#define mmPA_CL_VPORT_YSCALE_3                                                  0xa123
+#define mmPA_CL_VPORT_YSCALE_4                                                  0xa129
+#define mmPA_CL_VPORT_YSCALE_5                                                  0xa12f
+#define mmPA_CL_VPORT_YSCALE_6                                                  0xa135
+#define mmPA_CL_VPORT_YSCALE_7                                                  0xa13b
+#define mmPA_CL_VPORT_YSCALE_8                                                  0xa141
+#define mmPA_CL_VPORT_YSCALE_9                                                  0xa147
+#define mmPA_CL_VPORT_YSCALE_10                                                 0xa14d
+#define mmPA_CL_VPORT_YSCALE_11                                                 0xa153
+#define mmPA_CL_VPORT_YSCALE_12                                                 0xa159
+#define mmPA_CL_VPORT_YSCALE_13                                                 0xa15f
+#define mmPA_CL_VPORT_YSCALE_14                                                 0xa165
+#define mmPA_CL_VPORT_YSCALE_15                                                 0xa16b
+#define mmPA_CL_VPORT_YOFFSET_1                                                 0xa118
+#define mmPA_CL_VPORT_YOFFSET_2                                                 0xa11e
+#define mmPA_CL_VPORT_YOFFSET_3                                                 0xa124
+#define mmPA_CL_VPORT_YOFFSET_4                                                 0xa12a
+#define mmPA_CL_VPORT_YOFFSET_5                                                 0xa130
+#define mmPA_CL_VPORT_YOFFSET_6                                                 0xa136
+#define mmPA_CL_VPORT_YOFFSET_7                                                 0xa13c
+#define mmPA_CL_VPORT_YOFFSET_8                                                 0xa142
+#define mmPA_CL_VPORT_YOFFSET_9                                                 0xa148
+#define mmPA_CL_VPORT_YOFFSET_10                                                0xa14e
+#define mmPA_CL_VPORT_YOFFSET_11                                                0xa154
+#define mmPA_CL_VPORT_YOFFSET_12                                                0xa15a
+#define mmPA_CL_VPORT_YOFFSET_13                                                0xa160
+#define mmPA_CL_VPORT_YOFFSET_14                                                0xa166
+#define mmPA_CL_VPORT_YOFFSET_15                                                0xa16c
+#define mmPA_CL_VPORT_ZSCALE_1                                                  0xa119
+#define mmPA_CL_VPORT_ZSCALE_2                                                  0xa11f
+#define mmPA_CL_VPORT_ZSCALE_3                                                  0xa125
+#define mmPA_CL_VPORT_ZSCALE_4                                                  0xa12b
+#define mmPA_CL_VPORT_ZSCALE_5                                                  0xa131
+#define mmPA_CL_VPORT_ZSCALE_6                                                  0xa137
+#define mmPA_CL_VPORT_ZSCALE_7                                                  0xa13d
+#define mmPA_CL_VPORT_ZSCALE_8                                                  0xa143
+#define mmPA_CL_VPORT_ZSCALE_9                                                  0xa149
+#define mmPA_CL_VPORT_ZSCALE_10                                                 0xa14f
+#define mmPA_CL_VPORT_ZSCALE_11                                                 0xa155
+#define mmPA_CL_VPORT_ZSCALE_12                                                 0xa15b
+#define mmPA_CL_VPORT_ZSCALE_13                                                 0xa161
+#define mmPA_CL_VPORT_ZSCALE_14                                                 0xa167
+#define mmPA_CL_VPORT_ZSCALE_15                                                 0xa16d
+#define mmPA_CL_VPORT_ZOFFSET_1                                                 0xa11a
+#define mmPA_CL_VPORT_ZOFFSET_2                                                 0xa120
+#define mmPA_CL_VPORT_ZOFFSET_3                                                 0xa126
+#define mmPA_CL_VPORT_ZOFFSET_4                                                 0xa12c
+#define mmPA_CL_VPORT_ZOFFSET_5                                                 0xa132
+#define mmPA_CL_VPORT_ZOFFSET_6                                                 0xa138
+#define mmPA_CL_VPORT_ZOFFSET_7                                                 0xa13e
+#define mmPA_CL_VPORT_ZOFFSET_8                                                 0xa144
+#define mmPA_CL_VPORT_ZOFFSET_9                                                 0xa14a
+#define mmPA_CL_VPORT_ZOFFSET_10                                                0xa150
+#define mmPA_CL_VPORT_ZOFFSET_11                                                0xa156
+#define mmPA_CL_VPORT_ZOFFSET_12                                                0xa15c
+#define mmPA_CL_VPORT_ZOFFSET_13                                                0xa162
+#define mmPA_CL_VPORT_ZOFFSET_14                                                0xa168
+#define mmPA_CL_VPORT_ZOFFSET_15                                                0xa16e
+#define mmPA_CL_VTE_CNTL                                                        0xa206
+#define mmPA_CL_VS_OUT_CNTL                                                     0xa207
+#define mmPA_CL_NANINF_CNTL                                                     0xa208
+#define mmPA_CL_CLIP_CNTL                                                       0xa204
+#define mmPA_CL_GB_VERT_CLIP_ADJ                                                0xa2fa
+#define mmPA_CL_GB_VERT_DISC_ADJ                                                0xa2fb
+#define mmPA_CL_GB_HORZ_CLIP_ADJ                                                0xa2fc
+#define mmPA_CL_GB_HORZ_DISC_ADJ                                                0xa2fd
+#define mmPA_CL_UCP_0_X                                                         0xa16f
+#define mmPA_CL_UCP_0_Y                                                         0xa170
+#define mmPA_CL_UCP_0_Z                                                         0xa171
+#define mmPA_CL_UCP_0_W                                                         0xa172
+#define mmPA_CL_UCP_1_X                                                         0xa173
+#define mmPA_CL_UCP_1_Y                                                         0xa174
+#define mmPA_CL_UCP_1_Z                                                         0xa175
+#define mmPA_CL_UCP_1_W                                                         0xa176
+#define mmPA_CL_UCP_2_X                                                         0xa177
+#define mmPA_CL_UCP_2_Y                                                         0xa178
+#define mmPA_CL_UCP_2_Z                                                         0xa179
+#define mmPA_CL_UCP_2_W                                                         0xa17a
+#define mmPA_CL_UCP_3_X                                                         0xa17b
+#define mmPA_CL_UCP_3_Y                                                         0xa17c
+#define mmPA_CL_UCP_3_Z                                                         0xa17d
+#define mmPA_CL_UCP_3_W                                                         0xa17e
+#define mmPA_CL_UCP_4_X                                                         0xa17f
+#define mmPA_CL_UCP_4_Y                                                         0xa180
+#define mmPA_CL_UCP_4_Z                                                         0xa181
+#define mmPA_CL_UCP_4_W                                                         0xa182
+#define mmPA_CL_UCP_5_X                                                         0xa183
+#define mmPA_CL_UCP_5_Y                                                         0xa184
+#define mmPA_CL_UCP_5_Z                                                         0xa185
+#define mmPA_CL_UCP_5_W                                                         0xa186
+#define mmPA_CL_POINT_X_RAD                                                     0xa1f5
+#define mmPA_CL_POINT_Y_RAD                                                     0xa1f6
+#define mmPA_CL_POINT_SIZE                                                      0xa1f7
+#define mmPA_CL_POINT_CULL_RAD                                                  0xa1f8
+#define mmPA_CL_ENHANCE                                                         0x2285
+#define mmPA_CL_RESET_DEBUG                                                     0x2286
+#define mmPA_SU_VTX_CNTL                                                        0xa2f9
+#define mmPA_SU_POINT_SIZE                                                      0xa280
+#define mmPA_SU_POINT_MINMAX                                                    0xa281
+#define mmPA_SU_LINE_CNTL                                                       0xa282
+#define mmPA_SU_LINE_STIPPLE_CNTL                                               0xa209
+#define mmPA_SU_LINE_STIPPLE_SCALE                                              0xa20a
+#define mmPA_SU_PRIM_FILTER_CNTL                                                0xa20b
+#define mmPA_SU_SC_MODE_CNTL                                                    0xa205
+#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                                         0xa2de
+#define mmPA_SU_POLY_OFFSET_CLAMP                                               0xa2df
+#define mmPA_SU_POLY_OFFSET_FRONT_SCALE                                         0xa2e0
+#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                                        0xa2e1
+#define mmPA_SU_POLY_OFFSET_BACK_SCALE                                          0xa2e2
+#define mmPA_SU_POLY_OFFSET_BACK_OFFSET                                         0xa2e3
+#define mmPA_SU_HARDWARE_SCREEN_OFFSET                                          0xa08d
+#define mmPA_SU_LINE_STIPPLE_VALUE                                              0xc280
+#define mmPA_SU_PERFCOUNTER0_SELECT                                             0xd900
+#define mmPA_SU_PERFCOUNTER0_SELECT1                                            0xd901
+#define mmPA_SU_PERFCOUNTER1_SELECT                                             0xd902
+#define mmPA_SU_PERFCOUNTER1_SELECT1                                            0xd903
+#define mmPA_SU_PERFCOUNTER2_SELECT                                             0xd904
+#define mmPA_SU_PERFCOUNTER3_SELECT                                             0xd905
+#define mmPA_SU_PERFCOUNTER0_LO                                                 0xd100
+#define mmPA_SU_PERFCOUNTER0_HI                                                 0xd101
+#define mmPA_SU_PERFCOUNTER1_LO                                                 0xd102
+#define mmPA_SU_PERFCOUNTER1_HI                                                 0xd103
+#define mmPA_SU_PERFCOUNTER2_LO                                                 0xd104
+#define mmPA_SU_PERFCOUNTER2_HI                                                 0xd105
+#define mmPA_SU_PERFCOUNTER3_LO                                                 0xd106
+#define mmPA_SU_PERFCOUNTER3_HI                                                 0xd107
+#define mmPA_SC_AA_CONFIG                                                       0xa2f8
+#define mmPA_SC_AA_MASK_X0Y0_X1Y0                                               0xa30e
+#define mmPA_SC_AA_MASK_X0Y1_X1Y1                                               0xa30f
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                     0xa2fe
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                     0xa2ff
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                     0xa300
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                     0xa301
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                     0xa302
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                     0xa303
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                     0xa304
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                     0xa305
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                     0xa306
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                     0xa307
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                     0xa308
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                     0xa309
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                     0xa30a
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                     0xa30b
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                     0xa30c
+#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                     0xa30d
+#define mmPA_SC_CENTROID_PRIORITY_0                                             0xa2f5
+#define mmPA_SC_CENTROID_PRIORITY_1                                             0xa2f6
+#define mmPA_SC_CLIPRECT_0_TL                                                   0xa084
+#define mmPA_SC_CLIPRECT_0_BR                                                   0xa085
+#define mmPA_SC_CLIPRECT_1_TL                                                   0xa086
+#define mmPA_SC_CLIPRECT_1_BR                                                   0xa087
+#define mmPA_SC_CLIPRECT_2_TL                                                   0xa088
+#define mmPA_SC_CLIPRECT_2_BR                                                   0xa089
+#define mmPA_SC_CLIPRECT_3_TL                                                   0xa08a
+#define mmPA_SC_CLIPRECT_3_BR                                                   0xa08b
+#define mmPA_SC_CLIPRECT_RULE                                                   0xa083
+#define mmPA_SC_EDGERULE                                                        0xa08c
+#define mmPA_SC_LINE_CNTL                                                       0xa2f7
+#define mmPA_SC_LINE_STIPPLE                                                    0xa283
+#define mmPA_SC_MODE_CNTL_0                                                     0xa292
+#define mmPA_SC_MODE_CNTL_1                                                     0xa293
+#define mmPA_SC_RASTER_CONFIG                                                   0xa0d4
+#define mmPA_SC_RASTER_CONFIG_1                                                 0xa0d5
+#define mmPA_SC_SCREEN_EXTENT_CONTROL                                           0xa0d6
+#define mmPA_SC_GENERIC_SCISSOR_TL                                              0xa090
+#define mmPA_SC_GENERIC_SCISSOR_BR                                              0xa091
+#define mmPA_SC_SCREEN_SCISSOR_TL                                               0xa00c
+#define mmPA_SC_SCREEN_SCISSOR_BR                                               0xa00d
+#define mmPA_SC_WINDOW_OFFSET                                                   0xa080
+#define mmPA_SC_WINDOW_SCISSOR_TL                                               0xa081
+#define mmPA_SC_WINDOW_SCISSOR_BR                                               0xa082
+#define mmPA_SC_VPORT_SCISSOR_0_TL                                              0xa094
+#define mmPA_SC_VPORT_SCISSOR_1_TL                                              0xa096
+#define mmPA_SC_VPORT_SCISSOR_2_TL                                              0xa098
+#define mmPA_SC_VPORT_SCISSOR_3_TL                                              0xa09a
+#define mmPA_SC_VPORT_SCISSOR_4_TL                                              0xa09c
+#define mmPA_SC_VPORT_SCISSOR_5_TL                                              0xa09e
+#define mmPA_SC_VPORT_SCISSOR_6_TL                                              0xa0a0
+#define mmPA_SC_VPORT_SCISSOR_7_TL                                              0xa0a2
+#define mmPA_SC_VPORT_SCISSOR_8_TL                                              0xa0a4
+#define mmPA_SC_VPORT_SCISSOR_9_TL                                              0xa0a6
+#define mmPA_SC_VPORT_SCISSOR_10_TL                                             0xa0a8
+#define mmPA_SC_VPORT_SCISSOR_11_TL                                             0xa0aa
+#define mmPA_SC_VPORT_SCISSOR_12_TL                                             0xa0ac
+#define mmPA_SC_VPORT_SCISSOR_13_TL                                             0xa0ae
+#define mmPA_SC_VPORT_SCISSOR_14_TL                                             0xa0b0
+#define mmPA_SC_VPORT_SCISSOR_15_TL                                             0xa0b2
+#define mmPA_SC_VPORT_SCISSOR_0_BR                                              0xa095
+#define mmPA_SC_VPORT_SCISSOR_1_BR                                              0xa097
+#define mmPA_SC_VPORT_SCISSOR_2_BR                                              0xa099
+#define mmPA_SC_VPORT_SCISSOR_3_BR                                              0xa09b
+#define mmPA_SC_VPORT_SCISSOR_4_BR                                              0xa09d
+#define mmPA_SC_VPORT_SCISSOR_5_BR                                              0xa09f
+#define mmPA_SC_VPORT_SCISSOR_6_BR                                              0xa0a1
+#define mmPA_SC_VPORT_SCISSOR_7_BR                                              0xa0a3
+#define mmPA_SC_VPORT_SCISSOR_8_BR                                              0xa0a5
+#define mmPA_SC_VPORT_SCISSOR_9_BR                                              0xa0a7
+#define mmPA_SC_VPORT_SCISSOR_10_BR                                             0xa0a9
+#define mmPA_SC_VPORT_SCISSOR_11_BR                                             0xa0ab
+#define mmPA_SC_VPORT_SCISSOR_12_BR                                             0xa0ad
+#define mmPA_SC_VPORT_SCISSOR_13_BR                                             0xa0af
+#define mmPA_SC_VPORT_SCISSOR_14_BR                                             0xa0b1
+#define mmPA_SC_VPORT_SCISSOR_15_BR                                             0xa0b3
+#define mmPA_SC_VPORT_ZMIN_0                                                    0xa0b4
+#define mmPA_SC_VPORT_ZMIN_1                                                    0xa0b6
+#define mmPA_SC_VPORT_ZMIN_2                                                    0xa0b8
+#define mmPA_SC_VPORT_ZMIN_3                                                    0xa0ba
+#define mmPA_SC_VPORT_ZMIN_4                                                    0xa0bc
+#define mmPA_SC_VPORT_ZMIN_5                                                    0xa0be
+#define mmPA_SC_VPORT_ZMIN_6                                                    0xa0c0
+#define mmPA_SC_VPORT_ZMIN_7                                                    0xa0c2
+#define mmPA_SC_VPORT_ZMIN_8                                                    0xa0c4
+#define mmPA_SC_VPORT_ZMIN_9                                                    0xa0c6
+#define mmPA_SC_VPORT_ZMIN_10                                                   0xa0c8
+#define mmPA_SC_VPORT_ZMIN_11                                                   0xa0ca
+#define mmPA_SC_VPORT_ZMIN_12                                                   0xa0cc
+#define mmPA_SC_VPORT_ZMIN_13                                                   0xa0ce
+#define mmPA_SC_VPORT_ZMIN_14                                                   0xa0d0
+#define mmPA_SC_VPORT_ZMIN_15                                                   0xa0d2
+#define mmPA_SC_VPORT_ZMAX_0                                                    0xa0b5
+#define mmPA_SC_VPORT_ZMAX_1                                                    0xa0b7
+#define mmPA_SC_VPORT_ZMAX_2                                                    0xa0b9
+#define mmPA_SC_VPORT_ZMAX_3                                                    0xa0bb
+#define mmPA_SC_VPORT_ZMAX_4                                                    0xa0bd
+#define mmPA_SC_VPORT_ZMAX_5                                                    0xa0bf
+#define mmPA_SC_VPORT_ZMAX_6                                                    0xa0c1
+#define mmPA_SC_VPORT_ZMAX_7                                                    0xa0c3
+#define mmPA_SC_VPORT_ZMAX_8                                                    0xa0c5
+#define mmPA_SC_VPORT_ZMAX_9                                                    0xa0c7
+#define mmPA_SC_VPORT_ZMAX_10                                                   0xa0c9
+#define mmPA_SC_VPORT_ZMAX_11                                                   0xa0cb
+#define mmPA_SC_VPORT_ZMAX_12                                                   0xa0cd
+#define mmPA_SC_VPORT_ZMAX_13                                                   0xa0cf
+#define mmPA_SC_VPORT_ZMAX_14                                                   0xa0d1
+#define mmPA_SC_VPORT_ZMAX_15                                                   0xa0d3
+#define mmPA_SC_ENHANCE                                                         0x22fc
+#define mmPA_SC_FIFO_SIZE                                                       0x22f3
+#define mmPA_SC_IF_FIFO_SIZE                                                    0x22f5
+#define mmPA_SC_FORCE_EOV_MAX_CNTS                                              0x22c9
+#define mmPA_SC_LINE_STIPPLE_STATE                                              0xc281
+#define mmPA_SC_SCREEN_EXTENT_MIN_0                                             0xc284
+#define mmPA_SC_SCREEN_EXTENT_MAX_0                                             0xc285
+#define mmPA_SC_SCREEN_EXTENT_MIN_1                                             0xc286
+#define mmPA_SC_SCREEN_EXTENT_MAX_1                                             0xc28b
+#define mmPA_SC_PERFCOUNTER0_SELECT                                             0xd940
+#define mmPA_SC_PERFCOUNTER0_SELECT1                                            0xd941
+#define mmPA_SC_PERFCOUNTER1_SELECT                                             0xd942
+#define mmPA_SC_PERFCOUNTER2_SELECT                                             0xd943
+#define mmPA_SC_PERFCOUNTER3_SELECT                                             0xd944
+#define mmPA_SC_PERFCOUNTER4_SELECT                                             0xd945
+#define mmPA_SC_PERFCOUNTER5_SELECT                                             0xd946
+#define mmPA_SC_PERFCOUNTER6_SELECT                                             0xd947
+#define mmPA_SC_PERFCOUNTER7_SELECT                                             0xd948
+#define mmPA_SC_PERFCOUNTER0_LO                                                 0xd140
+#define mmPA_SC_PERFCOUNTER0_HI                                                 0xd141
+#define mmPA_SC_PERFCOUNTER1_LO                                                 0xd142
+#define mmPA_SC_PERFCOUNTER1_HI                                                 0xd143
+#define mmPA_SC_PERFCOUNTER2_LO                                                 0xd144
+#define mmPA_SC_PERFCOUNTER2_HI                                                 0xd145
+#define mmPA_SC_PERFCOUNTER3_LO                                                 0xd146
+#define mmPA_SC_PERFCOUNTER3_HI                                                 0xd147
+#define mmPA_SC_PERFCOUNTER4_LO                                                 0xd148
+#define mmPA_SC_PERFCOUNTER4_HI                                                 0xd149
+#define mmPA_SC_PERFCOUNTER5_LO                                                 0xd14a
+#define mmPA_SC_PERFCOUNTER5_HI                                                 0xd14b
+#define mmPA_SC_PERFCOUNTER6_LO                                                 0xd14c
+#define mmPA_SC_PERFCOUNTER6_HI                                                 0xd14d
+#define mmPA_SC_PERFCOUNTER7_LO                                                 0xd14e
+#define mmPA_SC_PERFCOUNTER7_HI                                                 0xd14f
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN                                           0xc2a0
+#define mmPA_SC_P3D_TRAP_SCREEN_H                                               0xc2a1
+#define mmPA_SC_P3D_TRAP_SCREEN_V                                               0xc2a2
+#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                      0xc2a3
+#define mmPA_SC_P3D_TRAP_SCREEN_COUNT                                           0xc2a4
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                                          0xc2a8
+#define mmPA_SC_HP3D_TRAP_SCREEN_H                                              0xc2a9
+#define mmPA_SC_HP3D_TRAP_SCREEN_V                                              0xc2aa
+#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                     0xc2ab
+#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT                                          0xc2ac
+#define mmPA_SC_TRAP_SCREEN_HV_EN                                               0xc2b0
+#define mmPA_SC_TRAP_SCREEN_H                                                   0xc2b1
+#define mmPA_SC_TRAP_SCREEN_V                                                   0xc2b2
+#define mmPA_SC_TRAP_SCREEN_OCCURRENCE                                          0xc2b3
+#define mmPA_SC_TRAP_SCREEN_COUNT                                               0xc2b4
+#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                         0x22c0
+#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                        0x22c1
+#define mmPA_SC_TRAP_SCREEN_HV_LOCK                                             0x22c2
+#define mmPA_CL_CNTL_STATUS                                                     0x2284
+#define mmPA_SU_CNTL_STATUS                                                     0x2294
+#define mmPA_SC_FIFO_DEPTH_CNTL                                                 0x2295
+#define mmCGTT_PA_CLK_CTRL                                                      0xf088
+#define mmCGTT_SC_CLK_CTRL                                                      0xf089
+#define mmPA_SU_DEBUG_CNTL                                                      0x2280
+#define mmPA_SU_DEBUG_DATA                                                      0x2281
+#define mmPA_SC_DEBUG_CNTL                                                      0x22f6
+#define mmPA_SC_DEBUG_DATA                                                      0x22f7
+#define ixCLIPPER_DEBUG_REG00                                                   0x0
+#define ixCLIPPER_DEBUG_REG01                                                   0x1
+#define ixCLIPPER_DEBUG_REG02                                                   0x2
+#define ixCLIPPER_DEBUG_REG03                                                   0x3
+#define ixCLIPPER_DEBUG_REG04                                                   0x4
+#define ixCLIPPER_DEBUG_REG05                                                   0x5
+#define ixCLIPPER_DEBUG_REG06                                                   0x6
+#define ixCLIPPER_DEBUG_REG07                                                   0x7
+#define ixCLIPPER_DEBUG_REG08                                                   0x8
+#define ixCLIPPER_DEBUG_REG09                                                   0x9
+#define ixCLIPPER_DEBUG_REG10                                                   0xa
+#define ixCLIPPER_DEBUG_REG11                                                   0xb
+#define ixCLIPPER_DEBUG_REG12                                                   0xc
+#define ixCLIPPER_DEBUG_REG13                                                   0xd
+#define ixCLIPPER_DEBUG_REG14                                                   0xe
+#define ixCLIPPER_DEBUG_REG15                                                   0xf
+#define ixCLIPPER_DEBUG_REG16                                                   0x10
+#define ixCLIPPER_DEBUG_REG17                                                   0x11
+#define ixCLIPPER_DEBUG_REG18                                                   0x12
+#define ixCLIPPER_DEBUG_REG19                                                   0x13
+#define ixSXIFCCG_DEBUG_REG0                                                    0x14
+#define ixSXIFCCG_DEBUG_REG1                                                    0x15
+#define ixSXIFCCG_DEBUG_REG2                                                    0x16
+#define ixSXIFCCG_DEBUG_REG3                                                    0x17
+#define ixSETUP_DEBUG_REG0                                                      0x18
+#define ixSETUP_DEBUG_REG1                                                      0x19
+#define ixSETUP_DEBUG_REG2                                                      0x1a
+#define ixSETUP_DEBUG_REG3                                                      0x1b
+#define ixSETUP_DEBUG_REG4                                                      0x1c
+#define ixSETUP_DEBUG_REG5                                                      0x1d
+#define ixPA_SC_DEBUG_REG0                                                      0x0
+#define ixPA_SC_DEBUG_REG1                                                      0x1
+#define mmCOMPUTE_DISPATCH_INITIATOR                                            0x2e00
+#define mmCOMPUTE_DIM_X                                                         0x2e01
+#define mmCOMPUTE_DIM_Y                                                         0x2e02
+#define mmCOMPUTE_DIM_Z                                                         0x2e03
+#define mmCOMPUTE_START_X                                                       0x2e04
+#define mmCOMPUTE_START_Y                                                       0x2e05
+#define mmCOMPUTE_START_Z                                                       0x2e06
+#define mmCOMPUTE_NUM_THREAD_X                                                  0x2e07
+#define mmCOMPUTE_NUM_THREAD_Y                                                  0x2e08
+#define mmCOMPUTE_NUM_THREAD_Z                                                  0x2e09
+#define mmCOMPUTE_PIPELINESTAT_ENABLE                                           0x2e0a
+#define mmCOMPUTE_PERFCOUNT_ENABLE                                              0x2e0b
+#define mmCOMPUTE_PGM_LO                                                        0x2e0c
+#define mmCOMPUTE_PGM_HI                                                        0x2e0d
+#define mmCOMPUTE_TBA_LO                                                        0x2e0e
+#define mmCOMPUTE_TBA_HI                                                        0x2e0f
+#define mmCOMPUTE_TMA_LO                                                        0x2e10
+#define mmCOMPUTE_TMA_HI                                                        0x2e11
+#define mmCOMPUTE_PGM_RSRC1                                                     0x2e12
+#define mmCOMPUTE_PGM_RSRC2                                                     0x2e13
+#define mmCOMPUTE_VMID                                                          0x2e14
+#define mmCOMPUTE_RESOURCE_LIMITS                                               0x2e15
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                                        0x2e16
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                                        0x2e17
+#define mmCOMPUTE_TMPRING_SIZE                                                  0x2e18
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2                                        0x2e19
+#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3                                        0x2e1a
+#define mmCOMPUTE_RESTART_X                                                     0x2e1b
+#define mmCOMPUTE_RESTART_Y                                                     0x2e1c
+#define mmCOMPUTE_RESTART_Z                                                     0x2e1d
+#define mmCOMPUTE_THREAD_TRACE_ENABLE                                           0x2e1e
+#define mmCOMPUTE_MISC_RESERVED                                                 0x2e1f
+#define mmCOMPUTE_DISPATCH_ID                                                   0x2e20
+#define mmCOMPUTE_THREADGROUP_ID                                                0x2e21
+#define mmCOMPUTE_RELAUNCH                                                      0x2e22
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO                                          0x2e23
+#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI                                          0x2e24
+#define mmCOMPUTE_WAVE_RESTORE_CONTROL                                          0x2e25
+#define mmCOMPUTE_USER_DATA_0                                                   0x2e40
+#define mmCOMPUTE_USER_DATA_1                                                   0x2e41
+#define mmCOMPUTE_USER_DATA_2                                                   0x2e42
+#define mmCOMPUTE_USER_DATA_3                                                   0x2e43
+#define mmCOMPUTE_USER_DATA_4                                                   0x2e44
+#define mmCOMPUTE_USER_DATA_5                                                   0x2e45
+#define mmCOMPUTE_USER_DATA_6                                                   0x2e46
+#define mmCOMPUTE_USER_DATA_7                                                   0x2e47
+#define mmCOMPUTE_USER_DATA_8                                                   0x2e48
+#define mmCOMPUTE_USER_DATA_9                                                   0x2e49
+#define mmCOMPUTE_USER_DATA_10                                                  0x2e4a
+#define mmCOMPUTE_USER_DATA_11                                                  0x2e4b
+#define mmCOMPUTE_USER_DATA_12                                                  0x2e4c
+#define mmCOMPUTE_USER_DATA_13                                                  0x2e4d
+#define mmCOMPUTE_USER_DATA_14                                                  0x2e4e
+#define mmCOMPUTE_USER_DATA_15                                                  0x2e4f
+#define mmCOMPUTE_NOWHERE                                                       0x2e7f
+#define mmCSPRIV_CONNECT                                                        0x0
+#define mmCSPRIV_THREAD_TRACE_TG0                                               0x1e
+#define mmCSPRIV_THREAD_TRACE_TG1                                               0x1e
+#define mmCSPRIV_THREAD_TRACE_TG2                                               0x1e
+#define mmCSPRIV_THREAD_TRACE_TG3                                               0x1e
+#define mmCSPRIV_THREAD_TRACE_EVENT                                             0x1f
+#define mmRLC_CNTL                                                              0xec00
+#define mmRLC_DEBUG_SELECT                                                      0xec01
+#define mmRLC_DEBUG                                                             0xec02
+#define mmRLC_MC_CNTL                                                           0xec03
+#define mmRLC_STAT                                                              0xec04
+#define mmRLC_SAFE_MODE                                                         0xec05
+#define mmRLC_SOFT_RESET_GPU                                                    0xec05
+#define mmRLC_MEM_SLP_CNTL                                                      0xec06
+#define mmSMU_RLC_RESPONSE                                                      0xec07
+#define mmRLC_RLCV_SAFE_MODE                                                    0xec08
+#define mmRLC_SMU_SAFE_MODE                                                     0xec09
+#define mmRLC_RLCV_COMMAND                                                      0xec0a
+#define mmRLC_PERFMON_CLK_CNTL                                                  0xdcbf
+#define mmRLC_PERFMON_CNTL                                                      0xdcc0
+#define mmRLC_PERFCOUNTER0_SELECT                                               0xdcc1
+#define mmRLC_PERFCOUNTER1_SELECT                                               0xdcc2
+#define mmRLC_PERFCOUNTER0_LO                                                   0xd480
+#define mmRLC_PERFCOUNTER1_LO                                                   0xd482
+#define mmRLC_PERFCOUNTER0_HI                                                   0xd481
+#define mmRLC_PERFCOUNTER1_HI                                                   0xd483
+#define mmCGTT_RLC_CLK_CTRL                                                     0xf0b8
+#define mmRLC_LB_CNTL                                                           0xec19
+#define mmRLC_LB_CNTR_MAX                                                       0xec12
+#define mmRLC_LB_CNTR_INIT                                                      0xec1b
+#define mmRLC_LOAD_BALANCE_CNTR                                                 0xec1c
+#define mmRLC_SAVE_AND_RESTORE_BASE                                             0xec1d
+#define mmRLC_JUMP_TABLE_RESTORE                                                0xec1e
+#define mmRLC_DRIVER_CPDMA_STATUS                                               0xec1e
+#define mmRLC_PG_DELAY_2                                                        0xec1f
+#define mmRLC_GPM_DEBUG_SELECT                                                  0xec20
+#define mmRLC_GPM_DEBUG                                                         0xec21
+#define mmRLC_HYP_GPM_UCODE_ADDR                                                0xf83c
+#define mmRLC_GPM_UCODE_ADDR                                                    0xf83c
+#define mmRLC_HYP_GPM_UCODE_DATA                                                0xf83d
+#define mmRLC_GPM_UCODE_DATA                                                    0xf83d
+#define mmGPU_BIST_CONTROL                                                      0xf835
+#define mmRLC_ROM_CNTL                                                          0xf836
+#define mmRLC_GPU_CLOCK_COUNT_LSB                                               0xec24
+#define mmRLC_GPU_CLOCK_COUNT_MSB                                               0xec25
+#define mmRLC_CAPTURE_GPU_CLOCK_COUNT                                           0xec26
+#define mmRLC_UCODE_CNTL                                                        0xec27
+#define mmRLC_GPM_STAT                                                          0xec40
+#define mmRLC_GPU_CLOCK_32_RES_SEL                                              0xec41
+#define mmRLC_GPU_CLOCK_32                                                      0xec42
+#define mmRLC_PG_CNTL                                                           0xec43
+#define mmRLC_GPM_THREAD_PRIORITY                                               0xec44
+#define mmRLC_GPM_THREAD_ENABLE                                                 0xec45
+#define mmRLC_GPM_VMID_THREAD0                                                  0xec46
+#define mmRLC_GPM_VMID_THREAD1                                                  0xec47
+#define mmRLC_CGTT_MGCG_OVERRIDE                                                0xec48
+#define mmRLC_CGCG_CGLS_CTRL                                                    0xec49
+#define mmRLC_CGCG_RAMP_CTRL                                                    0xec4a
+#define mmRLC_DYN_PG_STATUS                                                     0xec4b
+#define mmRLC_DYN_PG_REQUEST                                                    0xec4c
+#define mmRLC_PG_DELAY                                                          0xec4d
+#define mmRLC_CU_STATUS                                                         0xec4e
+#define mmRLC_LB_INIT_CU_MASK                                                   0xec4f
+#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK                                          0xec50
+#define mmRLC_LB_PARAMS                                                         0xec51
+#define mmRLC_THREAD1_DELAY                                                     0xec52
+#define mmRLC_PG_ALWAYS_ON_CU_MASK                                              0xec53
+#define mmRLC_MAX_PG_CU                                                         0xec54
+#define mmRLC_AUTO_PG_CTRL                                                      0xec55
+#define mmRLC_SMU_GRBM_REG_SAVE_CTRL                                            0xec56
+#define mmRLC_SMU_PG_CTRL                                                       0xec57
+#define mmRLC_SMU_PG_WAKE_UP_CTRL                                               0xec58
+#define mmRLC_SERDES_RD_MASTER_INDEX                                            0xec59
+#define mmRLC_SERDES_RD_DATA_0                                                  0xec5a
+#define mmRLC_SERDES_RD_DATA_1                                                  0xec5b
+#define mmRLC_SERDES_RD_DATA_2                                                  0xec5c
+#define mmRLC_SERDES_WR_CU_MASTER_MASK                                          0xec5d
+#define mmRLC_SERDES_WR_NONCU_MASTER_MASK                                       0xec5e
+#define mmRLC_SERDES_WR_CTRL                                                    0xec5f
+#define mmRLC_SERDES_WR_DATA                                                    0xec60
+#define mmRLC_SERDES_CU_MASTER_BUSY                                             0xec61
+#define mmRLC_SERDES_NONCU_MASTER_BUSY                                          0xec62
+#define mmRLC_GPM_GENERAL_0                                                     0xec63
+#define mmRLC_GPM_GENERAL_1                                                     0xec64
+#define mmRLC_GPM_GENERAL_2                                                     0xec65
+#define mmRLC_GPM_GENERAL_3                                                     0xec66
+#define mmRLC_GPM_GENERAL_4                                                     0xec67
+#define mmRLC_GPM_GENERAL_5                                                     0xec68
+#define mmRLC_GPM_GENERAL_6                                                     0xec69
+#define mmRLC_GPM_GENERAL_7                                                     0xec6a
+#define mmRLC_GPM_CU_PD_TIMEOUT                                                 0xec6b
+#define mmRLC_GPM_SCRATCH_ADDR                                                  0xec6c
+#define mmRLC_GPM_SCRATCH_DATA                                                  0xec6d
+#define mmRLC_STATIC_PG_STATUS                                                  0xec6e
+#define mmRLC_GPM_PERF_COUNT_0                                                  0xec6f
+#define mmRLC_GPM_PERF_COUNT_1                                                  0xec70
+#define mmRLC_GPR_REG1                                                          0xec79
+#define mmRLC_GPR_REG2                                                          0xec7a
+#define mmRLC_MGCG_CTRL                                                         0xec1a
+#define mmRLC_GPM_THREAD_RESET                                                  0xec28
+#define mmRLC_SPM_VMID                                                          0xec71
+#define mmRLC_SPM_INT_CNTL                                                      0xec72
+#define mmRLC_SPM_INT_STATUS                                                    0xec73
+#define mmRLC_SPM_DEBUG_SELECT                                                  0xec74
+#define mmRLC_SPM_DEBUG                                                         0xec75
+#define mmRLC_GPM_LOG_ADDR                                                      0xec76
+#define mmRLC_SMU_MESSAGE                                                       0xec76
+#define mmRLC_GPM_LOG_SIZE                                                      0xec77
+#define mmRLC_GPM_LOG_CONT                                                      0xec7b
+#define mmRLC_PG_DELAY_3                                                        0xec78
+#define mmRLC_GPM_INT_DISABLE_TH0                                               0xec7c
+#define mmRLC_GPM_INT_DISABLE_TH1                                               0xec7d
+#define mmRLC_GPM_INT_FORCE_TH0                                                 0xec7e
+#define mmRLC_GPM_INT_FORCE_TH1                                                 0xec7f
+#define mmRLC_SRM_CNTL                                                          0xec80
+#define mmRLC_SRM_DEBUG_SELECT                                                  0xec81
+#define mmRLC_SRM_DEBUG                                                         0xec82
+#define mmRLC_SRM_ARAM_ADDR                                                     0xec83
+#define mmRLC_SRM_ARAM_DATA                                                     0xec84
+#define mmRLC_SRM_DRAM_ADDR                                                     0xec85
+#define mmRLC_SRM_DRAM_DATA                                                     0xec86
+#define mmRLC_SRM_GPM_COMMAND                                                   0xec87
+#define mmRLC_SRM_GPM_COMMAND_STATUS                                            0xec88
+#define mmRLC_SRM_RLCV_COMMAND                                                  0xec89
+#define mmRLC_SRM_RLCV_COMMAND_STATUS                                           0xec8a
+#define mmRLC_SRM_INDEX_CNTL_ADDR_0                                             0xec8b
+#define mmRLC_SRM_INDEX_CNTL_ADDR_1                                             0xec8c
+#define mmRLC_SRM_INDEX_CNTL_ADDR_2                                             0xec8d
+#define mmRLC_SRM_INDEX_CNTL_ADDR_3                                             0xec8e
+#define mmRLC_SRM_INDEX_CNTL_ADDR_4                                             0xec8f
+#define mmRLC_SRM_INDEX_CNTL_ADDR_5                                             0xec90
+#define mmRLC_SRM_INDEX_CNTL_ADDR_6                                             0xec91
+#define mmRLC_SRM_INDEX_CNTL_ADDR_7                                             0xec92
+#define mmRLC_SRM_INDEX_CNTL_DATA_0                                             0xec93
+#define mmRLC_SRM_INDEX_CNTL_DATA_1                                             0xec94
+#define mmRLC_SRM_INDEX_CNTL_DATA_2                                             0xec95
+#define mmRLC_SRM_INDEX_CNTL_DATA_3                                             0xec96
+#define mmRLC_SRM_INDEX_CNTL_DATA_4                                             0xec97
+#define mmRLC_SRM_INDEX_CNTL_DATA_5                                             0xec98
+#define mmRLC_SRM_INDEX_CNTL_DATA_6                                             0xec99
+#define mmRLC_SRM_INDEX_CNTL_DATA_7                                             0xec9a
+#define mmRLC_SRM_STAT                                                          0xec9b
+#define mmRLC_SRM_GPM_ABORT                                                     0xec9c
+#define mmRLC_CSIB_ADDR_LO                                                      0xeca2
+#define mmRLC_CSIB_ADDR_HI                                                      0xeca3
+#define mmRLC_CSIB_LENGTH                                                       0xeca4
+#define mmRLC_CP_RESPONSE0                                                      0xeca5
+#define mmRLC_CP_RESPONSE1                                                      0xeca6
+#define mmRLC_CP_RESPONSE2                                                      0xeca7
+#define mmRLC_CP_RESPONSE3                                                      0xeca8
+#define mmRLC_SMU_COMMAND                                                       0xeca9
+#define mmRLC_CP_SCHEDULERS                                                     0xecaa
+#define mmRLC_SPM_PERFMON_CNTL                                                  0xdc80
+#define mmRLC_SPM_PERFMON_RING_BASE_LO                                          0xdc81
+#define mmRLC_SPM_PERFMON_RING_BASE_HI                                          0xdc82
+#define mmRLC_SPM_PERFMON_RING_SIZE                                             0xdc83
+#define mmRLC_SPM_PERFMON_SEGMENT_SIZE                                          0xdc84
+#define mmRLC_SPM_SE_MUXSEL_ADDR                                                0xdc85
+#define mmRLC_SPM_SE_MUXSEL_DATA                                                0xdc86
+#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY                                      0xdc87
+#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY                                      0xdc88
+#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY                                      0xdc89
+#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY                                       0xdc8a
+#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY                                       0xdc8b
+#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY                                       0xdc8c
+#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY                                      0xdc8d
+#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY                                       0xdc8e
+#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY                                       0xdc90
+#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY                                      0xdc91
+#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY                                      0xdc92
+#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY                                      0xdc93
+#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY                                       0xdc94
+#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY                                       0xdc95
+#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY                                      0xdc96
+#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY                                      0xdc97
+#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY                                      0xdc98
+#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY                                       0xdc9a
+#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR                                            0xdc9b
+#define mmRLC_SPM_GLOBAL_MUXSEL_DATA                                            0xdc9c
+#define mmRLC_SPM_RING_RDPTR                                                    0xdc9d
+#define mmRLC_SPM_SEGMENT_THRESHOLD                                             0xdc9e
+#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY                                     0xdc9f
+#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY                                     0xdca0
+#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY                                     0xdca1
+#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY                                     0xdca2
+#define mmRLC_GPU_IOV_VF_ENABLE                                                 0xfb00
+#define mmRLC_GPU_IOV_CFG_REG1                                                  0xfb01
+#define mmRLC_GPU_IOV_CFG_REG2                                                  0xfb02
+#define mmRLC_GPU_IOV_CFG_REG6                                                  0xfb06
+#define mmRLC_GPU_IOV_CFG_REG8                                                  0xfb08
+#define mmRLC_GPU_IOV_CFG_REG9                                                  0xfb21
+#define mmRLC_GPU_IOV_CFG_REG10                                                 0xfb22
+#define mmRLC_GPU_IOV_CFG_REG11                                                 0xfb23
+#define mmRLC_GPU_IOV_CFG_REG12                                                 0xfb24
+#define mmRLC_GPU_IOV_CFG_REG13                                                 0xfb25
+#define mmRLC_GPU_IOV_CFG_REG14                                                 0xfb26
+#define mmRLC_GPU_IOV_CFG_REG15                                                 0xfb27
+#define mmRLC_GPU_IOV_ACTIVE_FCN_ID                                             0xfb40
+#define mmRLC_GPM_VMID_THREAD2                                                  0xfb41
+#define mmRLC_GPU_IOV_UCODE_ADDR                                                0xfb42
+#define mmRLC_GPU_IOV_UCODE_DATA                                                0xfb43
+#define mmRLC_GPU_IOV_SCRATCH_ADDR                                              0xfb44
+#define mmRLC_GPU_IOV_SCRATCH_DATA                                              0xfb45
+#define mmRLC_GPU_IOV_F32_CNTL                                                  0xfb46
+#define mmRLC_GPU_IOV_F32_RESET                                                 0xfb47
+#define mmRLC_GPU_IOV_SDMA0_STATUS                                              0xfb48
+#define mmRLC_GPU_IOV_SDMA1_STATUS                                              0xfb49
+#define mmRLC_GPU_IOV_SMU_RESPONSE                                              0xfb4a
+#define mmRLC_GPU_IOV_VIRT_RESET_REQ                                            0xfb4c
+#define mmRLC_GPU_IOV_RLC_RESPONSE                                              0xfb4d
+#define mmRLC_GPU_IOV_INT_DISABLE                                               0xfb4e
+#define mmRLC_GPU_IOV_INT_FORCE                                                 0xfb4f
+#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS                                         0xfb50
+#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS                                         0xfb51
+#define mmRLC_GPU_IOV_SCH_0                                                     0xfb52
+#define mmRLC_GPU_IOV_SCH_1                                                     0xfb53
+#define mmRLC_GPU_IOV_SCH_2                                                     0xfb54
+#define mmRLC_GPU_IOV_SCH_3                                                     0xfb55
+#define mmRLC_GPU_IOV_SCH_INT                                                   0xfb56
+#define mmSPI_PS_INPUT_CNTL_0                                                   0xa191
+#define mmSPI_PS_INPUT_CNTL_1                                                   0xa192
+#define mmSPI_PS_INPUT_CNTL_2                                                   0xa193
+#define mmSPI_PS_INPUT_CNTL_3                                                   0xa194
+#define mmSPI_PS_INPUT_CNTL_4                                                   0xa195
+#define mmSPI_PS_INPUT_CNTL_5                                                   0xa196
+#define mmSPI_PS_INPUT_CNTL_6                                                   0xa197
+#define mmSPI_PS_INPUT_CNTL_7                                                   0xa198
+#define mmSPI_PS_INPUT_CNTL_8                                                   0xa199
+#define mmSPI_PS_INPUT_CNTL_9                                                   0xa19a
+#define mmSPI_PS_INPUT_CNTL_10                                                  0xa19b
+#define mmSPI_PS_INPUT_CNTL_11                                                  0xa19c
+#define mmSPI_PS_INPUT_CNTL_12                                                  0xa19d
+#define mmSPI_PS_INPUT_CNTL_13                                                  0xa19e
+#define mmSPI_PS_INPUT_CNTL_14                                                  0xa19f
+#define mmSPI_PS_INPUT_CNTL_15                                                  0xa1a0
+#define mmSPI_PS_INPUT_CNTL_16                                                  0xa1a1
+#define mmSPI_PS_INPUT_CNTL_17                                                  0xa1a2
+#define mmSPI_PS_INPUT_CNTL_18                                                  0xa1a3
+#define mmSPI_PS_INPUT_CNTL_19                                                  0xa1a4
+#define mmSPI_PS_INPUT_CNTL_20                                                  0xa1a5
+#define mmSPI_PS_INPUT_CNTL_21                                                  0xa1a6
+#define mmSPI_PS_INPUT_CNTL_22                                                  0xa1a7
+#define mmSPI_PS_INPUT_CNTL_23                                                  0xa1a8
+#define mmSPI_PS_INPUT_CNTL_24                                                  0xa1a9
+#define mmSPI_PS_INPUT_CNTL_25                                                  0xa1aa
+#define mmSPI_PS_INPUT_CNTL_26                                                  0xa1ab
+#define mmSPI_PS_INPUT_CNTL_27                                                  0xa1ac
+#define mmSPI_PS_INPUT_CNTL_28                                                  0xa1ad
+#define mmSPI_PS_INPUT_CNTL_29                                                  0xa1ae
+#define mmSPI_PS_INPUT_CNTL_30                                                  0xa1af
+#define mmSPI_PS_INPUT_CNTL_31                                                  0xa1b0
+#define mmSPI_VS_OUT_CONFIG                                                     0xa1b1
+#define mmSPI_PS_INPUT_ENA                                                      0xa1b3
+#define mmSPI_PS_INPUT_ADDR                                                     0xa1b4
+#define mmSPI_INTERP_CONTROL_0                                                  0xa1b5
+#define mmSPI_PS_IN_CONTROL                                                     0xa1b6
+#define mmSPI_BARYC_CNTL                                                        0xa1b8
+#define mmSPI_TMPRING_SIZE                                                      0xa1ba
+#define mmSPI_SHADER_POS_FORMAT                                                 0xa1c3
+#define mmSPI_SHADER_Z_FORMAT                                                   0xa1c4
+#define mmSPI_SHADER_COL_FORMAT                                                 0xa1c5
+#define mmSPI_ARB_PRIORITY                                                      0x31c0
+#define mmSPI_ARB_CYCLES_0                                                      0x31c1
+#define mmSPI_ARB_CYCLES_1                                                      0x31c2
+#define mmSPI_CDBG_SYS_GFX                                                      0x31c3
+#define mmSPI_CDBG_SYS_HP3D                                                     0x31c4
+#define mmSPI_CDBG_SYS_CS0                                                      0x31c5
+#define mmSPI_CDBG_SYS_CS1                                                      0x31c6
+#define mmSPI_WCL_PIPE_PERCENT_GFX                                              0x31c7
+#define mmSPI_WCL_PIPE_PERCENT_HP3D                                             0x31c8
+#define mmSPI_WCL_PIPE_PERCENT_CS0                                              0x31c9
+#define mmSPI_WCL_PIPE_PERCENT_CS1                                              0x31ca
+#define mmSPI_WCL_PIPE_PERCENT_CS2                                              0x31cb
+#define mmSPI_WCL_PIPE_PERCENT_CS3                                              0x31cc
+#define mmSPI_WCL_PIPE_PERCENT_CS4                                              0x31cd
+#define mmSPI_WCL_PIPE_PERCENT_CS5                                              0x31ce
+#define mmSPI_WCL_PIPE_PERCENT_CS6                                              0x31cf
+#define mmSPI_WCL_PIPE_PERCENT_CS7                                              0x31d0
+#define mmSPI_GDBG_WAVE_CNTL                                                    0x31d1
+#define mmSPI_GDBG_TRAP_CONFIG                                                  0x31d2
+#define mmSPI_GDBG_TRAP_MASK                                                    0x31d3
+#define mmSPI_GDBG_TBA_LO                                                       0x31d4
+#define mmSPI_GDBG_TBA_HI                                                       0x31d5
+#define mmSPI_GDBG_TMA_LO                                                       0x31d6
+#define mmSPI_GDBG_TMA_HI                                                       0x31d7
+#define mmSPI_GDBG_TRAP_DATA0                                                   0x31d8
+#define mmSPI_GDBG_TRAP_DATA1                                                   0x31d9
+#define mmSPI_RESET_DEBUG                                                       0x31da
+#define mmSPI_COMPUTE_QUEUE_RESET                                               0x31db
+#define mmSPI_RESOURCE_RESERVE_CU_0                                             0x31dc
+#define mmSPI_RESOURCE_RESERVE_CU_1                                             0x31dd
+#define mmSPI_RESOURCE_RESERVE_CU_2                                             0x31de
+#define mmSPI_RESOURCE_RESERVE_CU_3                                             0x31df
+#define mmSPI_RESOURCE_RESERVE_CU_4                                             0x31e0
+#define mmSPI_RESOURCE_RESERVE_CU_5                                             0x31e1
+#define mmSPI_RESOURCE_RESERVE_CU_6                                             0x31e2
+#define mmSPI_RESOURCE_RESERVE_CU_7                                             0x31e3
+#define mmSPI_RESOURCE_RESERVE_CU_8                                             0x31e4
+#define mmSPI_RESOURCE_RESERVE_CU_9                                             0x31e5
+#define mmSPI_RESOURCE_RESERVE_CU_10                                            0x31f0
+#define mmSPI_RESOURCE_RESERVE_CU_11                                            0x31f1
+#define mmSPI_RESOURCE_RESERVE_CU_12                                            0x31f4
+#define mmSPI_RESOURCE_RESERVE_CU_13                                            0x31f5
+#define mmSPI_RESOURCE_RESERVE_CU_14                                            0x31f6
+#define mmSPI_RESOURCE_RESERVE_CU_15                                            0x31f7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_0                                          0x31e6
+#define mmSPI_RESOURCE_RESERVE_EN_CU_1                                          0x31e7
+#define mmSPI_RESOURCE_RESERVE_EN_CU_2                                          0x31e8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_3                                          0x31e9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_4                                          0x31ea
+#define mmSPI_RESOURCE_RESERVE_EN_CU_5                                          0x31eb
+#define mmSPI_RESOURCE_RESERVE_EN_CU_6                                          0x31ec
+#define mmSPI_RESOURCE_RESERVE_EN_CU_7                                          0x31ed
+#define mmSPI_RESOURCE_RESERVE_EN_CU_8                                          0x31ee
+#define mmSPI_RESOURCE_RESERVE_EN_CU_9                                          0x31ef
+#define mmSPI_RESOURCE_RESERVE_EN_CU_10                                         0x31f2
+#define mmSPI_RESOURCE_RESERVE_EN_CU_11                                         0x31f3
+#define mmSPI_RESOURCE_RESERVE_EN_CU_12                                         0x31f8
+#define mmSPI_RESOURCE_RESERVE_EN_CU_13                                         0x31f9
+#define mmSPI_RESOURCE_RESERVE_EN_CU_14                                         0x31fa
+#define mmSPI_RESOURCE_RESERVE_EN_CU_15                                         0x31fb
+#define mmSPI_COMPUTE_WF_CTX_SAVE                                               0x31fc
+#define mmSPI_PS_MAX_WAVE_ID                                                    0x243a
+#define mmSPI_START_PHASE                                                       0x243b
+#define mmSPI_GFX_CNTL                                                          0x243c
+#define mmSPI_CONFIG_CNTL                                                       0x2440
+#define mmSPI_DEBUG_CNTL                                                        0x2441
+#define mmSPI_DEBUG_READ                                                        0x2442
+#define mmSPI_DSM_CNTL                                                          0x2443
+#define mmSPI_EDC_CNT                                                           0x2444
+#define mmSPI_PERFCOUNTER0_SELECT                                               0xd980
+#define mmSPI_PERFCOUNTER1_SELECT                                               0xd981
+#define mmSPI_PERFCOUNTER2_SELECT                                               0xd982
+#define mmSPI_PERFCOUNTER3_SELECT                                               0xd983
+#define mmSPI_PERFCOUNTER0_SELECT1                                              0xd984
+#define mmSPI_PERFCOUNTER1_SELECT1                                              0xd985
+#define mmSPI_PERFCOUNTER2_SELECT1                                              0xd986
+#define mmSPI_PERFCOUNTER3_SELECT1                                              0xd987
+#define mmSPI_PERFCOUNTER4_SELECT                                               0xd988
+#define mmSPI_PERFCOUNTER5_SELECT                                               0xd989
+#define mmSPI_PERFCOUNTER_BINS                                                  0xd98a
+#define mmSPI_PERFCOUNTER0_HI                                                   0xd180
+#define mmSPI_PERFCOUNTER0_LO                                                   0xd181
+#define mmSPI_PERFCOUNTER1_HI                                                   0xd182
+#define mmSPI_PERFCOUNTER1_LO                                                   0xd183
+#define mmSPI_PERFCOUNTER2_HI                                                   0xd184
+#define mmSPI_PERFCOUNTER2_LO                                                   0xd185
+#define mmSPI_PERFCOUNTER3_HI                                                   0xd186
+#define mmSPI_PERFCOUNTER3_LO                                                   0xd187
+#define mmSPI_PERFCOUNTER4_HI                                                   0xd188
+#define mmSPI_PERFCOUNTER4_LO                                                   0xd189
+#define mmSPI_PERFCOUNTER5_HI                                                   0xd18a
+#define mmSPI_PERFCOUNTER5_LO                                                   0xd18b
+#define mmSPI_CONFIG_CNTL_1                                                     0x244f
+#define mmSPI_DEBUG_BUSY                                                        0x2450
+#define mmSPI_CONFIG_CNTL_2                                                     0x2451
+#define mmCGTS_SM_CTRL_REG                                                      0xf000
+#define mmCGTS_RD_CTRL_REG                                                      0xf001
+#define mmCGTS_RD_REG                                                           0xf002
+#define mmCGTS_TCC_DISABLE                                                      0xf003
+#define mmCGTS_USER_TCC_DISABLE                                                 0xf004
+#define mmCGTS_CU0_SP0_CTRL_REG                                                 0xf008
+#define mmCGTS_CU0_LDS_SQ_CTRL_REG                                              0xf009
+#define mmCGTS_CU0_TA_SQC_CTRL_REG                                              0xf00a
+#define mmCGTS_CU0_SP1_CTRL_REG                                                 0xf00b
+#define mmCGTS_CU0_TD_TCP_CTRL_REG                                              0xf00c
+#define mmCGTS_CU1_SP0_CTRL_REG                                                 0xf00d
+#define mmCGTS_CU1_LDS_SQ_CTRL_REG                                              0xf00e
+#define mmCGTS_CU1_TA_CTRL_REG                                                  0xf00f
+#define mmCGTS_CU1_SP1_CTRL_REG                                                 0xf010
+#define mmCGTS_CU1_TD_TCP_CTRL_REG                                              0xf011
+#define mmCGTS_CU2_SP0_CTRL_REG                                                 0xf012
+#define mmCGTS_CU2_LDS_SQ_CTRL_REG                                              0xf013
+#define mmCGTS_CU2_TA_CTRL_REG                                                  0xf014
+#define mmCGTS_CU2_SP1_CTRL_REG                                                 0xf015
+#define mmCGTS_CU2_TD_TCP_CTRL_REG                                              0xf016
+#define mmCGTS_CU3_SP0_CTRL_REG                                                 0xf017
+#define mmCGTS_CU3_LDS_SQ_CTRL_REG                                              0xf018
+#define mmCGTS_CU3_TA_CTRL_REG                                                  0xf019
+#define mmCGTS_CU3_SP1_CTRL_REG                                                 0xf01a
+#define mmCGTS_CU3_TD_TCP_CTRL_REG                                              0xf01b
+#define mmCGTS_CU4_SP0_CTRL_REG                                                 0xf01c
+#define mmCGTS_CU4_LDS_SQ_CTRL_REG                                              0xf01d
+#define mmCGTS_CU4_TA_SQC_CTRL_REG                                              0xf01e
+#define mmCGTS_CU4_SP1_CTRL_REG                                                 0xf01f
+#define mmCGTS_CU4_TD_TCP_CTRL_REG                                              0xf020
+#define mmCGTS_CU5_SP0_CTRL_REG                                                 0xf021
+#define mmCGTS_CU5_LDS_SQ_CTRL_REG                                              0xf022
+#define mmCGTS_CU5_TA_CTRL_REG                                                  0xf023
+#define mmCGTS_CU5_SP1_CTRL_REG                                                 0xf024
+#define mmCGTS_CU5_TD_TCP_CTRL_REG                                              0xf025
+#define mmCGTS_CU6_SP0_CTRL_REG                                                 0xf026
+#define mmCGTS_CU6_LDS_SQ_CTRL_REG                                              0xf027
+#define mmCGTS_CU6_TA_CTRL_REG                                                  0xf028
+#define mmCGTS_CU6_SP1_CTRL_REG                                                 0xf029
+#define mmCGTS_CU6_TD_TCP_CTRL_REG                                              0xf02a
+#define mmCGTS_CU7_SP0_CTRL_REG                                                 0xf02b
+#define mmCGTS_CU7_LDS_SQ_CTRL_REG                                              0xf02c
+#define mmCGTS_CU7_TA_CTRL_REG                                                  0xf02d
+#define mmCGTS_CU7_SP1_CTRL_REG                                                 0xf02e
+#define mmCGTS_CU7_TD_TCP_CTRL_REG                                              0xf02f
+#define mmCGTS_CU8_SP0_CTRL_REG                                                 0xf030
+#define mmCGTS_CU8_LDS_SQ_CTRL_REG                                              0xf031
+#define mmCGTS_CU8_TA_SQC_CTRL_REG                                              0xf032
+#define mmCGTS_CU8_SP1_CTRL_REG                                                 0xf033
+#define mmCGTS_CU8_TD_TCP_CTRL_REG                                              0xf034
+#define mmCGTS_CU9_SP0_CTRL_REG                                                 0xf035
+#define mmCGTS_CU9_LDS_SQ_CTRL_REG                                              0xf036
+#define mmCGTS_CU9_TA_CTRL_REG                                                  0xf037
+#define mmCGTS_CU9_SP1_CTRL_REG                                                 0xf038
+#define mmCGTS_CU9_TD_TCP_CTRL_REG                                              0xf039
+#define mmCGTS_CU10_SP0_CTRL_REG                                                0xf03a
+#define mmCGTS_CU10_LDS_SQ_CTRL_REG                                             0xf03b
+#define mmCGTS_CU10_TA_CTRL_REG                                                 0xf03c
+#define mmCGTS_CU10_SP1_CTRL_REG                                                0xf03d
+#define mmCGTS_CU10_TD_TCP_CTRL_REG                                             0xf03e
+#define mmCGTS_CU11_SP0_CTRL_REG                                                0xf03f
+#define mmCGTS_CU11_LDS_SQ_CTRL_REG                                             0xf040
+#define mmCGTS_CU11_TA_CTRL_REG                                                 0xf041
+#define mmCGTS_CU11_SP1_CTRL_REG                                                0xf042
+#define mmCGTS_CU11_TD_TCP_CTRL_REG                                             0xf043
+#define mmCGTS_CU12_SP0_CTRL_REG                                                0xf044
+#define mmCGTS_CU12_LDS_SQ_CTRL_REG                                             0xf045
+#define mmCGTS_CU12_TA_SQC_CTRL_REG                                             0xf046
+#define mmCGTS_CU12_SP1_CTRL_REG                                                0xf047
+#define mmCGTS_CU12_TD_TCP_CTRL_REG                                             0xf048
+#define mmCGTS_CU13_SP0_CTRL_REG                                                0xf049
+#define mmCGTS_CU13_LDS_SQ_CTRL_REG                                             0xf04a
+#define mmCGTS_CU13_TA_CTRL_REG                                                 0xf04b
+#define mmCGTS_CU13_SP1_CTRL_REG                                                0xf04c
+#define mmCGTS_CU13_TD_TCP_CTRL_REG                                             0xf04d
+#define mmCGTS_CU14_SP0_CTRL_REG                                                0xf04e
+#define mmCGTS_CU14_LDS_SQ_CTRL_REG                                             0xf04f
+#define mmCGTS_CU14_TA_CTRL_REG                                                 0xf050
+#define mmCGTS_CU14_SP1_CTRL_REG                                                0xf051
+#define mmCGTS_CU14_TD_TCP_CTRL_REG                                             0xf052
+#define mmCGTS_CU15_SP0_CTRL_REG                                                0xf053
+#define mmCGTS_CU15_LDS_SQ_CTRL_REG                                             0xf054
+#define mmCGTS_CU15_TA_CTRL_REG                                                 0xf055
+#define mmCGTS_CU15_SP1_CTRL_REG                                                0xf056
+#define mmCGTS_CU15_TD_TCP_CTRL_REG                                             0xf057
+#define mmCGTT_SPI_CLK_CTRL                                                     0xf080
+#define mmCGTT_PC_CLK_CTRL                                                      0xf081
+#define mmCGTT_BCI_CLK_CTRL                                                     0xf082
+#define mmSPI_WF_LIFETIME_CNTL                                                  0x24aa
+#define mmSPI_WF_LIFETIME_LIMIT_0                                               0x24ab
+#define mmSPI_WF_LIFETIME_LIMIT_1                                               0x24ac
+#define mmSPI_WF_LIFETIME_LIMIT_2                                               0x24ad
+#define mmSPI_WF_LIFETIME_LIMIT_3                                               0x24ae
+#define mmSPI_WF_LIFETIME_LIMIT_4                                               0x24af
+#define mmSPI_WF_LIFETIME_LIMIT_5                                               0x24b0
+#define mmSPI_WF_LIFETIME_LIMIT_6                                               0x24b1
+#define mmSPI_WF_LIFETIME_LIMIT_7                                               0x24b2
+#define mmSPI_WF_LIFETIME_LIMIT_8                                               0x24b3
+#define mmSPI_WF_LIFETIME_LIMIT_9                                               0x24b4
+#define mmSPI_WF_LIFETIME_STATUS_0                                              0x24b5
+#define mmSPI_WF_LIFETIME_STATUS_1                                              0x24b6
+#define mmSPI_WF_LIFETIME_STATUS_2                                              0x24b7
+#define mmSPI_WF_LIFETIME_STATUS_3                                              0x24b8
+#define mmSPI_WF_LIFETIME_STATUS_4                                              0x24b9
+#define mmSPI_WF_LIFETIME_STATUS_5                                              0x24ba
+#define mmSPI_WF_LIFETIME_STATUS_6                                              0x24bb
+#define mmSPI_WF_LIFETIME_STATUS_7                                              0x24bc
+#define mmSPI_WF_LIFETIME_STATUS_8                                              0x24bd
+#define mmSPI_WF_LIFETIME_STATUS_9                                              0x24be
+#define mmSPI_WF_LIFETIME_STATUS_10                                             0x24bf
+#define mmSPI_WF_LIFETIME_STATUS_11                                             0x24c0
+#define mmSPI_WF_LIFETIME_STATUS_12                                             0x24c1
+#define mmSPI_WF_LIFETIME_STATUS_13                                             0x24c2
+#define mmSPI_WF_LIFETIME_STATUS_14                                             0x24c3
+#define mmSPI_WF_LIFETIME_STATUS_15                                             0x24c4
+#define mmSPI_WF_LIFETIME_STATUS_16                                             0x24c5
+#define mmSPI_WF_LIFETIME_STATUS_17                                             0x24c6
+#define mmSPI_WF_LIFETIME_STATUS_18                                             0x24c7
+#define mmSPI_WF_LIFETIME_STATUS_19                                             0x24c8
+#define mmSPI_WF_LIFETIME_STATUS_20                                             0x24c9
+#define mmSPI_WF_LIFETIME_DEBUG                                                 0x24ca
+#define mmSPI_SLAVE_DEBUG_BUSY                                                  0x24d3
+#define mmSPI_LB_CTR_CTRL                                                       0x24d4
+#define mmSPI_LB_CU_MASK                                                        0x24d5
+#define mmSPI_LB_DATA_REG                                                       0x24d6
+#define mmSPI_PG_ENABLE_STATIC_CU_MASK                                          0x24d7
+#define mmSPI_GDS_CREDITS                                                       0x24d8
+#define mmSPI_SX_EXPORT_BUFFER_SIZES                                            0x24d9
+#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                                        0x24da
+#define mmSPI_CSQ_WF_ACTIVE_STATUS                                              0x24db
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_0                                             0x24dc
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_1                                             0x24dd
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_2                                             0x24de
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_3                                             0x24df
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_4                                             0x24e0
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_5                                             0x24e1
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_6                                             0x24e2
+#define mmSPI_CSQ_WF_ACTIVE_COUNT_7                                             0x24e3
+#define mmBCI_DEBUG_READ                                                        0x24eb
+#define mmSPI_P0_TRAP_SCREEN_PSBA_LO                                            0x24ec
+#define mmSPI_P0_TRAP_SCREEN_PSBA_HI                                            0x24ed
+#define mmSPI_P0_TRAP_SCREEN_PSMA_LO                                            0x24ee
+#define mmSPI_P0_TRAP_SCREEN_PSMA_HI                                            0x24ef
+#define mmSPI_P0_TRAP_SCREEN_GPR_MIN                                            0x24f0
+#define mmSPI_P1_TRAP_SCREEN_PSBA_LO                                            0x24f1
+#define mmSPI_P1_TRAP_SCREEN_PSBA_HI                                            0x24f2
+#define mmSPI_P1_TRAP_SCREEN_PSMA_LO                                            0x24f3
+#define mmSPI_P1_TRAP_SCREEN_PSMA_HI                                            0x24f4
+#define mmSPI_P1_TRAP_SCREEN_GPR_MIN                                            0x24f5
+#define mmSPI_SHADER_TBA_LO_PS                                                  0x2c00
+#define mmSPI_SHADER_TBA_HI_PS                                                  0x2c01
+#define mmSPI_SHADER_TMA_LO_PS                                                  0x2c02
+#define mmSPI_SHADER_TMA_HI_PS                                                  0x2c03
+#define mmSPI_SHADER_PGM_LO_PS                                                  0x2c08
+#define mmSPI_SHADER_PGM_HI_PS                                                  0x2c09
+#define mmSPI_SHADER_PGM_RSRC1_PS                                               0x2c0a
+#define mmSPI_SHADER_PGM_RSRC2_PS                                               0x2c0b
+#define mmSPI_SHADER_PGM_RSRC3_PS                                               0x2c07
+#define mmSPI_SHADER_USER_DATA_PS_0                                             0x2c0c
+#define mmSPI_SHADER_USER_DATA_PS_1                                             0x2c0d
+#define mmSPI_SHADER_USER_DATA_PS_2                                             0x2c0e
+#define mmSPI_SHADER_USER_DATA_PS_3                                             0x2c0f
+#define mmSPI_SHADER_USER_DATA_PS_4                                             0x2c10
+#define mmSPI_SHADER_USER_DATA_PS_5                                             0x2c11
+#define mmSPI_SHADER_USER_DATA_PS_6                                             0x2c12
+#define mmSPI_SHADER_USER_DATA_PS_7                                             0x2c13
+#define mmSPI_SHADER_USER_DATA_PS_8                                             0x2c14
+#define mmSPI_SHADER_USER_DATA_PS_9                                             0x2c15
+#define mmSPI_SHADER_USER_DATA_PS_10                                            0x2c16
+#define mmSPI_SHADER_USER_DATA_PS_11                                            0x2c17
+#define mmSPI_SHADER_USER_DATA_PS_12                                            0x2c18
+#define mmSPI_SHADER_USER_DATA_PS_13                                            0x2c19
+#define mmSPI_SHADER_USER_DATA_PS_14                                            0x2c1a
+#define mmSPI_SHADER_USER_DATA_PS_15                                            0x2c1b
+#define mmSPI_SHADER_TBA_LO_VS                                                  0x2c40
+#define mmSPI_SHADER_TBA_HI_VS                                                  0x2c41
+#define mmSPI_SHADER_TMA_LO_VS                                                  0x2c42
+#define mmSPI_SHADER_TMA_HI_VS                                                  0x2c43
+#define mmSPI_SHADER_PGM_LO_VS                                                  0x2c48
+#define mmSPI_SHADER_PGM_HI_VS                                                  0x2c49
+#define mmSPI_SHADER_PGM_RSRC1_VS                                               0x2c4a
+#define mmSPI_SHADER_PGM_RSRC2_VS                                               0x2c4b
+#define mmSPI_SHADER_PGM_RSRC3_VS                                               0x2c46
+#define mmSPI_SHADER_LATE_ALLOC_VS                                              0x2c47
+#define mmSPI_SHADER_USER_DATA_VS_0                                             0x2c4c
+#define mmSPI_SHADER_USER_DATA_VS_1                                             0x2c4d
+#define mmSPI_SHADER_USER_DATA_VS_2                                             0x2c4e
+#define mmSPI_SHADER_USER_DATA_VS_3                                             0x2c4f
+#define mmSPI_SHADER_USER_DATA_VS_4                                             0x2c50
+#define mmSPI_SHADER_USER_DATA_VS_5                                             0x2c51
+#define mmSPI_SHADER_USER_DATA_VS_6                                             0x2c52
+#define mmSPI_SHADER_USER_DATA_VS_7                                             0x2c53
+#define mmSPI_SHADER_USER_DATA_VS_8                                             0x2c54
+#define mmSPI_SHADER_USER_DATA_VS_9                                             0x2c55
+#define mmSPI_SHADER_USER_DATA_VS_10                                            0x2c56
+#define mmSPI_SHADER_USER_DATA_VS_11                                            0x2c57
+#define mmSPI_SHADER_USER_DATA_VS_12                                            0x2c58
+#define mmSPI_SHADER_USER_DATA_VS_13                                            0x2c59
+#define mmSPI_SHADER_USER_DATA_VS_14                                            0x2c5a
+#define mmSPI_SHADER_USER_DATA_VS_15                                            0x2c5b
+#define mmSPI_SHADER_PGM_RSRC2_ES_VS                                            0x2c7c
+#define mmSPI_SHADER_PGM_RSRC2_LS_VS                                            0x2c7d
+#define mmSPI_SHADER_TBA_LO_GS                                                  0x2c80
+#define mmSPI_SHADER_TBA_HI_GS                                                  0x2c81
+#define mmSPI_SHADER_TMA_LO_GS                                                  0x2c82
+#define mmSPI_SHADER_TMA_HI_GS                                                  0x2c83
+#define mmSPI_SHADER_PGM_LO_GS                                                  0x2c88
+#define mmSPI_SHADER_PGM_HI_GS                                                  0x2c89
+#define mmSPI_SHADER_PGM_RSRC1_GS                                               0x2c8a
+#define mmSPI_SHADER_PGM_RSRC2_GS                                               0x2c8b
+#define mmSPI_SHADER_PGM_RSRC3_GS                                               0x2c87
+#define mmSPI_SHADER_USER_DATA_GS_0                                             0x2c8c
+#define mmSPI_SHADER_USER_DATA_GS_1                                             0x2c8d
+#define mmSPI_SHADER_USER_DATA_GS_2                                             0x2c8e
+#define mmSPI_SHADER_USER_DATA_GS_3                                             0x2c8f
+#define mmSPI_SHADER_USER_DATA_GS_4                                             0x2c90
+#define mmSPI_SHADER_USER_DATA_GS_5                                             0x2c91
+#define mmSPI_SHADER_USER_DATA_GS_6                                             0x2c92
+#define mmSPI_SHADER_USER_DATA_GS_7                                             0x2c93
+#define mmSPI_SHADER_USER_DATA_GS_8                                             0x2c94
+#define mmSPI_SHADER_USER_DATA_GS_9                                             0x2c95
+#define mmSPI_SHADER_USER_DATA_GS_10                                            0x2c96
+#define mmSPI_SHADER_USER_DATA_GS_11                                            0x2c97
+#define mmSPI_SHADER_USER_DATA_GS_12                                            0x2c98
+#define mmSPI_SHADER_USER_DATA_GS_13                                            0x2c99
+#define mmSPI_SHADER_USER_DATA_GS_14                                            0x2c9a
+#define mmSPI_SHADER_USER_DATA_GS_15                                            0x2c9b
+#define mmSPI_SHADER_PGM_RSRC2_ES_GS                                            0x2cbc
+#define mmSPI_SHADER_TBA_LO_ES                                                  0x2cc0
+#define mmSPI_SHADER_TBA_HI_ES                                                  0x2cc1
+#define mmSPI_SHADER_TMA_LO_ES                                                  0x2cc2
+#define mmSPI_SHADER_TMA_HI_ES                                                  0x2cc3
+#define mmSPI_SHADER_PGM_LO_ES                                                  0x2cc8
+#define mmSPI_SHADER_PGM_HI_ES                                                  0x2cc9
+#define mmSPI_SHADER_PGM_RSRC1_ES                                               0x2cca
+#define mmSPI_SHADER_PGM_RSRC2_ES                                               0x2ccb
+#define mmSPI_SHADER_PGM_RSRC3_ES                                               0x2cc7
+#define mmSPI_SHADER_USER_DATA_ES_0                                             0x2ccc
+#define mmSPI_SHADER_USER_DATA_ES_1                                             0x2ccd
+#define mmSPI_SHADER_USER_DATA_ES_2                                             0x2cce
+#define mmSPI_SHADER_USER_DATA_ES_3                                             0x2ccf
+#define mmSPI_SHADER_USER_DATA_ES_4                                             0x2cd0
+#define mmSPI_SHADER_USER_DATA_ES_5                                             0x2cd1
+#define mmSPI_SHADER_USER_DATA_ES_6                                             0x2cd2
+#define mmSPI_SHADER_USER_DATA_ES_7                                             0x2cd3
+#define mmSPI_SHADER_USER_DATA_ES_8                                             0x2cd4
+#define mmSPI_SHADER_USER_DATA_ES_9                                             0x2cd5
+#define mmSPI_SHADER_USER_DATA_ES_10                                            0x2cd6
+#define mmSPI_SHADER_USER_DATA_ES_11                                            0x2cd7
+#define mmSPI_SHADER_USER_DATA_ES_12                                            0x2cd8
+#define mmSPI_SHADER_USER_DATA_ES_13                                            0x2cd9
+#define mmSPI_SHADER_USER_DATA_ES_14                                            0x2cda
+#define mmSPI_SHADER_USER_DATA_ES_15                                            0x2cdb
+#define mmSPI_SHADER_PGM_RSRC2_LS_ES                                            0x2cfd
+#define mmSPI_SHADER_TBA_LO_HS                                                  0x2d00
+#define mmSPI_SHADER_TBA_HI_HS                                                  0x2d01
+#define mmSPI_SHADER_TMA_LO_HS                                                  0x2d02
+#define mmSPI_SHADER_TMA_HI_HS                                                  0x2d03
+#define mmSPI_SHADER_PGM_LO_HS                                                  0x2d08
+#define mmSPI_SHADER_PGM_HI_HS                                                  0x2d09
+#define mmSPI_SHADER_PGM_RSRC1_HS                                               0x2d0a
+#define mmSPI_SHADER_PGM_RSRC2_HS                                               0x2d0b
+#define mmSPI_SHADER_PGM_RSRC3_HS                                               0x2d07
+#define mmSPI_SHADER_USER_DATA_HS_0                                             0x2d0c
+#define mmSPI_SHADER_USER_DATA_HS_1                                             0x2d0d
+#define mmSPI_SHADER_USER_DATA_HS_2                                             0x2d0e
+#define mmSPI_SHADER_USER_DATA_HS_3                                             0x2d0f
+#define mmSPI_SHADER_USER_DATA_HS_4                                             0x2d10
+#define mmSPI_SHADER_USER_DATA_HS_5                                             0x2d11
+#define mmSPI_SHADER_USER_DATA_HS_6                                             0x2d12
+#define mmSPI_SHADER_USER_DATA_HS_7                                             0x2d13
+#define mmSPI_SHADER_USER_DATA_HS_8                                             0x2d14
+#define mmSPI_SHADER_USER_DATA_HS_9                                             0x2d15
+#define mmSPI_SHADER_USER_DATA_HS_10                                            0x2d16
+#define mmSPI_SHADER_USER_DATA_HS_11                                            0x2d17
+#define mmSPI_SHADER_USER_DATA_HS_12                                            0x2d18
+#define mmSPI_SHADER_USER_DATA_HS_13                                            0x2d19
+#define mmSPI_SHADER_USER_DATA_HS_14                                            0x2d1a
+#define mmSPI_SHADER_USER_DATA_HS_15                                            0x2d1b
+#define mmSPI_SHADER_PGM_RSRC2_LS_HS                                            0x2d3d
+#define mmSPI_SHADER_TBA_LO_LS                                                  0x2d40
+#define mmSPI_SHADER_TBA_HI_LS                                                  0x2d41
+#define mmSPI_SHADER_TMA_LO_LS                                                  0x2d42
+#define mmSPI_SHADER_TMA_HI_LS                                                  0x2d43
+#define mmSPI_SHADER_PGM_LO_LS                                                  0x2d48
+#define mmSPI_SHADER_PGM_HI_LS                                                  0x2d49
+#define mmSPI_SHADER_PGM_RSRC1_LS                                               0x2d4a
+#define mmSPI_SHADER_PGM_RSRC2_LS                                               0x2d4b
+#define mmSPI_SHADER_PGM_RSRC3_LS                                               0x2d47
+#define mmSPI_SHADER_USER_DATA_LS_0                                             0x2d4c
+#define mmSPI_SHADER_USER_DATA_LS_1                                             0x2d4d
+#define mmSPI_SHADER_USER_DATA_LS_2                                             0x2d4e
+#define mmSPI_SHADER_USER_DATA_LS_3                                             0x2d4f
+#define mmSPI_SHADER_USER_DATA_LS_4                                             0x2d50
+#define mmSPI_SHADER_USER_DATA_LS_5                                             0x2d51
+#define mmSPI_SHADER_USER_DATA_LS_6                                             0x2d52
+#define mmSPI_SHADER_USER_DATA_LS_7                                             0x2d53
+#define mmSPI_SHADER_USER_DATA_LS_8                                             0x2d54
+#define mmSPI_SHADER_USER_DATA_LS_9                                             0x2d55
+#define mmSPI_SHADER_USER_DATA_LS_10                                            0x2d56
+#define mmSPI_SHADER_USER_DATA_LS_11                                            0x2d57
+#define mmSPI_SHADER_USER_DATA_LS_12                                            0x2d58
+#define mmSPI_SHADER_USER_DATA_LS_13                                            0x2d59
+#define mmSPI_SHADER_USER_DATA_LS_14                                            0x2d5a
+#define mmSPI_SHADER_USER_DATA_LS_15                                            0x2d5b
+#define mmSQ_CONFIG                                                             0x2300
+#define mmSQC_CONFIG                                                            0x2301
+#define mmSQC_CACHES                                                            0xc348
+#define mmSQC_WRITEBACK                                                         0xc349
+#define mmSQC_DSM_CNTL                                                          0x230f
+#define mmSQ_RANDOM_WAVE_PRI                                                    0x2303
+#define mmSQ_REG_CREDITS                                                        0x2304
+#define mmSQ_FIFO_SIZES                                                         0x2305
+#define mmSQ_DSM_CNTL                                                           0x2306
+#define mmCC_GC_SHADER_RATE_CONFIG                                              0x2312
+#define mmGC_USER_SHADER_RATE_CONFIG                                            0x2313
+#define mmSQ_INTERRUPT_AUTO_MASK                                                0x2314
+#define mmSQ_INTERRUPT_MSG_CTRL                                                 0x2315
+#define mmSQ_PERFCOUNTER_CTRL                                                   0xd9e0
+#define mmSQ_PERFCOUNTER_MASK                                                   0xd9e1
+#define mmSQ_PERFCOUNTER_CTRL2                                                  0xd9e2
+#define mmCC_SQC_BANK_DISABLE                                                   0x2307
+#define mmUSER_SQC_BANK_DISABLE                                                 0x2308
+#define mmSQ_PERFCOUNTER0_LO                                                    0xd1c0
+#define mmSQ_PERFCOUNTER1_LO                                                    0xd1c2
+#define mmSQ_PERFCOUNTER2_LO                                                    0xd1c4
+#define mmSQ_PERFCOUNTER3_LO                                                    0xd1c6
+#define mmSQ_PERFCOUNTER4_LO                                                    0xd1c8
+#define mmSQ_PERFCOUNTER5_LO                                                    0xd1ca
+#define mmSQ_PERFCOUNTER6_LO                                                    0xd1cc
+#define mmSQ_PERFCOUNTER7_LO                                                    0xd1ce
+#define mmSQ_PERFCOUNTER8_LO                                                    0xd1d0
+#define mmSQ_PERFCOUNTER9_LO                                                    0xd1d2
+#define mmSQ_PERFCOUNTER10_LO                                                   0xd1d4
+#define mmSQ_PERFCOUNTER11_LO                                                   0xd1d6
+#define mmSQ_PERFCOUNTER12_LO                                                   0xd1d8
+#define mmSQ_PERFCOUNTER13_LO                                                   0xd1da
+#define mmSQ_PERFCOUNTER14_LO                                                   0xd1dc
+#define mmSQ_PERFCOUNTER15_LO                                                   0xd1de
+#define mmSQ_PERFCOUNTER0_HI                                                    0xd1c1
+#define mmSQ_PERFCOUNTER1_HI                                                    0xd1c3
+#define mmSQ_PERFCOUNTER2_HI                                                    0xd1c5
+#define mmSQ_PERFCOUNTER3_HI                                                    0xd1c7
+#define mmSQ_PERFCOUNTER4_HI                                                    0xd1c9
+#define mmSQ_PERFCOUNTER5_HI                                                    0xd1cb
+#define mmSQ_PERFCOUNTER6_HI                                                    0xd1cd
+#define mmSQ_PERFCOUNTER7_HI                                                    0xd1cf
+#define mmSQ_PERFCOUNTER8_HI                                                    0xd1d1
+#define mmSQ_PERFCOUNTER9_HI                                                    0xd1d3
+#define mmSQ_PERFCOUNTER10_HI                                                   0xd1d5
+#define mmSQ_PERFCOUNTER11_HI                                                   0xd1d7
+#define mmSQ_PERFCOUNTER12_HI                                                   0xd1d9
+#define mmSQ_PERFCOUNTER13_HI                                                   0xd1db
+#define mmSQ_PERFCOUNTER14_HI                                                   0xd1dd
+#define mmSQ_PERFCOUNTER15_HI                                                   0xd1df
+#define mmSQ_PERFCOUNTER0_SELECT                                                0xd9c0
+#define mmSQ_PERFCOUNTER1_SELECT                                                0xd9c1
+#define mmSQ_PERFCOUNTER2_SELECT                                                0xd9c2
+#define mmSQ_PERFCOUNTER3_SELECT                                                0xd9c3
+#define mmSQ_PERFCOUNTER4_SELECT                                                0xd9c4
+#define mmSQ_PERFCOUNTER5_SELECT                                                0xd9c5
+#define mmSQ_PERFCOUNTER6_SELECT                                                0xd9c6
+#define mmSQ_PERFCOUNTER7_SELECT                                                0xd9c7
+#define mmSQ_PERFCOUNTER8_SELECT                                                0xd9c8
+#define mmSQ_PERFCOUNTER9_SELECT                                                0xd9c9
+#define mmSQ_PERFCOUNTER10_SELECT                                               0xd9ca
+#define mmSQ_PERFCOUNTER11_SELECT                                               0xd9cb
+#define mmSQ_PERFCOUNTER12_SELECT                                               0xd9cc
+#define mmSQ_PERFCOUNTER13_SELECT                                               0xd9cd
+#define mmSQ_PERFCOUNTER14_SELECT                                               0xd9ce
+#define mmSQ_PERFCOUNTER15_SELECT                                               0xd9cf
+#define mmCGTT_SQ_CLK_CTRL                                                      0xf08c
+#define mmCGTT_SQG_CLK_CTRL                                                     0xf08d
+#define mmSQ_ALU_CLK_CTRL                                                       0xf08e
+#define mmSQ_TEX_CLK_CTRL                                                       0xf08f
+#define mmSQ_LDS_CLK_CTRL                                                       0xf090
+#define mmSQ_POWER_THROTTLE                                                     0xf091
+#define mmSQ_POWER_THROTTLE2                                                    0xf092
+#define mmSQ_TIME_HI                                                            0x237c
+#define mmSQ_TIME_LO                                                            0x237d
+#define mmSQ_THREAD_TRACE_BASE                                                  0xc330
+#define mmSQ_THREAD_TRACE_BASE2                                                 0xc337
+#define mmSQ_THREAD_TRACE_SIZE                                                  0xc331
+#define mmSQ_THREAD_TRACE_MASK                                                  0xc332
+#define mmSQ_THREAD_TRACE_USERDATA_0                                            0xc340
+#define mmSQ_THREAD_TRACE_USERDATA_1                                            0xc341
+#define mmSQ_THREAD_TRACE_USERDATA_2                                            0xc342
+#define mmSQ_THREAD_TRACE_USERDATA_3                                            0xc343
+#define mmSQ_THREAD_TRACE_MODE                                                  0xc336
+#define mmSQ_THREAD_TRACE_CTRL                                                  0xc335
+#define mmSQ_THREAD_TRACE_TOKEN_MASK                                            0xc333
+#define mmSQ_THREAD_TRACE_TOKEN_MASK2                                           0xc338
+#define mmSQ_THREAD_TRACE_PERF_MASK                                             0xc334
+#define mmSQ_THREAD_TRACE_WPTR                                                  0xc339
+#define mmSQ_THREAD_TRACE_STATUS                                                0xc33a
+#define mmSQ_THREAD_TRACE_CNTR                                                  0x2390
+#define mmSQ_THREAD_TRACE_HIWATER                                               0xc33b
+#define mmSQ_LB_CTR_CTRL                                                        0x2398
+#define mmSQ_LB_DATA_ALU_CYCLES                                                 0x2399
+#define mmSQ_LB_DATA_TEX_CYCLES                                                 0x239a
+#define mmSQ_LB_DATA_ALU_STALLS                                                 0x239b
+#define mmSQ_LB_DATA_TEX_STALLS                                                 0x239c
+#define mmSQC_EDC_CNT                                                           0x23a0
+#define mmSQ_EDC_SEC_CNT                                                        0x23a1
+#define mmSQ_EDC_DED_CNT                                                        0x23a2
+#define mmSQ_EDC_INFO                                                           0x23a3
+#define mmSQ_BUF_RSRC_WORD0                                                     0x23c0
+#define mmSQ_BUF_RSRC_WORD1                                                     0x23c1
+#define mmSQ_BUF_RSRC_WORD2                                                     0x23c2
+#define mmSQ_BUF_RSRC_WORD3                                                     0x23c3
+#define mmSQ_IMG_RSRC_WORD0                                                     0x23c4
+#define mmSQ_IMG_RSRC_WORD1                                                     0x23c5
+#define mmSQ_IMG_RSRC_WORD2                                                     0x23c6
+#define mmSQ_IMG_RSRC_WORD3                                                     0x23c7
+#define mmSQ_IMG_RSRC_WORD4                                                     0x23c8
+#define mmSQ_IMG_RSRC_WORD5                                                     0x23c9
+#define mmSQ_IMG_RSRC_WORD6                                                     0x23ca
+#define mmSQ_IMG_RSRC_WORD7                                                     0x23cb
+#define mmSQ_IMG_SAMP_WORD0                                                     0x23cc
+#define mmSQ_IMG_SAMP_WORD1                                                     0x23cd
+#define mmSQ_IMG_SAMP_WORD2                                                     0x23ce
+#define mmSQ_IMG_SAMP_WORD3                                                     0x23cf
+#define mmSQ_FLAT_SCRATCH_WORD0                                                 0x23d0
+#define mmSQ_FLAT_SCRATCH_WORD1                                                 0x23d1
+#define mmSQ_M0_GPR_IDX_WORD                                                    0x23d2
+#define mmSQ_IND_INDEX                                                          0x2378
+#define mmSQ_CMD                                                                0x237b
+#define mmSQ_IND_DATA                                                           0x2379
+#define mmSQ_REG_TIMESTAMP                                                      0x2374
+#define mmSQ_CMD_TIMESTAMP                                                      0x2375
+#define mmSQ_HV_VMID_CTRL                                                       0xf840
+#define ixSQ_WAVE_INST_DW0                                                      0x1a
+#define ixSQ_WAVE_INST_DW1                                                      0x1b
+#define ixSQ_WAVE_PC_LO                                                         0x18
+#define ixSQ_WAVE_PC_HI                                                         0x19
+#define ixSQ_WAVE_IB_DBG0                                                       0x1c
+#define ixSQ_WAVE_IB_DBG1                                                       0x1d
+#define ixSQ_WAVE_EXEC_LO                                                       0x27e
+#define ixSQ_WAVE_EXEC_HI                                                       0x27f
+#define ixSQ_WAVE_STATUS                                                        0x12
+#define ixSQ_WAVE_MODE                                                          0x11
+#define ixSQ_WAVE_TRAPSTS                                                       0x13
+#define ixSQ_WAVE_HW_ID                                                         0x14
+#define ixSQ_WAVE_GPR_ALLOC                                                     0x15
+#define ixSQ_WAVE_LDS_ALLOC                                                     0x16
+#define ixSQ_WAVE_IB_STS                                                        0x17
+#define ixSQ_WAVE_M0                                                            0x27c
+#define ixSQ_WAVE_TBA_LO                                                        0x26c
+#define ixSQ_WAVE_TBA_HI                                                        0x26d
+#define ixSQ_WAVE_TMA_LO                                                        0x26e
+#define ixSQ_WAVE_TMA_HI                                                        0x26f
+#define ixSQ_WAVE_TTMP0                                                         0x270
+#define ixSQ_WAVE_TTMP1                                                         0x271
+#define ixSQ_WAVE_TTMP2                                                         0x272
+#define ixSQ_WAVE_TTMP3                                                         0x273
+#define ixSQ_WAVE_TTMP4                                                         0x274
+#define ixSQ_WAVE_TTMP5                                                         0x275
+#define ixSQ_WAVE_TTMP6                                                         0x276
+#define ixSQ_WAVE_TTMP7                                                         0x277
+#define ixSQ_WAVE_TTMP8                                                         0x278
+#define ixSQ_WAVE_TTMP9                                                         0x279
+#define ixSQ_WAVE_TTMP10                                                        0x27a
+#define ixSQ_WAVE_TTMP11                                                        0x27b
+#define mmSQ_DEBUG_STS_GLOBAL                                                   0x2309
+#define mmSQ_DEBUG_STS_GLOBAL2                                                  0x2310
+#define mmSQ_DEBUG_STS_GLOBAL3                                                  0x2311
+#define ixSQ_DEBUG_STS_LOCAL                                                    0x8
+#define ixSQ_DEBUG_CTRL_LOCAL                                                   0x9
+#define mmSH_MEM_BASES                                                          0x230a
+#define mmSH_MEM_APE1_BASE                                                      0x230b
+#define mmSH_MEM_APE1_LIMIT                                                     0x230c
+#define mmSH_MEM_CONFIG                                                         0x230d
+#define mmSQ_THREAD_TRACE_WORD_CMN                                              0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST                                             0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2                                   0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2                                   0x23b1
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2                             0x23b0
+#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2                             0x23b1
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2                                 0x23b0
+#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2                                 0x23b1
+#define mmSQ_THREAD_TRACE_WORD_WAVE                                             0x23b0
+#define mmSQ_THREAD_TRACE_WORD_MISC                                             0x23b0
+#define mmSQ_THREAD_TRACE_WORD_WAVE_START                                       0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2                                       0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2                                       0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2                                    0x23b0
+#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2                                    0x23b0
+#define mmSQ_THREAD_TRACE_WORD_EVENT                                            0x23b0
+#define mmSQ_THREAD_TRACE_WORD_ISSUE                                            0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2                                      0x23b0
+#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2                                      0x23b1
+#define mmSQ_WREXEC_EXEC_LO                                                     0x23b1
+#define mmSQ_WREXEC_EXEC_HI                                                     0x23b1
+#define mmSQC_GATCL1_CNTL                                                       0x23b2
+#define mmSQC_ATC_EDC_GATCL1_CNT                                                0x23b3
+#define ixSQ_INTERRUPT_WORD_CMN                                                 0x20c0
+#define ixSQ_INTERRUPT_WORD_AUTO                                                0x20c0
+#define ixSQ_INTERRUPT_WORD_WAVE                                                0x20c0
+#define mmSQ_SOP2                                                               0x237f
+#define mmSQ_VOP1                                                               0x237f
+#define mmSQ_MTBUF_1                                                            0x237f
+#define mmSQ_EXP_1                                                              0x237f
+#define mmSQ_MUBUF_1                                                            0x237f
+#define mmSQ_SMEM_1                                                             0x237f
+#define mmSQ_INST                                                               0x237f
+#define mmSQ_EXP_0                                                              0x237f
+#define mmSQ_MUBUF_0                                                            0x237f
+#define mmSQ_VOP_SDWA                                                           0x237f
+#define mmSQ_VOP3_0                                                             0x237f
+#define mmSQ_VOP2                                                               0x237f
+#define mmSQ_MTBUF_0                                                            0x237f
+#define mmSQ_SOPP                                                               0x237f
+#define mmSQ_FLAT_0                                                             0x237f
+#define mmSQ_VOP3_0_SDST_ENC                                                    0x237f
+#define mmSQ_MIMG_1                                                             0x237f
+#define mmSQ_SOP1                                                               0x237f
+#define mmSQ_SOPC                                                               0x237f
+#define mmSQ_FLAT_1                                                             0x237f
+#define mmSQ_DS_1                                                               0x237f
+#define mmSQ_VOP3_1                                                             0x237f
+#define mmSQ_SMEM_0                                                             0x237f
+#define mmSQ_MIMG_0                                                             0x237f
+#define mmSQ_SOPK                                                               0x237f
+#define mmSQ_DS_0                                                               0x237f
+#define mmSQ_VOP_DPP                                                            0x237f
+#define mmSQ_VOPC                                                               0x237f
+#define mmSQ_VINTRP                                                             0x237f
+#define mmCGTT_SX_CLK_CTRL0                                                     0xf094
+#define mmCGTT_SX_CLK_CTRL1                                                     0xf095
+#define mmCGTT_SX_CLK_CTRL2                                                     0xf096
+#define mmCGTT_SX_CLK_CTRL3                                                     0xf097
+#define mmCGTT_SX_CLK_CTRL4                                                     0xf098
+#define mmSX_DEBUG_BUSY                                                         0x2414
+#define mmSX_DEBUG_BUSY_2                                                       0x2415
+#define mmSX_DEBUG_BUSY_3                                                       0x2416
+#define mmSX_DEBUG_BUSY_4                                                       0x2417
+#define mmSX_DEBUG_1                                                            0x2418
+#define mmSX_PERFCOUNTER0_SELECT                                                0xda40
+#define mmSX_PERFCOUNTER1_SELECT                                                0xda41
+#define mmSX_PERFCOUNTER2_SELECT                                                0xda42
+#define mmSX_PERFCOUNTER3_SELECT                                                0xda43
+#define mmSX_PERFCOUNTER0_SELECT1                                               0xda44
+#define mmSX_PERFCOUNTER1_SELECT1                                               0xda45
+#define mmSX_PERFCOUNTER0_LO                                                    0xd240
+#define mmSX_PERFCOUNTER0_HI                                                    0xd241
+#define mmSX_PERFCOUNTER1_LO                                                    0xd242
+#define mmSX_PERFCOUNTER1_HI                                                    0xd243
+#define mmSX_PERFCOUNTER2_LO                                                    0xd244
+#define mmSX_PERFCOUNTER2_HI                                                    0xd245
+#define mmSX_PERFCOUNTER3_LO                                                    0xd246
+#define mmSX_PERFCOUNTER3_HI                                                    0xd247
+#define mmTCC_CTRL                                                              0x2b80
+#define mmTCC_EDC_CNT                                                           0x2b82
+#define mmTCC_REDUNDANCY                                                        0x2b83
+#define mmTCC_EXE_DISABLE                                                       0x2b84
+#define mmTCC_DSM_CNTL                                                          0x2b85
+#define mmTCC_CGTT_SCLK_CTRL                                                    0xf0ac
+#define mmTCA_CGTT_SCLK_CTRL                                                    0xf0ad
+#define mmTCC_PERFCOUNTER0_SELECT                                               0xdb80
+#define mmTCC_PERFCOUNTER1_SELECT                                               0xdb82
+#define mmTCC_PERFCOUNTER0_SELECT1                                              0xdb81
+#define mmTCC_PERFCOUNTER1_SELECT1                                              0xdb83
+#define mmTCC_PERFCOUNTER2_SELECT                                               0xdb84
+#define mmTCC_PERFCOUNTER3_SELECT                                               0xdb85
+#define mmTCC_PERFCOUNTER0_LO                                                   0xd380
+#define mmTCC_PERFCOUNTER1_LO                                                   0xd382
+#define mmTCC_PERFCOUNTER2_LO                                                   0xd384
+#define mmTCC_PERFCOUNTER3_LO                                                   0xd386
+#define mmTCC_PERFCOUNTER0_HI                                                   0xd381
+#define mmTCC_PERFCOUNTER1_HI                                                   0xd383
+#define mmTCC_PERFCOUNTER2_HI                                                   0xd385
+#define mmTCC_PERFCOUNTER3_HI                                                   0xd387
+#define mmTCA_CTRL                                                              0x2bc0
+#define mmTCA_PERFCOUNTER0_SELECT                                               0xdb90
+#define mmTCA_PERFCOUNTER1_SELECT                                               0xdb92
+#define mmTCA_PERFCOUNTER0_SELECT1                                              0xdb91
+#define mmTCA_PERFCOUNTER1_SELECT1                                              0xdb93
+#define mmTCA_PERFCOUNTER2_SELECT                                               0xdb94
+#define mmTCA_PERFCOUNTER3_SELECT                                               0xdb95
+#define mmTCA_PERFCOUNTER0_LO                                                   0xd390
+#define mmTCA_PERFCOUNTER1_LO                                                   0xd392
+#define mmTCA_PERFCOUNTER2_LO                                                   0xd394
+#define mmTCA_PERFCOUNTER3_LO                                                   0xd396
+#define mmTCA_PERFCOUNTER0_HI                                                   0xd391
+#define mmTCA_PERFCOUNTER1_HI                                                   0xd393
+#define mmTCA_PERFCOUNTER2_HI                                                   0xd395
+#define mmTCA_PERFCOUNTER3_HI                                                   0xd397
+#define mmTA_BC_BASE_ADDR                                                       0xa020
+#define mmTA_BC_BASE_ADDR_HI                                                    0xa021
+#define mmTD_CNTL                                                               0x2525
+#define mmTD_STATUS                                                             0x2526
+#define mmTD_DEBUG_INDEX                                                        0x2528
+#define mmTD_DEBUG_DATA                                                         0x2529
+#define mmTD_DSM_CNTL                                                           0x252f
+#define mmTD_PERFCOUNTER0_SELECT                                                0xdb00
+#define mmTD_PERFCOUNTER1_SELECT                                                0xdb02
+#define mmTD_PERFCOUNTER0_SELECT1                                               0xdb01
+#define mmTD_PERFCOUNTER0_LO                                                    0xd300
+#define mmTD_PERFCOUNTER1_LO                                                    0xd302
+#define mmTD_PERFCOUNTER0_HI                                                    0xd301
+#define mmTD_PERFCOUNTER1_HI                                                    0xd303
+#define mmTD_SCRATCH                                                            0x2533
+#define mmTA_CNTL                                                               0x2541
+#define mmTA_CNTL_AUX                                                           0x2542
+#define mmTA_RESERVED_010C                                                      0x2543
+#define mmTA_CS_BC_BASE_ADDR                                                    0xc380
+#define mmTA_CS_BC_BASE_ADDR_HI                                                 0xc381
+#define mmTA_STATUS                                                             0x2548
+#define mmTA_DEBUG_INDEX                                                        0x254c
+#define mmTA_DEBUG_DATA                                                         0x254d
+#define mmTA_PERFCOUNTER0_SELECT                                                0xdac0
+#define mmTA_PERFCOUNTER1_SELECT                                                0xdac2
+#define mmTA_PERFCOUNTER0_SELECT1                                               0xdac1
+#define mmTA_PERFCOUNTER0_LO                                                    0xd2c0
+#define mmTA_PERFCOUNTER1_LO                                                    0xd2c2
+#define mmTA_PERFCOUNTER0_HI                                                    0xd2c1
+#define mmTA_PERFCOUNTER1_HI                                                    0xd2c3
+#define mmTA_SCRATCH                                                            0x2564
+#define mmSH_HIDDEN_PRIVATE_BASE_VMID                                           0x2580
+#define mmSH_STATIC_MEM_CONFIG                                                  0x2581
+#define mmTCP_INVALIDATE                                                        0x2b00
+#define mmTCP_STATUS                                                            0x2b01
+#define mmTCP_CNTL                                                              0x2b02
+#define mmTCP_CHAN_STEER_LO                                                     0x2b03
+#define mmTCP_CHAN_STEER_HI                                                     0x2b04
+#define mmTCP_ADDR_CONFIG                                                       0x2b05
+#define mmTCP_CREDIT                                                            0x2b06
+#define mmTCP_PERFCOUNTER0_SELECT                                               0xdb40
+#define mmTCP_PERFCOUNTER1_SELECT                                               0xdb42
+#define mmTCP_PERFCOUNTER0_SELECT1                                              0xdb41
+#define mmTCP_PERFCOUNTER1_SELECT1                                              0xdb43
+#define mmTCP_PERFCOUNTER2_SELECT                                               0xdb44
+#define mmTCP_PERFCOUNTER3_SELECT                                               0xdb45
+#define mmTCP_PERFCOUNTER0_LO                                                   0xd340
+#define mmTCP_PERFCOUNTER1_LO                                                   0xd342
+#define mmTCP_PERFCOUNTER2_LO                                                   0xd344
+#define mmTCP_PERFCOUNTER3_LO                                                   0xd346
+#define mmTCP_PERFCOUNTER0_HI                                                   0xd341
+#define mmTCP_PERFCOUNTER1_HI                                                   0xd343
+#define mmTCP_PERFCOUNTER2_HI                                                   0xd345
+#define mmTCP_PERFCOUNTER3_HI                                                   0xd347
+#define mmTCP_BUFFER_ADDR_HASH_CNTL                                             0x2b16
+#define mmTCP_EDC_CNT                                                           0x2b17
+#define mmTC_CFG_L1_LOAD_POLICY0                                                0x2b1a
+#define mmTC_CFG_L1_LOAD_POLICY1                                                0x2b1b
+#define mmTC_CFG_L1_STORE_POLICY                                                0x2b1c
+#define mmTC_CFG_L2_LOAD_POLICY0                                                0x2b1d
+#define mmTC_CFG_L2_LOAD_POLICY1                                                0x2b1e
+#define mmTC_CFG_L2_STORE_POLICY0                                               0x2b1f
+#define mmTC_CFG_L2_STORE_POLICY1                                               0x2b20
+#define mmTC_CFG_L2_ATOMIC_POLICY                                               0x2b21
+#define mmTC_CFG_L1_VOLATILE                                                    0x2b22
+#define mmTC_CFG_L2_VOLATILE                                                    0x2b23
+#define mmTCP_WATCH0_ADDR_H                                                     0x32a0
+#define mmTCP_WATCH1_ADDR_H                                                     0x32a3
+#define mmTCP_WATCH2_ADDR_H                                                     0x32a6
+#define mmTCP_WATCH3_ADDR_H                                                     0x32a9
+#define mmTCP_WATCH0_ADDR_L                                                     0x32a1
+#define mmTCP_WATCH1_ADDR_L                                                     0x32a4
+#define mmTCP_WATCH2_ADDR_L                                                     0x32a7
+#define mmTCP_WATCH3_ADDR_L                                                     0x32aa
+#define mmTCP_WATCH0_CNTL                                                       0x32a2
+#define mmTCP_WATCH1_CNTL                                                       0x32a5
+#define mmTCP_WATCH2_CNTL                                                       0x32a8
+#define mmTCP_WATCH3_CNTL                                                       0x32ab
+#define mmTCP_GATCL1_CNTL                                                       0x32b0
+#define mmTCP_ATC_EDC_GATCL1_CNT                                                0x32b1
+#define mmTCP_GATCL1_DSM_CNTL                                                   0x32b2
+#define mmTCP_DSM_CNTL                                                          0x32b3
+#define mmTCP_CNTL2                                                             0x32b4
+#define mmTD_CGTT_CTRL                                                          0xf09c
+#define mmTA_CGTT_CTRL                                                          0xf09d
+#define mmCGTT_TCP_CLK_CTRL                                                     0xf09e
+#define mmCGTT_TCI_CLK_CTRL                                                     0xf09f
+#define mmTCI_STATUS                                                            0x2b61
+#define mmTCI_CNTL_1                                                            0x2b62
+#define mmTCI_CNTL_2                                                            0x2b63
+#define mmGDS_CONFIG                                                            0x25c0
+#define mmGDS_CNTL_STATUS                                                       0x25c1
+#define mmGDS_ENHANCE2                                                          0x25c2
+#define mmGDS_PROTECTION_FAULT                                                  0x25c3
+#define mmGDS_VM_PROTECTION_FAULT                                               0x25c4
+#define mmGDS_EDC_CNT                                                           0x25c5
+#define mmGDS_EDC_GRBM_CNT                                                      0x25c6
+#define mmGDS_EDC_OA_DED                                                        0x25c7
+#define mmGDS_DEBUG_CNTL                                                        0x25c8
+#define mmGDS_DEBUG_DATA                                                        0x25c9
+#define mmGDS_DSM_CNTL                                                          0x25ca
+#define mmCGTT_GDS_CLK_CTRL                                                     0xf0a0
+#define mmGDS_RD_ADDR                                                           0xc400
+#define mmGDS_RD_DATA                                                           0xc401
+#define mmGDS_RD_BURST_ADDR                                                     0xc402
+#define mmGDS_RD_BURST_COUNT                                                    0xc403
+#define mmGDS_RD_BURST_DATA                                                     0xc404
+#define mmGDS_WR_ADDR                                                           0xc405
+#define mmGDS_WR_DATA                                                           0xc406
+#define mmGDS_WR_BURST_ADDR                                                     0xc407
+#define mmGDS_WR_BURST_DATA                                                     0xc408
+#define mmGDS_WRITE_COMPLETE                                                    0xc409
+#define mmGDS_ATOM_CNTL                                                         0xc40a
+#define mmGDS_ATOM_COMPLETE                                                     0xc40b
+#define mmGDS_ATOM_BASE                                                         0xc40c
+#define mmGDS_ATOM_SIZE                                                         0xc40d
+#define mmGDS_ATOM_OFFSET0                                                      0xc40e
+#define mmGDS_ATOM_OFFSET1                                                      0xc40f
+#define mmGDS_ATOM_DST                                                          0xc410
+#define mmGDS_ATOM_OP                                                           0xc411
+#define mmGDS_ATOM_SRC0                                                         0xc412
+#define mmGDS_ATOM_SRC0_U                                                       0xc413
+#define mmGDS_ATOM_SRC1                                                         0xc414
+#define mmGDS_ATOM_SRC1_U                                                       0xc415
+#define mmGDS_ATOM_READ0                                                        0xc416
+#define mmGDS_ATOM_READ0_U                                                      0xc417
+#define mmGDS_ATOM_READ1                                                        0xc418
+#define mmGDS_ATOM_READ1_U                                                      0xc419
+#define mmGDS_GWS_RESOURCE_CNTL                                                 0xc41a
+#define mmGDS_GWS_RESOURCE                                                      0xc41b
+#define mmGDS_GWS_RESOURCE_CNT                                                  0xc41c
+#define mmGDS_OA_CNTL                                                           0xc41d
+#define mmGDS_OA_COUNTER                                                        0xc41e
+#define mmGDS_OA_ADDRESS                                                        0xc41f
+#define mmGDS_OA_INCDEC                                                         0xc420
+#define mmGDS_OA_RING_SIZE                                                      0xc421
+#define ixGDS_DEBUG_REG0                                                        0x0
+#define ixGDS_DEBUG_REG1                                                        0x1
+#define ixGDS_DEBUG_REG2                                                        0x2
+#define ixGDS_DEBUG_REG3                                                        0x3
+#define ixGDS_DEBUG_REG4                                                        0x4
+#define ixGDS_DEBUG_REG5                                                        0x5
+#define ixGDS_DEBUG_REG6                                                        0x6
+#define mmGDS_PERFCOUNTER0_SELECT                                               0xda80
+#define mmGDS_PERFCOUNTER1_SELECT                                               0xda81
+#define mmGDS_PERFCOUNTER2_SELECT                                               0xda82
+#define mmGDS_PERFCOUNTER3_SELECT                                               0xda83
+#define mmGDS_PERFCOUNTER0_LO                                                   0xd280
+#define mmGDS_PERFCOUNTER1_LO                                                   0xd282
+#define mmGDS_PERFCOUNTER2_LO                                                   0xd284
+#define mmGDS_PERFCOUNTER3_LO                                                   0xd286
+#define mmGDS_PERFCOUNTER0_HI                                                   0xd281
+#define mmGDS_PERFCOUNTER1_HI                                                   0xd283
+#define mmGDS_PERFCOUNTER2_HI                                                   0xd285
+#define mmGDS_PERFCOUNTER3_HI                                                   0xd287
+#define mmGDS_PERFCOUNTER0_SELECT1                                              0xda84
+#define mmGDS_VMID0_BASE                                                        0x3300
+#define mmGDS_VMID1_BASE                                                        0x3302
+#define mmGDS_VMID2_BASE                                                        0x3304
+#define mmGDS_VMID3_BASE                                                        0x3306
+#define mmGDS_VMID4_BASE                                                        0x3308
+#define mmGDS_VMID5_BASE                                                        0x330a
+#define mmGDS_VMID6_BASE                                                        0x330c
+#define mmGDS_VMID7_BASE                                                        0x330e
+#define mmGDS_VMID8_BASE                                                        0x3310
+#define mmGDS_VMID9_BASE                                                        0x3312
+#define mmGDS_VMID10_BASE                                                       0x3314
+#define mmGDS_VMID11_BASE                                                       0x3316
+#define mmGDS_VMID12_BASE                                                       0x3318
+#define mmGDS_VMID13_BASE                                                       0x331a
+#define mmGDS_VMID14_BASE                                                       0x331c
+#define mmGDS_VMID15_BASE                                                       0x331e
+#define mmGDS_VMID0_SIZE                                                        0x3301
+#define mmGDS_VMID1_SIZE                                                        0x3303
+#define mmGDS_VMID2_SIZE                                                        0x3305
+#define mmGDS_VMID3_SIZE                                                        0x3307
+#define mmGDS_VMID4_SIZE                                                        0x3309
+#define mmGDS_VMID5_SIZE                                                        0x330b
+#define mmGDS_VMID6_SIZE                                                        0x330d
+#define mmGDS_VMID7_SIZE                                                        0x330f
+#define mmGDS_VMID8_SIZE                                                        0x3311
+#define mmGDS_VMID9_SIZE                                                        0x3313
+#define mmGDS_VMID10_SIZE                                                       0x3315
+#define mmGDS_VMID11_SIZE                                                       0x3317
+#define mmGDS_VMID12_SIZE                                                       0x3319
+#define mmGDS_VMID13_SIZE                                                       0x331b
+#define mmGDS_VMID14_SIZE                                                       0x331d
+#define mmGDS_VMID15_SIZE                                                       0x331f
+#define mmGDS_GWS_VMID0                                                         0x3320
+#define mmGDS_GWS_VMID1                                                         0x3321
+#define mmGDS_GWS_VMID2                                                         0x3322
+#define mmGDS_GWS_VMID3                                                         0x3323
+#define mmGDS_GWS_VMID4                                                         0x3324
+#define mmGDS_GWS_VMID5                                                         0x3325
+#define mmGDS_GWS_VMID6                                                         0x3326
+#define mmGDS_GWS_VMID7                                                         0x3327
+#define mmGDS_GWS_VMID8                                                         0x3328
+#define mmGDS_GWS_VMID9                                                         0x3329
+#define mmGDS_GWS_VMID10                                                        0x332a
+#define mmGDS_GWS_VMID11                                                        0x332b
+#define mmGDS_GWS_VMID12                                                        0x332c
+#define mmGDS_GWS_VMID13                                                        0x332d
+#define mmGDS_GWS_VMID14                                                        0x332e
+#define mmGDS_GWS_VMID15                                                        0x332f
+#define mmGDS_OA_VMID0                                                          0x3330
+#define mmGDS_OA_VMID1                                                          0x3331
+#define mmGDS_OA_VMID2                                                          0x3332
+#define mmGDS_OA_VMID3                                                          0x3333
+#define mmGDS_OA_VMID4                                                          0x3334
+#define mmGDS_OA_VMID5                                                          0x3335
+#define mmGDS_OA_VMID6                                                          0x3336
+#define mmGDS_OA_VMID7                                                          0x3337
+#define mmGDS_OA_VMID8                                                          0x3338
+#define mmGDS_OA_VMID9                                                          0x3339
+#define mmGDS_OA_VMID10                                                         0x333a
+#define mmGDS_OA_VMID11                                                         0x333b
+#define mmGDS_OA_VMID12                                                         0x333c
+#define mmGDS_OA_VMID13                                                         0x333d
+#define mmGDS_OA_VMID14                                                         0x333e
+#define mmGDS_OA_VMID15                                                         0x333f
+#define mmGDS_GWS_RESET0                                                        0x3344
+#define mmGDS_GWS_RESET1                                                        0x3345
+#define mmGDS_GWS_RESOURCE_RESET                                                0x3346
+#define mmGDS_COMPUTE_MAX_WAVE_ID                                               0x3348
+#define mmGDS_OA_RESET_MASK                                                     0x3349
+#define mmGDS_OA_RESET                                                          0x334a
+#define mmGDS_ENHANCE                                                           0x334b
+#define mmGDS_OA_CGPG_RESTORE                                                   0x334c
+#define mmGDS_CS_CTXSW_STATUS                                                   0x334d
+#define mmGDS_CS_CTXSW_CNT0                                                     0x334e
+#define mmGDS_CS_CTXSW_CNT1                                                     0x334f
+#define mmGDS_CS_CTXSW_CNT2                                                     0x3350
+#define mmGDS_CS_CTXSW_CNT3                                                     0x3351
+#define mmGDS_GFX_CTXSW_STATUS                                                  0x3352
+#define mmGDS_VS_CTXSW_CNT0                                                     0x3353
+#define mmGDS_VS_CTXSW_CNT1                                                     0x3354
+#define mmGDS_VS_CTXSW_CNT2                                                     0x3355
+#define mmGDS_VS_CTXSW_CNT3                                                     0x3356
+#define mmGDS_PS0_CTXSW_CNT0                                                    0x3357
+#define mmGDS_PS1_CTXSW_CNT0                                                    0x335b
+#define mmGDS_PS2_CTXSW_CNT0                                                    0x335f
+#define mmGDS_PS3_CTXSW_CNT0                                                    0x3363
+#define mmGDS_PS4_CTXSW_CNT0                                                    0x3367
+#define mmGDS_PS5_CTXSW_CNT0                                                    0x336b
+#define mmGDS_PS6_CTXSW_CNT0                                                    0x336f
+#define mmGDS_PS7_CTXSW_CNT0                                                    0x3373
+#define mmGDS_PS0_CTXSW_CNT1                                                    0x3358
+#define mmGDS_PS1_CTXSW_CNT1                                                    0x335c
+#define mmGDS_PS2_CTXSW_CNT1                                                    0x3360
+#define mmGDS_PS3_CTXSW_CNT1                                                    0x3364
+#define mmGDS_PS4_CTXSW_CNT1                                                    0x3368
+#define mmGDS_PS5_CTXSW_CNT1                                                    0x336c
+#define mmGDS_PS6_CTXSW_CNT1                                                    0x3370
+#define mmGDS_PS7_CTXSW_CNT1                                                    0x3374
+#define mmGDS_PS0_CTXSW_CNT2                                                    0x3359
+#define mmGDS_PS1_CTXSW_CNT2                                                    0x335d
+#define mmGDS_PS2_CTXSW_CNT2                                                    0x3361
+#define mmGDS_PS3_CTXSW_CNT2                                                    0x3365
+#define mmGDS_PS4_CTXSW_CNT2                                                    0x3369
+#define mmGDS_PS5_CTXSW_CNT2                                                    0x336d
+#define mmGDS_PS6_CTXSW_CNT2                                                    0x3371
+#define mmGDS_PS7_CTXSW_CNT2                                                    0x3375
+#define mmGDS_PS0_CTXSW_CNT3                                                    0x335a
+#define mmGDS_PS1_CTXSW_CNT3                                                    0x335e
+#define mmGDS_PS2_CTXSW_CNT3                                                    0x3362
+#define mmGDS_PS3_CTXSW_CNT3                                                    0x3366
+#define mmGDS_PS4_CTXSW_CNT3                                                    0x336a
+#define mmGDS_PS5_CTXSW_CNT3                                                    0x336e
+#define mmGDS_PS6_CTXSW_CNT3                                                    0x3372
+#define mmGDS_PS7_CTXSW_CNT3                                                    0x3376
+#define mmCS_COPY_STATE                                                         0xa1f3
+#define mmGFX_COPY_STATE                                                        0xa1f4
+#define mmVGT_DRAW_INITIATOR                                                    0xa1fc
+#define mmVGT_EVENT_INITIATOR                                                   0xa2a4
+#define mmVGT_EVENT_ADDRESS_REG                                                 0xa1fe
+#define mmVGT_DMA_BASE_HI                                                       0xa1f9
+#define mmVGT_DMA_BASE                                                          0xa1fa
+#define mmVGT_DMA_INDEX_TYPE                                                    0xa29f
+#define mmVGT_DMA_NUM_INSTANCES                                                 0xa2a2
+#define mmIA_ENHANCE                                                            0xa29c
+#define mmVGT_DMA_SIZE                                                          0xa29d
+#define mmVGT_DMA_MAX_SIZE                                                      0xa29e
+#define mmVGT_DMA_PRIMITIVE_TYPE                                                0x2271
+#define mmVGT_DMA_CONTROL                                                       0x2272
+#define mmVGT_IMMED_DATA                                                        0xa1fd
+#define mmVGT_INDEX_TYPE                                                        0xc243
+#define mmVGT_NUM_INDICES                                                       0xc24c
+#define mmVGT_NUM_INSTANCES                                                     0xc24d
+#define mmVGT_PRIMITIVE_TYPE                                                    0xc242
+#define mmVGT_PRIMITIVEID_EN                                                    0xa2a1
+#define mmVGT_PRIMITIVEID_RESET                                                 0xa2a3
+#define mmVGT_VTX_CNT_EN                                                        0xa2ae
+#define mmVGT_REUSE_OFF                                                         0xa2ad
+#define mmVGT_INSTANCE_STEP_RATE_0                                              0xa2a8
+#define mmVGT_INSTANCE_STEP_RATE_1                                              0xa2a9
+#define mmVGT_MAX_VTX_INDX                                                      0xa100
+#define mmVGT_MIN_VTX_INDX                                                      0xa101
+#define mmVGT_INDX_OFFSET                                                       0xa102
+#define mmVGT_VERTEX_REUSE_BLOCK_CNTL                                           0xa316
+#define mmVGT_OUT_DEALLOC_CNTL                                                  0xa317
+#define mmVGT_MULTI_PRIM_IB_RESET_INDX                                          0xa103
+#define mmVGT_MULTI_PRIM_IB_RESET_EN                                            0xa2a5
+#define mmVGT_ENHANCE                                                           0xa294
+#define mmVGT_OUTPUT_PATH_CNTL                                                  0xa284
+#define mmVGT_HOS_CNTL                                                          0xa285
+#define mmVGT_HOS_MAX_TESS_LEVEL                                                0xa286
+#define mmVGT_HOS_MIN_TESS_LEVEL                                                0xa287
+#define mmVGT_HOS_REUSE_DEPTH                                                   0xa288
+#define mmVGT_GROUP_PRIM_TYPE                                                   0xa289
+#define mmVGT_GROUP_FIRST_DECR                                                  0xa28a
+#define mmVGT_GROUP_DECR                                                        0xa28b
+#define mmVGT_GROUP_VECT_0_CNTL                                                 0xa28c
+#define mmVGT_GROUP_VECT_1_CNTL                                                 0xa28d
+#define mmVGT_GROUP_VECT_0_FMT_CNTL                                             0xa28e
+#define mmVGT_GROUP_VECT_1_FMT_CNTL                                             0xa28f
+#define mmVGT_VTX_VECT_EJECT_REG                                                0x222c
+#define mmVGT_DMA_DATA_FIFO_DEPTH                                               0x222d
+#define mmVGT_DMA_REQ_FIFO_DEPTH                                                0x222e
+#define mmVGT_DRAW_INIT_FIFO_DEPTH                                              0x222f
+#define mmVGT_LAST_COPY_STATE                                                   0x2230
+#define mmCC_GC_SHADER_ARRAY_CONFIG                                             0x226f
+#define mmGC_USER_SHADER_ARRAY_CONFIG                                           0x2270
+#define mmVGT_GS_MODE                                                           0xa290
+#define mmVGT_GS_ONCHIP_CNTL                                                    0xa291
+#define mmVGT_GS_OUT_PRIM_TYPE                                                  0xa29b
+#define mmVGT_CACHE_INVALIDATION                                                0x2231
+#define mmVGT_RESET_DEBUG                                                       0x2232
+#define mmVGT_STRMOUT_DELAY                                                     0x2233
+#define mmVGT_FIFO_DEPTHS                                                       0x2234
+#define mmVGT_GS_PER_ES                                                         0xa295
+#define mmVGT_ES_PER_GS                                                         0xa296
+#define mmVGT_GS_PER_VS                                                         0xa297
+#define mmVGT_GS_VERTEX_REUSE                                                   0x2235
+#define mmVGT_MC_LAT_CNTL                                                       0x2236
+#define mmIA_CNTL_STATUS                                                        0x2237
+#define mmVGT_STRMOUT_CONFIG                                                    0xa2e5
+#define mmVGT_STRMOUT_BUFFER_SIZE_0                                             0xa2b4
+#define mmVGT_STRMOUT_BUFFER_SIZE_1                                             0xa2b8
+#define mmVGT_STRMOUT_BUFFER_SIZE_2                                             0xa2bc
+#define mmVGT_STRMOUT_BUFFER_SIZE_3                                             0xa2c0
+#define mmVGT_STRMOUT_BUFFER_OFFSET_0                                           0xa2b7
+#define mmVGT_STRMOUT_BUFFER_OFFSET_1                                           0xa2bb
+#define mmVGT_STRMOUT_BUFFER_OFFSET_2                                           0xa2bf
+#define mmVGT_STRMOUT_BUFFER_OFFSET_3                                           0xa2c3
+#define mmVGT_STRMOUT_VTX_STRIDE_0                                              0xa2b5
+#define mmVGT_STRMOUT_VTX_STRIDE_1                                              0xa2b9
+#define mmVGT_STRMOUT_VTX_STRIDE_2                                              0xa2bd
+#define mmVGT_STRMOUT_VTX_STRIDE_3                                              0xa2c1
+#define mmVGT_STRMOUT_BUFFER_CONFIG                                             0xa2e6
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                                      0xc244
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                                      0xc245
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                                      0xc246
+#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                                      0xc247
+#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                        0xa2ca
+#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                            0xa2cb
+#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                 0xa2cc
+#define mmVGT_GS_MAX_VERT_OUT                                                   0xa2ce
+#define mmVGT_SHADER_STAGES_EN                                                  0xa2d5
+#define mmVGT_DISPATCH_DRAW_INDEX                                               0xa2dd
+#define mmVGT_LS_HS_CONFIG                                                      0xa2d6
+#define mmVGT_DMA_LS_HS_CONFIG                                                  0x2273
+#define mmVGT_TF_PARAM                                                          0xa2db
+#define mmVGT_TESS_DISTRIBUTION                                                 0xa2d4
+#define mmVGT_TF_RING_SIZE                                                      0xc24e
+#define mmVGT_SYS_CONFIG                                                        0x2263
+#define mmVGT_HS_OFFCHIP_PARAM                                                  0xc24f
+#define mmVGT_TF_MEMORY_BASE                                                    0xc250
+#define mmVGT_GS_INSTANCE_CNT                                                   0xa2e4
+#define mmIA_MULTI_VGT_PARAM                                                    0xa2aa
+#define mmVGT_VS_MAX_WAVE_ID                                                    0x2268
+#define mmVGT_ESGS_RING_SIZE                                                    0xc240
+#define mmVGT_GSVS_RING_SIZE                                                    0xc241
+#define mmVGT_GSVS_RING_OFFSET_1                                                0xa298
+#define mmVGT_GSVS_RING_OFFSET_2                                                0xa299
+#define mmVGT_GSVS_RING_OFFSET_3                                                0xa29a
+#define mmVGT_ESGS_RING_ITEMSIZE                                                0xa2ab
+#define mmVGT_GSVS_RING_ITEMSIZE                                                0xa2ac
+#define mmVGT_GS_VERT_ITEMSIZE                                                  0xa2d7
+#define mmVGT_GS_VERT_ITEMSIZE_1                                                0xa2d8
+#define mmVGT_GS_VERT_ITEMSIZE_2                                                0xa2d9
+#define mmVGT_GS_VERT_ITEMSIZE_3                                                0xa2da
+#define mmWD_CNTL_STATUS                                                        0x223f
+#define mmWD_ENHANCE                                                            0xa2a0
+#define mmGFX_PIPE_CONTROL                                                      0x226d
+#define mmGFX_PIPE_PRIORITY                                                     0xf87f
+#define mmCGTT_VGT_CLK_CTRL                                                     0xf084
+#define mmCGTT_IA_CLK_CTRL                                                      0xf085
+#define mmCGTT_WD_CLK_CTRL                                                      0xf086
+#define mmVGT_DEBUG_CNTL                                                        0x2238
+#define mmVGT_DEBUG_DATA                                                        0x2239
+#define mmIA_DEBUG_CNTL                                                         0x223a
+#define mmIA_DEBUG_DATA                                                         0x223b
+#define mmVGT_CNTL_STATUS                                                       0x223c
+#define mmWD_DEBUG_CNTL                                                         0x223d
+#define mmWD_DEBUG_DATA                                                         0x223e
+#define mmWD_QOS                                                                0x2242
+#define mmCC_GC_PRIM_CONFIG                                                     0x2240
+#define mmGC_USER_PRIM_CONFIG                                                   0x2241
+#define ixWD_DEBUG_REG0                                                         0x0
+#define ixWD_DEBUG_REG1                                                         0x1
+#define ixWD_DEBUG_REG2                                                         0x2
+#define ixWD_DEBUG_REG3                                                         0x3
+#define ixWD_DEBUG_REG4                                                         0x4
+#define ixWD_DEBUG_REG5                                                         0x5
+#define ixWD_DEBUG_REG6                                                         0x6
+#define ixWD_DEBUG_REG7                                                         0x7
+#define ixWD_DEBUG_REG8                                                         0x8
+#define ixWD_DEBUG_REG9                                                         0x9
+#define ixWD_DEBUG_REG10                                                        0xa
+#define ixIA_DEBUG_REG0                                                         0x0
+#define ixIA_DEBUG_REG1                                                         0x1
+#define ixIA_DEBUG_REG2                                                         0x2
+#define ixIA_DEBUG_REG3                                                         0x3
+#define ixIA_DEBUG_REG4                                                         0x4
+#define ixIA_DEBUG_REG5                                                         0x5
+#define ixIA_DEBUG_REG6                                                         0x6
+#define ixIA_DEBUG_REG7                                                         0x7
+#define ixIA_DEBUG_REG8                                                         0x8
+#define ixIA_DEBUG_REG9                                                         0x9
+#define ixVGT_DEBUG_REG0                                                        0x0
+#define ixVGT_DEBUG_REG1                                                        0x1
+#define ixVGT_DEBUG_REG2                                                        0x1e
+#define ixVGT_DEBUG_REG3                                                        0x1f
+#define ixVGT_DEBUG_REG4                                                        0x20
+#define ixVGT_DEBUG_REG5                                                        0x21
+#define ixVGT_DEBUG_REG6                                                        0x22
+#define ixVGT_DEBUG_REG7                                                        0x23
+#define ixVGT_DEBUG_REG8                                                        0x8
+#define ixVGT_DEBUG_REG9                                                        0x9
+#define ixVGT_DEBUG_REG10                                                       0xa
+#define ixVGT_DEBUG_REG11                                                       0xb
+#define ixVGT_DEBUG_REG12                                                       0xc
+#define ixVGT_DEBUG_REG13                                                       0xd
+#define ixVGT_DEBUG_REG14                                                       0xe
+#define ixVGT_DEBUG_REG15                                                       0xf
+#define ixVGT_DEBUG_REG16                                                       0x10
+#define ixVGT_DEBUG_REG17                                                       0x11
+#define ixVGT_DEBUG_REG18                                                       0x7
+#define ixVGT_DEBUG_REG19                                                       0x13
+#define ixVGT_DEBUG_REG20                                                       0x14
+#define ixVGT_DEBUG_REG21                                                       0x15
+#define ixVGT_DEBUG_REG22                                                       0x16
+#define ixVGT_DEBUG_REG23                                                       0x17
+#define ixVGT_DEBUG_REG24                                                       0x18
+#define ixVGT_DEBUG_REG25                                                       0x19
+#define ixVGT_DEBUG_REG26                                                       0x24
+#define ixVGT_DEBUG_REG27                                                       0x1b
+#define ixVGT_DEBUG_REG28                                                       0x1c
+#define ixVGT_DEBUG_REG29                                                       0x1d
+#define ixVGT_DEBUG_REG31                                                       0x26
+#define ixVGT_DEBUG_REG32                                                       0x27
+#define ixVGT_DEBUG_REG33                                                       0x28
+#define ixVGT_DEBUG_REG34                                                       0x29
+#define ixVGT_DEBUG_REG36                                                       0x2b
+#define mmVGT_PERFCOUNTER_SEID_MASK                                             0xd894
+#define mmVGT_PERFCOUNTER0_SELECT                                               0xd88c
+#define mmVGT_PERFCOUNTER1_SELECT                                               0xd88d
+#define mmVGT_PERFCOUNTER2_SELECT                                               0xd88e
+#define mmVGT_PERFCOUNTER3_SELECT                                               0xd88f
+#define mmVGT_PERFCOUNTER0_SELECT1                                              0xd890
+#define mmVGT_PERFCOUNTER1_SELECT1                                              0xd891
+#define mmVGT_PERFCOUNTER0_LO                                                   0xd090
+#define mmVGT_PERFCOUNTER1_LO                                                   0xd092
+#define mmVGT_PERFCOUNTER2_LO                                                   0xd094
+#define mmVGT_PERFCOUNTER3_LO                                                   0xd096
+#define mmVGT_PERFCOUNTER0_HI                                                   0xd091
+#define mmVGT_PERFCOUNTER1_HI                                                   0xd093
+#define mmVGT_PERFCOUNTER2_HI                                                   0xd095
+#define mmVGT_PERFCOUNTER3_HI                                                   0xd097
+#define mmIA_PERFCOUNTER0_SELECT                                                0xd884
+#define mmIA_PERFCOUNTER1_SELECT                                                0xd885
+#define mmIA_PERFCOUNTER2_SELECT                                                0xd886
+#define mmIA_PERFCOUNTER3_SELECT                                                0xd887
+#define mmIA_PERFCOUNTER0_SELECT1                                               0xd888
+#define mmIA_PERFCOUNTER0_LO                                                    0xd088
+#define mmIA_PERFCOUNTER1_LO                                                    0xd08a
+#define mmIA_PERFCOUNTER2_LO                                                    0xd08c
+#define mmIA_PERFCOUNTER3_LO                                                    0xd08e
+#define mmIA_PERFCOUNTER0_HI                                                    0xd089
+#define mmIA_PERFCOUNTER1_HI                                                    0xd08b
+#define mmIA_PERFCOUNTER2_HI                                                    0xd08d
+#define mmIA_PERFCOUNTER3_HI                                                    0xd08f
+#define mmWD_PERFCOUNTER0_SELECT                                                0xd880
+#define mmWD_PERFCOUNTER1_SELECT                                                0xd881
+#define mmWD_PERFCOUNTER2_SELECT                                                0xd882
+#define mmWD_PERFCOUNTER3_SELECT                                                0xd883
+#define mmWD_PERFCOUNTER0_LO                                                    0xd080
+#define mmWD_PERFCOUNTER1_LO                                                    0xd082
+#define mmWD_PERFCOUNTER2_LO                                                    0xd084
+#define mmWD_PERFCOUNTER3_LO                                                    0xd086
+#define mmWD_PERFCOUNTER0_HI                                                    0xd081
+#define mmWD_PERFCOUNTER1_HI                                                    0xd083
+#define mmWD_PERFCOUNTER2_HI                                                    0xd085
+#define mmWD_PERFCOUNTER3_HI                                                    0xd087
+#define mmDIDT_IND_INDEX                                                        0x3280
+#define mmDIDT_IND_DATA                                                         0x3281
+#define ixDIDT_SQ_CTRL0                                                         0x0
+#define ixDIDT_SQ_CTRL1                                                         0x1
+#define ixDIDT_SQ_CTRL2                                                         0x2
+#define ixDIDT_SQ_CTRL_OCP                                                      0x3
+#define ixDIDT_SQ_WEIGHT0_3                                                     0x10
+#define ixDIDT_SQ_WEIGHT4_7                                                     0x11
+#define ixDIDT_SQ_WEIGHT8_11                                                    0x12
+#define ixDIDT_DB_CTRL0                                                         0x20
+#define ixDIDT_DB_CTRL1                                                         0x21
+#define ixDIDT_DB_CTRL2                                                         0x22
+#define ixDIDT_DB_CTRL_OCP                                                      0x23
+#define ixDIDT_DB_WEIGHT0_3                                                     0x30
+#define ixDIDT_DB_WEIGHT4_7                                                     0x31
+#define ixDIDT_DB_WEIGHT8_11                                                    0x32
+#define ixDIDT_TD_CTRL0                                                         0x40
+#define ixDIDT_TD_CTRL1                                                         0x41
+#define ixDIDT_TD_CTRL2                                                         0x42
+#define ixDIDT_TD_CTRL_OCP                                                      0x43
+#define ixDIDT_TD_WEIGHT0_3                                                     0x50
+#define ixDIDT_TD_WEIGHT4_7                                                     0x51
+#define ixDIDT_TD_WEIGHT8_11                                                    0x52
+#define ixDIDT_TCP_CTRL0                                                        0x60
+#define ixDIDT_TCP_CTRL1                                                        0x61
+#define ixDIDT_TCP_CTRL2                                                        0x62
+#define ixDIDT_TCP_CTRL_OCP                                                     0x63
+#define ixDIDT_TCP_WEIGHT0_3                                                    0x70
+#define ixDIDT_TCP_WEIGHT4_7                                                    0x71
+#define ixDIDT_TCP_WEIGHT8_11                                                   0x72
+#define ixDIDT_DBR_CTRL0                                                        0x80
+#define ixDIDT_DBR_CTRL1                                                        0x81
+#define ixDIDT_DBR_CTRL2                                                        0x82
+#define ixDIDT_DBR_CTRL_OCP                                                     0x83
+#define ixDIDT_DBR_WEIGHT0_3                                                    0x90
+#define ixDIDT_DBR_WEIGHT4_7                                                    0x91
+#define ixDIDT_DBR_WEIGHT8_11                                                   0x92
+
+#endif /* GFX_8_0_D_H */

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h
new file mode 100644 (file)
index 0000000..43386c2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h
@@ -0,0 +1,6858 @@
+/*
+ * GFX_8_0 Register documentation
+ *
+ * Copyright (C) 2014  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_8_0_ENUM_H
+#define GFX_8_0_ENUM_H
+
+typedef enum SurfaceNumber {
+       NUMBER_UNORM                                     = 0x0,
+       NUMBER_SNORM                                     = 0x1,
+       NUMBER_USCALED                                   = 0x2,
+       NUMBER_SSCALED                                   = 0x3,
+       NUMBER_UINT                                      = 0x4,
+       NUMBER_SINT                                      = 0x5,
+       NUMBER_SRGB                                      = 0x6,
+       NUMBER_FLOAT                                     = 0x7,
+} SurfaceNumber;
+typedef enum SurfaceSwap {
+       SWAP_STD                                         = 0x0,
+       SWAP_ALT                                         = 0x1,
+       SWAP_STD_REV                                     = 0x2,
+       SWAP_ALT_REV                                     = 0x3,
+} SurfaceSwap;
+typedef enum CBMode {
+       CB_DISABLE                                       = 0x0,
+       CB_NORMAL                                        = 0x1,
+       CB_ELIMINATE_FAST_CLEAR                          = 0x2,
+       CB_RESOLVE                                       = 0x3,
+       CB_DECOMPRESS                                    = 0x4,
+       CB_FMASK_DECOMPRESS                              = 0x5,
+       CB_DCC_DECOMPRESS                                = 0x6,
+} CBMode;
+typedef enum RoundMode {
+       ROUND_BY_HALF                                    = 0x0,
+       ROUND_TRUNCATE                                   = 0x1,
+} RoundMode;
+typedef enum SourceFormat {
+       EXPORT_4C_32BPC                                  = 0x0,
+       EXPORT_4C_16BPC                                  = 0x1,
+       EXPORT_2C_32BPC_GR                               = 0x2,
+       EXPORT_2C_32BPC_AR                               = 0x3,
+} SourceFormat;
+typedef enum BlendOp {
+       BLEND_ZERO                                       = 0x0,
+       BLEND_ONE                                        = 0x1,
+       BLEND_SRC_COLOR                                  = 0x2,
+       BLEND_ONE_MINUS_SRC_COLOR                        = 0x3,
+       BLEND_SRC_ALPHA                                  = 0x4,
+       BLEND_ONE_MINUS_SRC_ALPHA                        = 0x5,
+       BLEND_DST_ALPHA                                  = 0x6,
+       BLEND_ONE_MINUS_DST_ALPHA                        = 0x7,
+       BLEND_DST_COLOR                                  = 0x8,
+       BLEND_ONE_MINUS_DST_COLOR                        = 0x9,
+       BLEND_SRC_ALPHA_SATURATE                         = 0xa,
+       BLEND_BOTH_SRC_ALPHA                             = 0xb,
+       BLEND_BOTH_INV_SRC_ALPHA                         = 0xc,
+       BLEND_CONSTANT_COLOR                             = 0xd,
+       BLEND_ONE_MINUS_CONSTANT_COLOR                   = 0xe,
+       BLEND_SRC1_COLOR                                 = 0xf,
+       BLEND_INV_SRC1_COLOR                             = 0x10,
+       BLEND_SRC1_ALPHA                                 = 0x11,
+       BLEND_INV_SRC1_ALPHA                             = 0x12,
+       BLEND_CONSTANT_ALPHA                             = 0x13,
+       BLEND_ONE_MINUS_CONSTANT_ALPHA                   = 0x14,
+} BlendOp;
+typedef enum CombFunc {
+       COMB_DST_PLUS_SRC                                = 0x0,
+       COMB_SRC_MINUS_DST                               = 0x1,
+       COMB_MIN_DST_SRC                                 = 0x2,
+       COMB_MAX_DST_SRC                                 = 0x3,
+       COMB_DST_MINUS_SRC                               = 0x4,
+} CombFunc;
+typedef enum BlendOpt {
+       FORCE_OPT_AUTO                                   = 0x0,
+       FORCE_OPT_DISABLE                                = 0x1,
+       FORCE_OPT_ENABLE_IF_SRC_A_0                      = 0x2,
+       FORCE_OPT_ENABLE_IF_SRC_RGB_0                    = 0x3,
+       FORCE_OPT_ENABLE_IF_SRC_ARGB_0                   = 0x4,
+       FORCE_OPT_ENABLE_IF_SRC_A_1                      = 0x5,
+       FORCE_OPT_ENABLE_IF_SRC_RGB_1                    = 0x6,
+       FORCE_OPT_ENABLE_IF_SRC_ARGB_1                   = 0x7,
+} BlendOpt;
+typedef enum CmaskCode {
+       CMASK_CLR00_F0                                   = 0x0,
+       CMASK_CLR00_F1                                   = 0x1,
+       CMASK_CLR00_F2                                   = 0x2,
+       CMASK_CLR00_FX                                   = 0x3,
+       CMASK_CLR01_F0                                   = 0x4,
+       CMASK_CLR01_F1                                   = 0x5,
+       CMASK_CLR01_F2                                   = 0x6,
+       CMASK_CLR01_FX                                   = 0x7,
+       CMASK_CLR10_F0                                   = 0x8,
+       CMASK_CLR10_F1                                   = 0x9,
+       CMASK_CLR10_F2                                   = 0xa,
+       CMASK_CLR10_FX                                   = 0xb,
+       CMASK_CLR11_F0                                   = 0xc,
+       CMASK_CLR11_F1                                   = 0xd,
+       CMASK_CLR11_F2                                   = 0xe,
+       CMASK_CLR11_FX                                   = 0xf,
+} CmaskCode;
+typedef enum CmaskAddr {
+       CMASK_ADDR_TILED                                 = 0x0,
+       CMASK_ADDR_LINEAR                                = 0x1,
+       CMASK_ADDR_COMPATIBLE                            = 0x2,
+} CmaskAddr;
+typedef enum CBPerfSel {
+       CB_PERF_SEL_NONE                                 = 0x0,
+       CB_PERF_SEL_BUSY                                 = 0x1,
+       CB_PERF_SEL_CORE_SCLK_VLD                        = 0x2,
+       CB_PERF_SEL_REG_SCLK0_VLD                        = 0x3,
+       CB_PERF_SEL_REG_SCLK1_VLD                        = 0x4,
+       CB_PERF_SEL_DRAWN_QUAD                           = 0x5,
+       CB_PERF_SEL_DRAWN_PIXEL                          = 0x6,
+       CB_PERF_SEL_DRAWN_QUAD_FRAGMENT                  = 0x7,
+       CB_PERF_SEL_DRAWN_TILE                           = 0x8,
+       CB_PERF_SEL_DB_CB_TILE_VALID_READY               = 0x9,
+       CB_PERF_SEL_DB_CB_TILE_VALID_READYB              = 0xa,
+       CB_PERF_SEL_DB_CB_TILE_VALIDB_READY              = 0xb,
+       CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB             = 0xc,
+       CB_PERF_SEL_CM_FC_TILE_VALID_READY               = 0xd,
+       CB_PERF_SEL_CM_FC_TILE_VALID_READYB              = 0xe,
+       CB_PERF_SEL_CM_FC_TILE_VALIDB_READY              = 0xf,
+       CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB             = 0x10,
+       CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY          = 0x11,
+       CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB         = 0x12,
+       CB_PERF_SEL_DB_CB_LQUAD_VALID_READY              = 0x13,
+       CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB             = 0x14,
+       CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY             = 0x15,
+       CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB            = 0x16,
+       CB_PERF_SEL_LQUAD_NO_TILE                        = 0x17,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R          = 0x18,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR         = 0x19,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR         = 0x1a,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR       = 0x1b,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR     = 0x1c,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
+       CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
+       CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT    = 0x1f,
+       CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID         = 0x20,
+       CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
+       CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK      = 0x22,
+       CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL         = 0x23,
+       CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY            = 0x24,
+       CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB           = 0x25,
+       CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY           = 0x26,
+       CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB          = 0x27,
+       CB_PERF_SEL_FOP_IN_VALID_READY                   = 0x28,
+       CB_PERF_SEL_FOP_IN_VALID_READYB                  = 0x29,
+       CB_PERF_SEL_FOP_IN_VALIDB_READY                  = 0x2a,
+       CB_PERF_SEL_FOP_IN_VALIDB_READYB                 = 0x2b,
+       CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY           = 0x2c,
+       CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB          = 0x2d,
+       CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY          = 0x2e,
+       CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB         = 0x2f,
+       CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY            = 0x30,
+       CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB           = 0x31,
+       CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY           = 0x32,
+       CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB          = 0x33,
+       CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY            = 0x34,
+       CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB           = 0x35,
+       CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY           = 0x36,
+       CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB          = 0x37,
+       CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY        = 0x38,
+       CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB       = 0x39,
+       CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY       = 0x3a,
+       CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB      = 0x3b,
+       CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY         = 0x3c,
+       CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB        = 0x3d,
+       CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY        = 0x3e,
+       CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB       = 0x3f,
+       CB_PERF_SEL_CC_BC_CS_FRAG_VALID                  = 0x40,
+       CB_PERF_SEL_CM_CACHE_HIT                         = 0x41,
+       CB_PERF_SEL_CM_CACHE_TAG_MISS                    = 0x42,
+       CB_PERF_SEL_CM_CACHE_SECTOR_MISS                 = 0x43,
+       CB_PERF_SEL_CM_CACHE_REEVICTION_STALL            = 0x44,
+       CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
+       CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
+       CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
+       CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL           = 0x48,
+       CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL          = 0x49,
+       CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL            = 0x4a,
+       CB_PERF_SEL_CM_CACHE_STALL                       = 0x4b,
+       CB_PERF_SEL_CM_CACHE_FLUSH                       = 0x4c,
+       CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED                = 0x4d,
+       CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED             = 0x4e,
+       CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED       = 0x4f,
+       CB_PERF_SEL_FC_CACHE_HIT                         = 0x50,
+       CB_PERF_SEL_FC_CACHE_TAG_MISS                    = 0x51,
+       CB_PERF_SEL_FC_CACHE_SECTOR_MISS                 = 0x52,
+       CB_PERF_SEL_FC_CACHE_REEVICTION_STALL            = 0x53,
+       CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
+       CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
+       CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
+       CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL           = 0x57,
+       CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL          = 0x58,
+       CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL            = 0x59,
+       CB_PERF_SEL_FC_CACHE_STALL                       = 0x5a,
+       CB_PERF_SEL_FC_CACHE_FLUSH                       = 0x5b,
+       CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED                = 0x5c,
+       CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED             = 0x5d,
+       CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x5e,
+       CB_PERF_SEL_CC_CACHE_HIT                         = 0x5f,
+       CB_PERF_SEL_CC_CACHE_TAG_MISS                    = 0x60,
+       CB_PERF_SEL_CC_CACHE_SECTOR_MISS                 = 0x61,
+       CB_PERF_SEL_CC_CACHE_REEVICTION_STALL            = 0x62,
+       CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
+       CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
+       CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
+       CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL           = 0x66,
+       CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL          = 0x67,
+       CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL            = 0x68,
+       CB_PERF_SEL_CC_CACHE_STALL                       = 0x69,
+       CB_PERF_SEL_CC_CACHE_FLUSH                       = 0x6a,
+       CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED                = 0x6b,
+       CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED             = 0x6c,
+       CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x6d,
+       CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION        = 0x6e,
+       CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC      = 0x6f,
+       CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY             = 0x70,
+       CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB            = 0x71,
+       CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY            = 0x72,
+       CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB           = 0x73,
+       CB_PERF_SEL_CM_MC_WRITE_REQUEST                  = 0x74,
+       CB_PERF_SEL_FC_MC_WRITE_REQUEST                  = 0x75,
+       CB_PERF_SEL_CC_MC_WRITE_REQUEST                  = 0x76,
+       CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x77,
+       CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x78,
+       CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x79,
+       CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY             = 0x7a,
+       CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB            = 0x7b,
+       CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY            = 0x7c,
+       CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB           = 0x7d,
+       CB_PERF_SEL_CM_MC_READ_REQUEST                   = 0x7e,
+       CB_PERF_SEL_FC_MC_READ_REQUEST                   = 0x7f,
+       CB_PERF_SEL_CC_MC_READ_REQUEST                   = 0x80,
+       CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT        = 0x81,
+       CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT        = 0x82,
+       CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT        = 0x83,
+       CB_PERF_SEL_CM_TQ_FULL                           = 0x84,
+       CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL      = 0x85,
+       CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL              = 0x86,
+       CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL              = 0x87,
+       CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL   = 0x88,
+       CB_PERF_SEL_FOP_FMASK_RAW_STALL                  = 0x89,
+       CB_PERF_SEL_FOP_FMASK_BYPASS_STALL               = 0x8a,
+       CB_PERF_SEL_CC_SF_FULL                           = 0x8b,
+       CB_PERF_SEL_CC_RB_FULL                           = 0x8c,
+       CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL     = 0x8d,
+       CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL      = 0x8e,
+       CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL             = 0x8f,
+       CB_PERF_SEL_EVENT                                = 0x90,
+       CB_PERF_SEL_EVENT_CACHE_FLUSH_TS                 = 0x91,
+       CB_PERF_SEL_EVENT_CONTEXT_DONE                   = 0x92,
+       CB_PERF_SEL_EVENT_CACHE_FLUSH                    = 0x93,
+       CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT   = 0x94,
+       CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT      = 0x95,
+       CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS       = 0x96,
+       CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META          = 0x97,
+       CB_PERF_SEL_CC_SURFACE_SYNC                      = 0x98,
+       CB_PERF_SEL_CMASK_READ_DATA_0xC                  = 0x99,
+       CB_PERF_SEL_CMASK_READ_DATA_0xD                  = 0x9a,
+       CB_PERF_SEL_CMASK_READ_DATA_0xE                  = 0x9b,
+       CB_PERF_SEL_CMASK_READ_DATA_0xF                  = 0x9c,
+       CB_PERF_SEL_CMASK_WRITE_DATA_0xC                 = 0x9d,
+       CB_PERF_SEL_CMASK_WRITE_DATA_0xD                 = 0x9e,
+       CB_PERF_SEL_CMASK_WRITE_DATA_0xE                 = 0x9f,
+       CB_PERF_SEL_CMASK_WRITE_DATA_0xF                 = 0xa0,
+       CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT              = 0xa1,
+       CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT         = 0xa2,
+       CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT      = 0xa3,
+       CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE    = 0xa4,
+       CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE   = 0xa5,
+       CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE   = 0xa6,
+       CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE   = 0xa7,
+       CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE   = 0xa8,
+       CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE   = 0xa9,
+       CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE   = 0xaa,
+       CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE   = 0xab,
+       CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE     = 0xac,
+       CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE    = 0xad,
+       CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE    = 0xae,
+       CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE    = 0xaf,
+       CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE    = 0xb0,
+       CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE    = 0xb1,
+       CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE    = 0xb2,
+       CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE    = 0xb3,
+       CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT                = 0xb4,
+       CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS               = 0xb5,
+       CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS               = 0xb6,
+       CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS               = 0xb7,
+       CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS               = 0xb8,
+       CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS               = 0xb9,
+       CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS               = 0xba,
+       CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT              = 0xbb,
+       CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS             = 0xbc,
+       CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS             = 0xbd,
+       CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS             = 0xbe,
+       CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS             = 0xbf,
+       CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS             = 0xc0,
+       CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS             = 0xc1,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_0                = 0xc2,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_1                = 0xc3,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_2                = 0xc4,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_3                = 0xc5,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_4                = 0xc6,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_5                = 0xc7,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_6                = 0xc8,
+       CB_PERF_SEL_QUAD_READS_FRAGMENT_7                = 0xc9,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0               = 0xca,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1               = 0xcb,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2               = 0xcc,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3               = 0xcd,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4               = 0xce,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5               = 0xcf,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6               = 0xd0,
+       CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7               = 0xd1,
+       CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST         = 0xd2,
+       CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS          = 0xd3,
+       CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS        = 0xd4,
+       CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5,
+       CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6,
+       CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED       = 0xd7,
+       CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST      = 0xd8,
+       CB_PERF_SEL_DRAWN_BUSY                           = 0xd9,
+       CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY              = 0xda,
+       CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY               = 0xdb,
+       CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY               = 0xdc,
+       CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY               = 0xdd,
+       CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde,
+       CB_PERF_SEL_FC_SEQUENCER_CLEAR                   = 0xdf,
+       CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR    = 0xe0,
+       CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS        = 0xe1,
+       CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2,
+       CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL             = 0xe3,
+       CB_PERF_SEL_FC_DOC_IS_STALLED                    = 0xe4,
+       CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED             = 0xe5,
+       CB_PERF_SEL_FC_DOC_MRTS_COMBINED                 = 0xe6,
+       CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS                = 0xe7,
+       CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT                 = 0xe8,
+       CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS                = 0xe9,
+       CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT                 = 0xea,
+       CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL         = 0xeb,
+       CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR            = 0xec,
+       CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS           = 0xed,
+       CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS           = 0xee,
+       CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS           = 0xef,
+       CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS     = 0xf0,
+       CB_PERF_SEL_FC_DCC_CACHE_HIT                     = 0xf1,
+       CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS                = 0xf2,
+       CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS             = 0xf3,
+       CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL        = 0xf4,
+       CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5,
+       CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6,
+       CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7,
+       CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL       = 0xf8,
+       CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL      = 0xf9,
+       CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL        = 0xfa,
+       CB_PERF_SEL_FC_DCC_CACHE_STALL                   = 0xfb,
+       CB_PERF_SEL_FC_DCC_CACHE_FLUSH                   = 0xfc,
+       CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED            = 0xfd,
+       CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED         = 0xfe,
+       CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED   = 0xff,
+       CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT             = 0x100,
+       CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST              = 0x101,
+       CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT   = 0x102,
+       CB_PERF_SEL_FC_MC_DCC_READ_REQUEST               = 0x103,
+       CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT    = 0x104,
+       CB_PERF_SEL_CC_DCC_RDREQ_STALL                   = 0x105,
+       CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN            = 0x106,
+       CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT           = 0x107,
+       CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN              = 0x108,
+       CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT             = 0x109,
+       CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR              = 0x10a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1     = 0x10b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1       = 0x11a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2       = 0x11f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3       = 0x124,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x15c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x15d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x163,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x164,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x16b,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x16c,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x172,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x173,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1        = 0x174,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2        = 0x175,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3        = 0x176,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4        = 0x177,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5        = 0x178,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6        = 0x179,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7        = 0x17a,
+       CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED       = 0x17b,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1           = 0x17c,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1           = 0x17d,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2           = 0x17e,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3           = 0x17f,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1           = 0x180,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2           = 0x181,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3           = 0x182,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4           = 0x183,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5           = 0x184,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1           = 0x185,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2           = 0x186,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3           = 0x187,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4           = 0x188,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5           = 0x189,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6           = 0x18a,
+       CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7           = 0x18b,
+} CBPerfSel;
+typedef enum CBPerfOpFilterSel {
+       CB_PERF_OP_FILTER_SEL_WRITE_ONLY                 = 0x0,
+       CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION          = 0x1,
+       CB_PERF_OP_FILTER_SEL_RESOLVE                    = 0x2,
+       CB_PERF_OP_FILTER_SEL_DECOMPRESS                 = 0x3,
+       CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS           = 0x4,
+       CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR       = 0x5,
+} CBPerfOpFilterSel;
+typedef enum CBPerfClearFilterSel {
+       CB_PERF_CLEAR_FILTER_SEL_NONCLEAR                = 0x0,
+       CB_PERF_CLEAR_FILTER_SEL_CLEAR                   = 0x1,
+} CBPerfClearFilterSel;
+typedef enum CP_RING_ID {
+       RINGID0                                          = 0x0,
+       RINGID1                                          = 0x1,
+       RINGID2                                          = 0x2,
+       RINGID3                                          = 0x3,
+} CP_RING_ID;
+typedef enum CP_PIPE_ID {
+       PIPE_ID0                                         = 0x0,
+       PIPE_ID1                                         = 0x1,
+       PIPE_ID2                                         = 0x2,
+       PIPE_ID3                                         = 0x3,
+} CP_PIPE_ID;
+typedef enum CP_ME_ID {
+       ME_ID0                                           = 0x0,
+       ME_ID1                                           = 0x1,
+       ME_ID2                                           = 0x2,
+       ME_ID3                                           = 0x3,
+} CP_ME_ID;
+typedef enum SPM_PERFMON_STATE {
+       STRM_PERFMON_STATE_DISABLE_AND_RESET             = 0x0,
+       STRM_PERFMON_STATE_START_COUNTING                = 0x1,
+       STRM_PERFMON_STATE_STOP_COUNTING                 = 0x2,
+       STRM_PERFMON_STATE_RESERVED_3                    = 0x3,
+       STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM     = 0x4,
+       STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM        = 0x5,
+} SPM_PERFMON_STATE;
+typedef enum CP_PERFMON_STATE {
+       CP_PERFMON_STATE_DISABLE_AND_RESET               = 0x0,
+       CP_PERFMON_STATE_START_COUNTING                  = 0x1,
+       CP_PERFMON_STATE_STOP_COUNTING                   = 0x2,
+       CP_PERFMON_STATE_RESERVED_3                      = 0x3,
+       CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM       = 0x4,
+       CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM          = 0x5,
+} CP_PERFMON_STATE;
+typedef enum CP_PERFMON_ENABLE_MODE {
+       CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT              = 0x0,
+       CP_PERFMON_ENABLE_MODE_RESERVED_1                = 0x1,
+       CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE        = 0x2,
+       CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE       = 0x3,
+} CP_PERFMON_ENABLE_MODE;
+typedef enum CPG_PERFCOUNT_SEL {
+       CPG_PERF_SEL_ALWAYS_COUNT                        = 0x0,
+       CPG_PERF_SEL_RBIU_FIFO_FULL                      = 0x1,
+       CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR             = 0x2,
+       CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL          = 0x3,
+       CPG_PERF_SEL_CP_GRBM_DWORDS_SENT                 = 0x4,
+       CPG_PERF_SEL_ME_PARSER_BUSY                      = 0x5,
+       CPG_PERF_SEL_COUNT_TYPE0_PACKETS                 = 0x6,
+       CPG_PERF_SEL_COUNT_TYPE3_PACKETS                 = 0x7,
+       CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0x8,
+       CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS              = 0x9,
+       CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS          = 0xa,
+       CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS          = 0xb,
+       CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ             = 0xc,
+       CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ            = 0xd,
+       CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX          = 0xe,
+       CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS        = 0xf,
+       CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE        = 0x10,
+       CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM   = 0x11,
+       CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY            = 0x12,
+       CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY            = 0x13,
+       CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY           = 0x14,
+       CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ       = 0x15,
+       CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP        = 0x16,
+       CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ        = 0x17,
+       CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX     = 0x18,
+       CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU          = 0x19,
+       CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS        = 0x1a,
+       CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH         = 0x1b,
+       CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER               = 0x1c,
+       CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER             = 0x1d,
+       CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS     = 0x1e,
+       CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY       = 0x1f,
+       CPG_PERF_SEL_DYNAMIC_CLK_VALID                   = 0x20,
+       CPG_PERF_SEL_REGISTER_CLK_VALID                  = 0x21,
+       CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT              = 0x22,
+       CPG_PERF_SEL_MIU_READ_REQUEST_SENT               = 0x23,
+       CPG_PERF_SEL_CE_STALL_RAM_DUMP                   = 0x24,
+       CPG_PERF_SEL_CE_STALL_RAM_WRITE                  = 0x25,
+       CPG_PERF_SEL_CE_STALL_ON_INC_FIFO                = 0x26,
+       CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO             = 0x27,
+       CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU           = 0x28,
+       CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ           = 0x29,
+       CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG          = 0x2a,
+       CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER              = 0x2b,
+       CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x2c,
+       CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS             = 0x2d,
+       CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x2e,
+       CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x2f,
+       CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x30,
+} CPG_PERFCOUNT_SEL;
+typedef enum CPF_PERFCOUNT_SEL {
+       CPF_PERF_SEL_ALWAYS_COUNT                        = 0x0,
+       CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE      = 0x1,
+       CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE        = 0x2,
+       CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS        = 0x3,
+       CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING          = 0x4,
+       CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1           = 0x5,
+       CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2           = 0x6,
+       CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE         = 0x7,
+       CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS       = 0x8,
+       CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR                 = 0x9,
+       CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR              = 0xa,
+       CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0xb,
+       CPF_PERF_SEL_GRBM_DWORDS_SENT                    = 0xc,
+       CPF_PERF_SEL_DYNAMIC_CLOCK_VALID                 = 0xd,
+       CPF_PERF_SEL_REGISTER_CLOCK_VALID                = 0xe,
+       CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND              = 0xf,
+       CPF_PERF_SEL_MIU_READ_REQUEST_SEND               = 0x10,
+       CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x11,
+       CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x12,
+       CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x13,
+} CPF_PERFCOUNT_SEL;
+typedef enum CPC_PERFCOUNT_SEL {
+       CPC_PERF_SEL_ALWAYS_COUNT                        = 0x0,
+       CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE             = 0x1,
+       CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION           = 0x2,
+       CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE             = 0x3,
+       CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE             = 0x4,
+       CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x5,
+       CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY        = 0x6,
+       CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF   = 0x7,
+       CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ         = 0x8,
+       CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ          = 0x9,
+       CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE         = 0xa,
+       CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ          = 0xb,
+       CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF     = 0xc,
+       CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE          = 0xd,
+       CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY        = 0xe,
+       CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF   = 0xf,
+       CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ         = 0x10,
+       CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ          = 0x11,
+       CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE         = 0x12,
+       CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ          = 0x13,
+       CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF     = 0x14,
+       CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE          = 0x15,
+       CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE          = 0x16,
+       CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS          = 0x17,
+       CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION          = 0x18,
+} CPC_PERFCOUNT_SEL;
+typedef enum CP_ALPHA_TAG_RAM_SEL {
+       CPG_TAG_RAM                                      = 0x0,
+       CPC_TAG_RAM                                      = 0x1,
+       CPF_TAG_RAM                                      = 0x2,
+       RSV_TAG_RAM                                      = 0x3,
+} CP_ALPHA_TAG_RAM_SEL;
+#define SEM_ECC_ERROR                             0x0
+#define SEM_RESERVED                              0x1
+#define SEM_FAILED                                0x2
+#define SEM_PASSED                                0x3
+#define IQ_QUEUE_SLEEP                            0x0
+#define IQ_OFFLOAD_RETRY                          0x1
+#define IQ_SCH_WAVE_MSG                           0x2
+#define IQ_SEM_REARM                              0x3
+#define IQ_DEQUEUE_RETRY                          0x4
+#define IQ_INTR_TYPE_PQ                           0x0
+#define IQ_INTR_TYPE_IB                           0x1
+#define IQ_INTR_TYPE_MQD                          0x2
+#define VMID_SZ                                   0x4
+#define CONFIG_SPACE_START                        0x2000
+#define CONFIG_SPACE_END                          0x9fff
+#define CONFIG_SPACE1_START                       0x2000
+#define CONFIG_SPACE1_END                         0x2bff
+#define CONFIG_SPACE2_START                       0x3000
+#define CONFIG_SPACE2_END                         0x9fff
+#define UCONFIG_SPACE_START                       0xc000
+#define UCONFIG_SPACE_END                         0xffff
+#define PERSISTENT_SPACE_START                    0x2c00
+#define PERSISTENT_SPACE_END                      0x2fff
+#define CONTEXT_SPACE_START                       0xa000
+#define CONTEXT_SPACE_END                         0xbfff
+typedef enum ForceControl {
+       FORCE_OFF                                        = 0x0,
+       FORCE_ENABLE                                     = 0x1,
+       FORCE_DISABLE                                    = 0x2,
+       FORCE_RESERVED                                   = 0x3,
+} ForceControl;
+typedef enum ZSamplePosition {
+       Z_SAMPLE_CENTER                                  = 0x0,
+       Z_SAMPLE_CENTROID                                = 0x1,
+} ZSamplePosition;
+typedef enum ZOrder {
+       LATE_Z                                           = 0x0,
+       EARLY_Z_THEN_LATE_Z                              = 0x1,
+       RE_Z                                             = 0x2,
+       EARLY_Z_THEN_RE_Z                                = 0x3,
+} ZOrder;
+typedef enum ZpassControl {
+       ZPASS_DISABLE                                    = 0x0,
+       ZPASS_SAMPLES                                    = 0x1,
+       ZPASS_PIXELS                                     = 0x2,
+} ZpassControl;
+typedef enum ZModeForce {
+       NO_FORCE                                         = 0x0,
+       FORCE_EARLY_Z                                    = 0x1,
+       FORCE_LATE_Z                                     = 0x2,
+       FORCE_RE_Z                                       = 0x3,
+} ZModeForce;
+typedef enum ZLimitSumm {
+       FORCE_SUMM_OFF                                   = 0x0,
+       FORCE_SUMM_MINZ                                  = 0x1,
+       FORCE_SUMM_MAXZ                                  = 0x2,
+       FORCE_SUMM_BOTH                                  = 0x3,
+} ZLimitSumm;
+typedef enum CompareFrag {
+       FRAG_NEVER                                       = 0x0,
+       FRAG_LESS                                        = 0x1,
+       FRAG_EQUAL                                       = 0x2,
+       FRAG_LEQUAL                                      = 0x3,
+       FRAG_GREATER                                     = 0x4,
+       FRAG_NOTEQUAL                                    = 0x5,
+       FRAG_GEQUAL                                      = 0x6,
+       FRAG_ALWAYS                                      = 0x7,
+} CompareFrag;
+typedef enum StencilOp {
+       STENCIL_KEEP                                     = 0x0,
+       STENCIL_ZERO                                     = 0x1,
+       STENCIL_ONES                                     = 0x2,
+       STENCIL_REPLACE_TEST                             = 0x3,
+       STENCIL_REPLACE_OP                               = 0x4,
+       STENCIL_ADD_CLAMP                                = 0x5,
+       STENCIL_SUB_CLAMP                                = 0x6,
+       STENCIL_INVERT                                   = 0x7,
+       STENCIL_ADD_WRAP                                 = 0x8,
+       STENCIL_SUB_WRAP                                 = 0x9,
+       STENCIL_AND                                      = 0xa,
+       STENCIL_OR                                       = 0xb,
+       STENCIL_XOR                                      = 0xc,
+       STENCIL_NAND                                     = 0xd,
+       STENCIL_NOR                                      = 0xe,
+       STENCIL_XNOR                                     = 0xf,
+} StencilOp;
+typedef enum ConservativeZExport {
+       EXPORT_ANY_Z                                     = 0x0,
+       EXPORT_LESS_THAN_Z                               = 0x1,
+       EXPORT_GREATER_THAN_Z                            = 0x2,
+       EXPORT_RESERVED                                  = 0x3,
+} ConservativeZExport;
+typedef enum DbPSLControl {
+       PSLC_AUTO                                        = 0x0,
+       PSLC_ON_HANG_ONLY                                = 0x1,
+       PSLC_ASAP                                        = 0x2,
+       PSLC_COUNTDOWN                                   = 0x3,
+} DbPSLControl;
+typedef enum PerfCounter_Vals {
+       DB_PERF_SEL_SC_DB_tile_sends                     = 0x0,
+       DB_PERF_SEL_SC_DB_tile_busy                      = 0x1,
+       DB_PERF_SEL_SC_DB_tile_stalls                    = 0x2,
+       DB_PERF_SEL_SC_DB_tile_events                    = 0x3,
+       DB_PERF_SEL_SC_DB_tile_tiles                     = 0x4,
+       DB_PERF_SEL_SC_DB_tile_covered                   = 0x5,
+       DB_PERF_SEL_hiz_tc_read_starved                  = 0x6,
+       DB_PERF_SEL_hiz_tc_write_stall                   = 0x7,
+       DB_PERF_SEL_hiz_qtiles_culled                    = 0x8,
+       DB_PERF_SEL_his_qtiles_culled                    = 0x9,
+       DB_PERF_SEL_DB_SC_tile_sends                     = 0xa,
+       DB_PERF_SEL_DB_SC_tile_busy                      = 0xb,
+       DB_PERF_SEL_DB_SC_tile_stalls                    = 0xc,
+       DB_PERF_SEL_DB_SC_tile_df_stalls                 = 0xd,
+       DB_PERF_SEL_DB_SC_tile_tiles                     = 0xe,
+       DB_PERF_SEL_DB_SC_tile_culled                    = 0xf,
+       DB_PERF_SEL_DB_SC_tile_hier_kill                 = 0x10,
+       DB_PERF_SEL_DB_SC_tile_fast_ops                  = 0x11,
+       DB_PERF_SEL_DB_SC_tile_no_ops                    = 0x12,
+       DB_PERF_SEL_DB_SC_tile_tile_rate                 = 0x13,
+       DB_PERF_SEL_DB_SC_tile_ssaa_kill                 = 0x14,
+       DB_PERF_SEL_DB_SC_tile_fast_z_ops                = 0x15,
+       DB_PERF_SEL_DB_SC_tile_fast_stencil_ops          = 0x16,
+       DB_PERF_SEL_SC_DB_quad_sends                     = 0x17,
+       DB_PERF_SEL_SC_DB_quad_busy                      = 0x18,
+       DB_PERF_SEL_SC_DB_quad_squads                    = 0x19,
+       DB_PERF_SEL_SC_DB_quad_tiles                     = 0x1a,
+       DB_PERF_SEL_SC_DB_quad_pixels                    = 0x1b,
+       DB_PERF_SEL_SC_DB_quad_killed_tiles              = 0x1c,
+       DB_PERF_SEL_DB_SC_quad_sends                     = 0x1d,
+       DB_PERF_SEL_DB_SC_quad_busy                      = 0x1e,
+       DB_PERF_SEL_DB_SC_quad_stalls                    = 0x1f,
+       DB_PERF_SEL_DB_SC_quad_tiles                     = 0x20,
+       DB_PERF_SEL_DB_SC_quad_lit_quad                  = 0x21,
+       DB_PERF_SEL_DB_CB_tile_sends                     = 0x22,
+       DB_PERF_SEL_DB_CB_tile_busy                      = 0x23,
+       DB_PERF_SEL_DB_CB_tile_stalls                    = 0x24,
+       DB_PERF_SEL_SX_DB_quad_sends                     = 0x25,
+       DB_PERF_SEL_SX_DB_quad_busy                      = 0x26,
+       DB_PERF_SEL_SX_DB_quad_stalls                    = 0x27,
+       DB_PERF_SEL_SX_DB_quad_quads                     = 0x28,
+       DB_PERF_SEL_SX_DB_quad_pixels                    = 0x29,
+       DB_PERF_SEL_SX_DB_quad_exports                   = 0x2a,
+       DB_PERF_SEL_SH_quads_outstanding_sum             = 0x2b,
+       DB_PERF_SEL_DB_CB_lquad_sends                    = 0x2c,
+       DB_PERF_SEL_DB_CB_lquad_busy                     = 0x2d,
+       DB_PERF_SEL_DB_CB_lquad_stalls                   = 0x2e,
+       DB_PERF_SEL_DB_CB_lquad_quads                    = 0x2f,
+       DB_PERF_SEL_tile_rd_sends                        = 0x30,
+       DB_PERF_SEL_mi_tile_rd_outstanding_sum           = 0x31,
+       DB_PERF_SEL_quad_rd_sends                        = 0x32,
+       DB_PERF_SEL_quad_rd_busy                         = 0x33,
+       DB_PERF_SEL_quad_rd_mi_stall                     = 0x34,
+       DB_PERF_SEL_quad_rd_rw_collision                 = 0x35,
+       DB_PERF_SEL_quad_rd_tag_stall                    = 0x36,
+       DB_PERF_SEL_quad_rd_32byte_reqs                  = 0x37,
+       DB_PERF_SEL_quad_rd_panic                        = 0x38,
+       DB_PERF_SEL_mi_quad_rd_outstanding_sum           = 0x39,
+       DB_PERF_SEL_quad_rdret_sends                     = 0x3a,
+       DB_PERF_SEL_quad_rdret_busy                      = 0x3b,
+       DB_PERF_SEL_tile_wr_sends                        = 0x3c,
+       DB_PERF_SEL_tile_wr_acks                         = 0x3d,
+       DB_PERF_SEL_mi_tile_wr_outstanding_sum           = 0x3e,
+       DB_PERF_SEL_quad_wr_sends                        = 0x3f,
+       DB_PERF_SEL_quad_wr_busy                         = 0x40,
+       DB_PERF_SEL_quad_wr_mi_stall                     = 0x41,
+       DB_PERF_SEL_quad_wr_coherency_stall              = 0x42,
+       DB_PERF_SEL_quad_wr_acks                         = 0x43,
+       DB_PERF_SEL_mi_quad_wr_outstanding_sum           = 0x44,
+       DB_PERF_SEL_Tile_Cache_misses                    = 0x45,
+       DB_PERF_SEL_Tile_Cache_hits                      = 0x46,
+       DB_PERF_SEL_Tile_Cache_flushes                   = 0x47,
+       DB_PERF_SEL_Tile_Cache_surface_stall             = 0x48,
+       DB_PERF_SEL_Tile_Cache_starves                   = 0x49,
+       DB_PERF_SEL_Tile_Cache_mem_return_starve         = 0x4a,
+       DB_PERF_SEL_tcp_dispatcher_reads                 = 0x4b,
+       DB_PERF_SEL_tcp_prefetcher_reads                 = 0x4c,
+       DB_PERF_SEL_tcp_preloader_reads                  = 0x4d,
+       DB_PERF_SEL_tcp_dispatcher_flushes               = 0x4e,
+       DB_PERF_SEL_tcp_prefetcher_flushes               = 0x4f,
+       DB_PERF_SEL_tcp_preloader_flushes                = 0x50,
+       DB_PERF_SEL_Depth_Tile_Cache_sends               = 0x51,
+       DB_PERF_SEL_Depth_Tile_Cache_busy                = 0x52,
+       DB_PERF_SEL_Depth_Tile_Cache_starves             = 0x53,
+       DB_PERF_SEL_Depth_Tile_Cache_dtile_locked        = 0x54,
+       DB_PERF_SEL_Depth_Tile_Cache_alloc_stall         = 0x55,
+       DB_PERF_SEL_Depth_Tile_Cache_misses              = 0x56,
+       DB_PERF_SEL_Depth_Tile_Cache_hits                = 0x57,
+       DB_PERF_SEL_Depth_Tile_Cache_flushes             = 0x58,
+       DB_PERF_SEL_Depth_Tile_Cache_noop_tile           = 0x59,
+       DB_PERF_SEL_Depth_Tile_Cache_detailed_noop       = 0x5a,
+       DB_PERF_SEL_Depth_Tile_Cache_event               = 0x5b,
+       DB_PERF_SEL_Depth_Tile_Cache_tile_frees          = 0x5c,
+       DB_PERF_SEL_Depth_Tile_Cache_data_frees          = 0x5d,
+       DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve   = 0x5e,
+       DB_PERF_SEL_Stencil_Cache_misses                 = 0x5f,
+       DB_PERF_SEL_Stencil_Cache_hits                   = 0x60,
+       DB_PERF_SEL_Stencil_Cache_flushes                = 0x61,
+       DB_PERF_SEL_Stencil_Cache_starves                = 0x62,
+       DB_PERF_SEL_Stencil_Cache_frees                  = 0x63,
+       DB_PERF_SEL_Z_Cache_separate_Z_misses            = 0x64,
+       DB_PERF_SEL_Z_Cache_separate_Z_hits              = 0x65,
+       DB_PERF_SEL_Z_Cache_separate_Z_flushes           = 0x66,
+       DB_PERF_SEL_Z_Cache_separate_Z_starves           = 0x67,
+       DB_PERF_SEL_Z_Cache_pmask_misses                 = 0x68,
+       DB_PERF_SEL_Z_Cache_pmask_hits                   = 0x69,
+       DB_PERF_SEL_Z_Cache_pmask_flushes                = 0x6a,
+       DB_PERF_SEL_Z_Cache_pmask_starves                = 0x6b,
+       DB_PERF_SEL_Z_Cache_frees                        = 0x6c,
+       DB_PERF_SEL_Plane_Cache_misses                   = 0x6d,
+       DB_PERF_SEL_Plane_Cache_hits                     = 0x6e,
+       DB_PERF_SEL_Plane_Cache_flushes                  = 0x6f,
+       DB_PERF_SEL_Plane_Cache_starves                  = 0x70,
+       DB_PERF_SEL_Plane_Cache_frees                    = 0x71,
+       DB_PERF_SEL_flush_expanded_stencil               = 0x72,
+       DB_PERF_SEL_flush_compressed_stencil             = 0x73,
+       DB_PERF_SEL_flush_single_stencil                 = 0x74,
+       DB_PERF_SEL_planes_flushed                       = 0x75,
+       DB_PERF_SEL_flush_1plane                         = 0x76,
+       DB_PERF_SEL_flush_2plane                         = 0x77,
+       DB_PERF_SEL_flush_3plane                         = 0x78,
+       DB_PERF_SEL_flush_4plane                         = 0x79,
+       DB_PERF_SEL_flush_5plane                         = 0x7a,
+       DB_PERF_SEL_flush_6plane                         = 0x7b,
+       DB_PERF_SEL_flush_7plane                         = 0x7c,
+       DB_PERF_SEL_flush_8plane                         = 0x7d,
+       DB_PERF_SEL_flush_9plane                         = 0x7e,
+       DB_PERF_SEL_flush_10plane                        = 0x7f,
+       DB_PERF_SEL_flush_11plane                        = 0x80,
+       DB_PERF_SEL_flush_12plane                        = 0x81,
+       DB_PERF_SEL_flush_13plane                        = 0x82,
+       DB_PERF_SEL_flush_14plane                        = 0x83,
+       DB_PERF_SEL_flush_15plane                        = 0x84,
+       DB_PERF_SEL_flush_16plane                        = 0x85,
+       DB_PERF_SEL_flush_expanded_z                     = 0x86,
+       DB_PERF_SEL_earlyZ_waiting_for_postZ_done        = 0x87,
+       DB_PERF_SEL_reZ_waiting_for_postZ_done           = 0x88,
+       DB_PERF_SEL_dk_tile_sends                        = 0x89,
+       DB_PERF_SEL_dk_tile_busy                         = 0x8a,
+       DB_PERF_SEL_dk_tile_quad_starves                 = 0x8b,
+       DB_PERF_SEL_dk_tile_stalls                       = 0x8c,
+       DB_PERF_SEL_dk_squad_sends                       = 0x8d,
+       DB_PERF_SEL_dk_squad_busy                        = 0x8e,
+       DB_PERF_SEL_dk_squad_stalls                      = 0x8f,
+       DB_PERF_SEL_Op_Pipe_Busy                         = 0x90,
+       DB_PERF_SEL_Op_Pipe_MC_Read_stall                = 0x91,
+       DB_PERF_SEL_qc_busy                              = 0x92,
+       DB_PERF_SEL_qc_xfc                               = 0x93,
+       DB_PERF_SEL_qc_conflicts                         = 0x94,
+       DB_PERF_SEL_qc_full_stall                        = 0x95,
+       DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ         = 0x96,
+       DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ         = 0x97,
+       DB_PERF_SEL_tsc_insert_summarize_stall           = 0x98,
+       DB_PERF_SEL_tl_busy                              = 0x99,
+       DB_PERF_SEL_tl_dtc_read_starved                  = 0x9a,
+       DB_PERF_SEL_tl_z_fetch_stall                     = 0x9b,
+       DB_PERF_SEL_tl_stencil_stall                     = 0x9c,
+       DB_PERF_SEL_tl_z_decompress_stall                = 0x9d,
+       DB_PERF_SEL_tl_stencil_locked_stall              = 0x9e,
+       DB_PERF_SEL_tl_events                            = 0x9f,
+       DB_PERF_SEL_tl_summarize_squads                  = 0xa0,
+       DB_PERF_SEL_tl_flush_expand_squads               = 0xa1,
+       DB_PERF_SEL_tl_expand_squads                     = 0xa2,
+       DB_PERF_SEL_tl_preZ_squads                       = 0xa3,
+       DB_PERF_SEL_tl_postZ_squads                      = 0xa4,
+       DB_PERF_SEL_tl_preZ_noop_squads                  = 0xa5,
+       DB_PERF_SEL_tl_postZ_noop_squads                 = 0xa6,
+       DB_PERF_SEL_tl_tile_ops                          = 0xa7,
+       DB_PERF_SEL_tl_in_xfc                            = 0xa8,
+       DB_PERF_SEL_tl_in_single_stencil_expand_stall    = 0xa9,
+       DB_PERF_SEL_tl_in_fast_z_stall                   = 0xaa,
+       DB_PERF_SEL_tl_out_xfc                           = 0xab,
+       DB_PERF_SEL_tl_out_squads                        = 0xac,
+       DB_PERF_SEL_zf_plane_multicycle                  = 0xad,
+       DB_PERF_SEL_PostZ_Samples_passing_Z              = 0xae,
+       DB_PERF_SEL_PostZ_Samples_failing_Z              = 0xaf,
+       DB_PERF_SEL_PostZ_Samples_failing_S              = 0xb0,
+       DB_PERF_SEL_PreZ_Samples_passing_Z               = 0xb1,
+       DB_PERF_SEL_PreZ_Samples_failing_Z               = 0xb2,
+       DB_PERF_SEL_PreZ_Samples_failing_S               = 0xb3,
+       DB_PERF_SEL_ts_tc_update_stall                   = 0xb4,
+       DB_PERF_SEL_sc_kick_start                        = 0xb5,
+       DB_PERF_SEL_sc_kick_end                          = 0xb6,
+       DB_PERF_SEL_clock_reg_active                     = 0xb7,
+       DB_PERF_SEL_clock_main_active                    = 0xb8,
+       DB_PERF_SEL_clock_mem_export_active              = 0xb9,
+       DB_PERF_SEL_esr_ps_out_busy                      = 0xba,
+       DB_PERF_SEL_esr_ps_lqf_busy                      = 0xbb,
+       DB_PERF_SEL_esr_ps_lqf_stall                     = 0xbc,
+       DB_PERF_SEL_etr_out_send                         = 0xbd,
+       DB_PERF_SEL_etr_out_busy                         = 0xbe,
+       DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0xbf,
+       DB_PERF_SEL_etr_out_cb_tile_stall                = 0xc0,
+       DB_PERF_SEL_etr_out_esr_stall                    = 0xc1,
+       DB_PERF_SEL_esr_ps_sqq_busy                      = 0xc2,
+       DB_PERF_SEL_esr_ps_sqq_stall                     = 0xc3,
+       DB_PERF_SEL_esr_eot_fwd_busy                     = 0xc4,
+       DB_PERF_SEL_esr_eot_fwd_holding_squad            = 0xc5,
+       DB_PERF_SEL_esr_eot_fwd_forward                  = 0xc6,
+       DB_PERF_SEL_esr_sqq_zi_busy                      = 0xc7,
+       DB_PERF_SEL_esr_sqq_zi_stall                     = 0xc8,
+       DB_PERF_SEL_postzl_sq_pt_busy                    = 0xc9,
+       DB_PERF_SEL_postzl_sq_pt_stall                   = 0xca,
+       DB_PERF_SEL_postzl_se_busy                       = 0xcb,
+       DB_PERF_SEL_postzl_se_stall                      = 0xcc,
+       DB_PERF_SEL_postzl_partial_launch                = 0xcd,
+       DB_PERF_SEL_postzl_full_launch                   = 0xce,
+       DB_PERF_SEL_postzl_partial_waiting               = 0xcf,
+       DB_PERF_SEL_postzl_tile_mem_stall                = 0xd0,
+       DB_PERF_SEL_postzl_tile_init_stall               = 0xd1,
+       DB_PEFF_SEL_prezl_tile_mem_stall                 = 0xd2,
+       DB_PERF_SEL_prezl_tile_init_stall                = 0xd3,
+       DB_PERF_SEL_dtt_sm_clash_stall                   = 0xd4,
+       DB_PERF_SEL_dtt_sm_slot_stall                    = 0xd5,
+       DB_PERF_SEL_dtt_sm_miss_stall                    = 0xd6,
+       DB_PERF_SEL_mi_rdreq_busy                        = 0xd7,
+       DB_PERF_SEL_mi_rdreq_stall                       = 0xd8,
+       DB_PERF_SEL_mi_wrreq_busy                        = 0xd9,
+       DB_PERF_SEL_mi_wrreq_stall                       = 0xda,
+       DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop     = 0xdb,
+       DB_PERF_SEL_dkg_tile_rate_tile                   = 0xdc,
+       DB_PERF_SEL_prezl_src_in_sends                   = 0xdd,
+       DB_PERF_SEL_prezl_src_in_stall                   = 0xde,
+       DB_PERF_SEL_prezl_src_in_squads                  = 0xdf,
+       DB_PERF_SEL_prezl_src_in_squads_unrolled         = 0xe0,
+       DB_PERF_SEL_prezl_src_in_tile_rate               = 0xe1,
+       DB_PERF_SEL_prezl_src_in_tile_rate_unrolled      = 0xe2,
+       DB_PERF_SEL_prezl_src_out_stall                  = 0xe3,
+       DB_PERF_SEL_postzl_src_in_sends                  = 0xe4,
+       DB_PERF_SEL_postzl_src_in_stall                  = 0xe5,
+       DB_PERF_SEL_postzl_src_in_squads                 = 0xe6,
+       DB_PERF_SEL_postzl_src_in_squads_unrolled        = 0xe7,
+       DB_PERF_SEL_postzl_src_in_tile_rate              = 0xe8,
+       DB_PERF_SEL_postzl_src_in_tile_rate_unrolled     = 0xe9,
+       DB_PERF_SEL_postzl_src_out_stall                 = 0xea,
+       DB_PERF_SEL_esr_ps_src_in_sends                  = 0xeb,
+       DB_PERF_SEL_esr_ps_src_in_stall                  = 0xec,
+       DB_PERF_SEL_esr_ps_src_in_squads                 = 0xed,
+       DB_PERF_SEL_esr_ps_src_in_squads_unrolled        = 0xee,
+       DB_PERF_SEL_esr_ps_src_in_tile_rate              = 0xef,
+       DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled     = 0xf0,
+       DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
+       DB_PERF_SEL_esr_ps_src_out_stall                 = 0xf2,
+       DB_PERF_SEL_depth_bounds_qtiles_culled           = 0xf3,
+       DB_PERF_SEL_PreZ_Samples_failing_DB              = 0xf4,
+       DB_PERF_SEL_PostZ_Samples_failing_DB             = 0xf5,
+       DB_PERF_SEL_flush_compressed                     = 0xf6,
+       DB_PERF_SEL_flush_plane_le4                      = 0xf7,
+       DB_PERF_SEL_tiles_z_fully_summarized             = 0xf8,
+       DB_PERF_SEL_tiles_stencil_fully_summarized       = 0xf9,
+       DB_PERF_SEL_tiles_z_clear_on_expclear            = 0xfa,
+       DB_PERF_SEL_tiles_s_clear_on_expclear            = 0xfb,
+       DB_PERF_SEL_tiles_decomp_on_expclear             = 0xfc,
+       DB_PERF_SEL_tiles_compressed_to_decompressed     = 0xfd,
+       DB_PERF_SEL_Op_Pipe_Prez_Busy                    = 0xfe,
+       DB_PERF_SEL_Op_Pipe_Postz_Busy                   = 0xff,
+       DB_PERF_SEL_di_dt_stall                          = 0x100,
+} PerfCounter_Vals;
+typedef enum RingCounterControl {
+       COUNTER_RING_SPLIT                               = 0x0,
+       COUNTER_RING_0                                   = 0x1,
+       COUNTER_RING_1                                   = 0x2,
+} RingCounterControl;
+typedef enum PixelPipeCounterId {
+       PIXEL_PIPE_OCCLUSION_COUNT_0                     = 0x0,
+       PIXEL_PIPE_OCCLUSION_COUNT_1                     = 0x1,
+       PIXEL_PIPE_OCCLUSION_COUNT_2                     = 0x2,
+       PIXEL_PIPE_OCCLUSION_COUNT_3                     = 0x3,
+       PIXEL_PIPE_SCREEN_MIN_EXTENTS_0                  = 0x4,
+       PIXEL_PIPE_SCREEN_MAX_EXTENTS_0                  = 0x5,
+       PIXEL_PIPE_SCREEN_MIN_EXTENTS_1                  = 0x6,
+       PIXEL_PIPE_SCREEN_MAX_EXTENTS_1                  = 0x7,
+} PixelPipeCounterId;
+typedef enum PixelPipeStride {
+       PIXEL_PIPE_STRIDE_32_BITS                        = 0x0,
+       PIXEL_PIPE_STRIDE_64_BITS                        = 0x1,
+       PIXEL_PIPE_STRIDE_128_BITS                       = 0x2,
+       PIXEL_PIPE_STRIDE_256_BITS                       = 0x3,
+} PixelPipeStride;
+typedef enum GB_EDC_DED_MODE {
+       GB_EDC_DED_MODE_LOG                              = 0x0,
+       GB_EDC_DED_MODE_HALT                             = 0x1,
+       GB_EDC_DED_MODE_INT_HALT                         = 0x2,
+} GB_EDC_DED_MODE;
+#define GB_TILING_CONFIG_TABLE_SIZE               0x20
+#define GB_TILING_CONFIG_MACROTABLE_SIZE          0x10
+typedef enum GRBM_PERF_SEL {
+       GRBM_PERF_SEL_COUNT                              = 0x0,
+       GRBM_PERF_SEL_USER_DEFINED                       = 0x1,
+       GRBM_PERF_SEL_GUI_ACTIVE                         = 0x2,
+       GRBM_PERF_SEL_CP_BUSY                            = 0x3,
+       GRBM_PERF_SEL_CP_COHER_BUSY                      = 0x4,
+       GRBM_PERF_SEL_CP_DMA_BUSY                        = 0x5,
+       GRBM_PERF_SEL_CB_BUSY                            = 0x6,
+       GRBM_PERF_SEL_DB_BUSY                            = 0x7,
+       GRBM_PERF_SEL_PA_BUSY                            = 0x8,
+       GRBM_PERF_SEL_SC_BUSY                            = 0x9,
+       GRBM_PERF_SEL_RESERVED_6                         = 0xa,
+       GRBM_PERF_SEL_SPI_BUSY                           = 0xb,
+       GRBM_PERF_SEL_SX_BUSY                            = 0xc,
+       GRBM_PERF_SEL_TA_BUSY                            = 0xd,
+       GRBM_PERF_SEL_CB_CLEAN                           = 0xe,
+       GRBM_PERF_SEL_DB_CLEAN                           = 0xf,
+       GRBM_PERF_SEL_RESERVED_5                         = 0x10,
+       GRBM_PERF_SEL_VGT_BUSY                           = 0x11,
+       GRBM_PERF_SEL_RESERVED_4                         = 0x12,
+       GRBM_PERF_SEL_RESERVED_3                         = 0x13,
+       GRBM_PERF_SEL_RESERVED_2                         = 0x14,
+       GRBM_PERF_SEL_RESERVED_1                         = 0x15,
+       GRBM_PERF_SEL_RESERVED_0                         = 0x16,
+       GRBM_PERF_SEL_IA_BUSY                            = 0x17,
+       GRBM_PERF_SEL_IA_NO_DMA_BUSY                     = 0x18,
+       GRBM_PERF_SEL_GDS_BUSY                           = 0x19,
+       GRBM_PERF_SEL_BCI_BUSY                           = 0x1a,
+       GRBM_PERF_SEL_RLC_BUSY                           = 0x1b,
+       GRBM_PERF_SEL_TC_BUSY                            = 0x1c,
+       GRBM_PERF_SEL_CPG_BUSY                           = 0x1d,
+       GRBM_PERF_SEL_CPC_BUSY                           = 0x1e,
+       GRBM_PERF_SEL_CPF_BUSY                           = 0x1f,
+       GRBM_PERF_SEL_WD_BUSY                            = 0x20,
+       GRBM_PERF_SEL_WD_NO_DMA_BUSY                     = 0x21,
+} GRBM_PERF_SEL;
+typedef enum GRBM_SE0_PERF_SEL {
+       GRBM_SE0_PERF_SEL_COUNT                          = 0x0,
+       GRBM_SE0_PERF_SEL_USER_DEFINED                   = 0x1,
+       GRBM_SE0_PERF_SEL_CB_BUSY                        = 0x2,
+       GRBM_SE0_PERF_SEL_DB_BUSY                        = 0x3,
+       GRBM_SE0_PERF_SEL_SC_BUSY                        = 0x4,
+       GRBM_SE0_PERF_SEL_RESERVED_1                     = 0x5,
+       GRBM_SE0_PERF_SEL_SPI_BUSY                       = 0x6,
+       GRBM_SE0_PERF_SEL_SX_BUSY                        = 0x7,
+       GRBM_SE0_PERF_SEL_TA_BUSY                        = 0x8,
+       GRBM_SE0_PERF_SEL_CB_CLEAN                       = 0x9,
+       GRBM_SE0_PERF_SEL_DB_CLEAN                       = 0xa,
+       GRBM_SE0_PERF_SEL_RESERVED_0                     = 0xb,
+       GRBM_SE0_PERF_SEL_PA_BUSY                        = 0xc,
+       GRBM_SE0_PERF_SEL_VGT_BUSY                       = 0xd,
+       GRBM_SE0_PERF_SEL_BCI_BUSY                       = 0xe,
+} GRBM_SE0_PERF_SEL;
+typedef enum GRBM_SE1_PERF_SEL {
+       GRBM_SE1_PERF_SEL_COUNT                          = 0x0,
+       GRBM_SE1_PERF_SEL_USER_DEFINED                   = 0x1,
+       GRBM_SE1_PERF_SEL_CB_BUSY                        = 0x2,
+       GRBM_SE1_PERF_SEL_DB_BUSY                        = 0x3,
+       GRBM_SE1_PERF_SEL_SC_BUSY                        = 0x4,
+       GRBM_SE1_PERF_SEL_RESERVED_1                     = 0x5,
+       GRBM_SE1_PERF_SEL_SPI_BUSY                       = 0x6,
+       GRBM_SE1_PERF_SEL_SX_BUSY                        = 0x7,
+       GRBM_SE1_PERF_SEL_TA_BUSY                        = 0x8,
+       GRBM_SE1_PERF_SEL_CB_CLEAN                       = 0x9,
+       GRBM_SE1_PERF_SEL_DB_CLEAN                       = 0xa,
+       GRBM_SE1_PERF_SEL_RESERVED_0                     = 0xb,
+       GRBM_SE1_PERF_SEL_PA_BUSY                        = 0xc,
+       GRBM_SE1_PERF_SEL_VGT_BUSY                       = 0xd,
+       GRBM_SE1_PERF_SEL_BCI_BUSY                       = 0xe,
+} GRBM_SE1_PERF_SEL;
+typedef enum GRBM_SE2_PERF_SEL {
+       GRBM_SE2_PERF_SEL_COUNT                          = 0x0,
+       GRBM_SE2_PERF_SEL_USER_DEFINED                   = 0x1,
+       GRBM_SE2_PERF_SEL_CB_BUSY                        = 0x2,
+       GRBM_SE2_PERF_SEL_DB_BUSY                        = 0x3,
+       GRBM_SE2_PERF_SEL_SC_BUSY                        = 0x4,
+       GRBM_SE2_PERF_SEL_RESERVED_1                     = 0x5,
+       GRBM_SE2_PERF_SEL_SPI_BUSY                       = 0x6,
+       GRBM_SE2_PERF_SEL_SX_BUSY                        = 0x7,
+       GRBM_SE2_PERF_SEL_TA_BUSY                        = 0x8,
+       GRBM_SE2_PERF_SEL_CB_CLEAN                       = 0x9,
+       GRBM_SE2_PERF_SEL_DB_CLEAN                       = 0xa,
+       GRBM_SE2_PERF_SEL_RESERVED_0                     = 0xb,
+       GRBM_SE2_PERF_SEL_PA_BUSY                        = 0xc,
+       GRBM_SE2_PERF_SEL_VGT_BUSY                       = 0xd,
+       GRBM_SE2_PERF_SEL_BCI_BUSY                       = 0xe,
+} GRBM_SE2_PERF_SEL;
+typedef enum GRBM_SE3_PERF_SEL {
+       GRBM_SE3_PERF_SEL_COUNT                          = 0x0,
+       GRBM_SE3_PERF_SEL_USER_DEFINED                   = 0x1,
+       GRBM_SE3_PERF_SEL_CB_BUSY                        = 0x2,
+       GRBM_SE3_PERF_SEL_DB_BUSY                        = 0x3,
+       GRBM_SE3_PERF_SEL_SC_BUSY                        = 0x4,
+       GRBM_SE3_PERF_SEL_RESERVED_1                     = 0x5,
+       GRBM_SE3_PERF_SEL_SPI_BUSY                       = 0x6,
+       GRBM_SE3_PERF_SEL_SX_BUSY                        = 0x7,
+       GRBM_SE3_PERF_SEL_TA_BUSY                        = 0x8,
+       GRBM_SE3_PERF_SEL_CB_CLEAN                       = 0x9,
+       GRBM_SE3_PERF_SEL_DB_CLEAN                       = 0xa,
+       GRBM_SE3_PERF_SEL_RESERVED_0                     = 0xb,
+       GRBM_SE3_PERF_SEL_PA_BUSY                        = 0xc,
+       GRBM_SE3_PERF_SEL_VGT_BUSY                       = 0xd,
+       GRBM_SE3_PERF_SEL_BCI_BUSY                       = 0xe,
+} GRBM_SE3_PERF_SEL;
+typedef enum SU_PERFCNT_SEL {
+       PERF_PAPC_PASX_REQ                               = 0x0,
+       PERF_PAPC_PASX_DISABLE_PIPE                      = 0x1,
+       PERF_PAPC_PASX_FIRST_VECTOR                      = 0x2,
+       PERF_PAPC_PASX_SECOND_VECTOR                     = 0x3,
+       PERF_PAPC_PASX_FIRST_DEAD                        = 0x4,
+       PERF_PAPC_PASX_SECOND_DEAD                       = 0x5,
+       PERF_PAPC_PASX_VTX_KILL_DISCARD                  = 0x6,
+       PERF_PAPC_PASX_VTX_NAN_DISCARD                   = 0x7,
+       PERF_PAPC_PA_INPUT_PRIM                          = 0x8,
+       PERF_PAPC_PA_INPUT_NULL_PRIM                     = 0x9,
+       PERF_PAPC_PA_INPUT_EVENT_FLAG                    = 0xa,
+       PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT               = 0xb,
+       PERF_PAPC_PA_INPUT_END_OF_PACKET                 = 0xc,
+       PERF_PAPC_PA_INPUT_EXTENDED_EVENT                = 0xd,
+       PERF_PAPC_CLPR_CULL_PRIM                         = 0xe,
+       PERF_PAPC_CLPR_VVUCP_CULL_PRIM                   = 0xf,
+       PERF_PAPC_CLPR_VV_CULL_PRIM                      = 0x10,
+       PERF_PAPC_CLPR_UCP_CULL_PRIM                     = 0x11,
+       PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM                = 0x12,
+       PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM                 = 0x13,
+       PERF_PAPC_CLPR_CULL_TO_NULL_PRIM                 = 0x14,
+       PERF_PAPC_CLPR_VVUCP_CLIP_PRIM                   = 0x15,
+       PERF_PAPC_CLPR_VV_CLIP_PRIM                      = 0x16,
+       PERF_PAPC_CLPR_UCP_CLIP_PRIM                     = 0x17,
+       PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE              = 0x18,
+       PERF_PAPC_CLPR_CLIP_PLANE_CNT_1                  = 0x19,
+       PERF_PAPC_CLPR_CLIP_PLANE_CNT_2                  = 0x1a,
+       PERF_PAPC_CLPR_CLIP_PLANE_CNT_3                  = 0x1b,
+       PERF_PAPC_CLPR_CLIP_PLANE_CNT_4                  = 0x1c,
+       PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8                = 0x1d,
+       PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12               = 0x1e,
+       PERF_PAPC_CLPR_CLIP_PLANE_NEAR                   = 0x1f,
+       PERF_PAPC_CLPR_CLIP_PLANE_FAR                    = 0x20,
+       PERF_PAPC_CLPR_CLIP_PLANE_LEFT                   = 0x21,
+       PERF_PAPC_CLPR_CLIP_PLANE_RIGHT                  = 0x22,
+       PERF_PAPC_CLPR_CLIP_PLANE_TOP                    = 0x23,
+       PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM                 = 0x24,
+       PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM                = 0x25,
+       PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM             = 0x26,
+       PERF_PAPC_CLSM_NULL_PRIM                         = 0x27,
+       PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM              = 0x28,
+       PERF_PAPC_CLSM_CULL_TO_NULL_PRIM                 = 0x29,
+       PERF_PAPC_CLSM_OUT_PRIM_CNT_1                    = 0x2a,
+       PERF_PAPC_CLSM_OUT_PRIM_CNT_2                    = 0x2b,
+       PERF_PAPC_CLSM_OUT_PRIM_CNT_3                    = 0x2c,
+       PERF_PAPC_CLSM_OUT_PRIM_CNT_4                    = 0x2d,
+       PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8                  = 0x2e,
+       PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13                 = 0x2f,
+       PERF_PAPC_CLIPGA_VTE_KILL_PRIM                   = 0x30,
+       PERF_PAPC_SU_INPUT_PRIM                          = 0x31,
+       PERF_PAPC_SU_INPUT_CLIP_PRIM                     = 0x32,
+       PERF_PAPC_SU_INPUT_NULL_PRIM                     = 0x33,
+       PERF_PAPC_SU_INPUT_PRIM_DUAL                     = 0x34,
+       PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL                = 0x35,
+       PERF_PAPC_SU_ZERO_AREA_CULL_PRIM                 = 0x36,
+       PERF_PAPC_SU_BACK_FACE_CULL_PRIM                 = 0x37,
+       PERF_PAPC_SU_FRONT_FACE_CULL_PRIM                = 0x38,
+       PERF_PAPC_SU_POLYMODE_FACE_CULL                  = 0x39,
+       PERF_PAPC_SU_POLYMODE_BACK_CULL                  = 0x3a,
+       PERF_PAPC_SU_POLYMODE_FRONT_CULL                 = 0x3b,
+       PERF_PAPC_SU_POLYMODE_INVALID_FILL               = 0x3c,
+       PERF_PAPC_SU_OUTPUT_PRIM                         = 0x3d,
+       PERF_PAPC_SU_OUTPUT_CLIP_PRIM                    = 0x3e,
+       PERF_PAPC_SU_OUTPUT_NULL_PRIM                    = 0x3f,
+       PERF_PAPC_SU_OUTPUT_EVENT_FLAG                   = 0x40,
+       PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT              = 0x41,
+       PERF_PAPC_SU_OUTPUT_END_OF_PACKET                = 0x42,
+       PERF_PAPC_SU_OUTPUT_POLYMODE_FACE                = 0x43,
+       PERF_PAPC_SU_OUTPUT_POLYMODE_BACK                = 0x44,
+       PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT               = 0x45,
+       PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE              = 0x46,
+       PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK              = 0x47,
+       PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT             = 0x48,
+       PERF_PAPC_SU_OUTPUT_PRIM_DUAL                    = 0x49,
+       PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL               = 0x4a,
+       PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL                = 0x4b,
+       PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL           = 0x4c,
+       PERF_PAPC_PASX_REQ_IDLE                          = 0x4d,
+       PERF_PAPC_PASX_REQ_BUSY                          = 0x4e,
+       PERF_PAPC_PASX_REQ_STALLED                       = 0x4f,
+       PERF_PAPC_PASX_REC_IDLE                          = 0x50,
+       PERF_PAPC_PASX_REC_BUSY                          = 0x51,
+       PERF_PAPC_PASX_REC_STARVED_SX                    = 0x52,
+       PERF_PAPC_PASX_REC_STALLED                       = 0x53,
+       PERF_PAPC_PASX_REC_STALLED_POS_MEM               = 0x54,
+       PERF_PAPC_PASX_REC_STALLED_CCGSM_IN              = 0x55,
+       PERF_PAPC_CCGSM_IDLE                             = 0x56,
+       PERF_PAPC_CCGSM_BUSY                             = 0x57,
+       PERF_PAPC_CCGSM_STALLED                          = 0x58,
+       PERF_PAPC_CLPRIM_IDLE                            = 0x59,
+       PERF_PAPC_CLPRIM_BUSY                            = 0x5a,
+       PERF_PAPC_CLPRIM_STALLED                         = 0x5b,
+       PERF_PAPC_CLPRIM_STARVED_CCGSM                   = 0x5c,
+       PERF_PAPC_CLIPSM_IDLE                            = 0x5d,
+       PERF_PAPC_CLIPSM_BUSY                            = 0x5e,
+       PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH             = 0x5f,
+       PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ               = 0x60,
+       PERF_PAPC_CLIPSM_WAIT_CLIPGA                     = 0x61,
+       PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP             = 0x62,
+       PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM                 = 0x63,
+       PERF_PAPC_CLIPGA_IDLE                            = 0x64,
+       PERF_PAPC_CLIPGA_BUSY                            = 0x65,
+       PERF_PAPC_CLIPGA_STARVED_VTE_CLIP                = 0x66,
+       PERF_PAPC_CLIPGA_STALLED                         = 0x67,
+       PERF_PAPC_CLIP_IDLE                              = 0x68,
+       PERF_PAPC_CLIP_BUSY                              = 0x69,
+       PERF_PAPC_SU_IDLE                                = 0x6a,
+       PERF_PAPC_SU_BUSY                                = 0x6b,
+       PERF_PAPC_SU_STARVED_CLIP                        = 0x6c,
+       PERF_PAPC_SU_STALLED_SC                          = 0x6d,
+       PERF_PAPC_CL_DYN_SCLK_VLD                        = 0x6e,
+       PERF_PAPC_SU_DYN_SCLK_VLD                        = 0x6f,
+       PERF_PAPC_PA_REG_SCLK_VLD                        = 0x70,
+       PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL          = 0x71,
+       PERF_PAPC_PASX_SE0_REQ                           = 0x72,
+       PERF_PAPC_PASX_SE1_REQ                           = 0x73,
+       PERF_PAPC_PASX_SE0_FIRST_VECTOR                  = 0x74,
+       PERF_PAPC_PASX_SE0_SECOND_VECTOR                 = 0x75,
+       PERF_PAPC_PASX_SE1_FIRST_VECTOR                  = 0x76,
+       PERF_PAPC_PASX_SE1_SECOND_VECTOR                 = 0x77,
+       PERF_PAPC_SU_SE0_PRIM_FILTER_CULL                = 0x78,
+       PERF_PAPC_SU_SE1_PRIM_FILTER_CULL                = 0x79,
+       PERF_PAPC_SU_SE01_PRIM_FILTER_CULL               = 0x7a,
+       PERF_PAPC_SU_SE0_OUTPUT_PRIM                     = 0x7b,
+       PERF_PAPC_SU_SE1_OUTPUT_PRIM                     = 0x7c,
+       PERF_PAPC_SU_SE01_OUTPUT_PRIM                    = 0x7d,
+       PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM                = 0x7e,
+       PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM                = 0x7f,
+       PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM               = 0x80,
+       PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT          = 0x81,
+       PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT          = 0x82,
+       PERF_PAPC_SU_SE0_STALLED_SC                      = 0x83,
+       PERF_PAPC_SU_SE1_STALLED_SC                      = 0x84,
+       PERF_PAPC_SU_SE01_STALLED_SC                     = 0x85,
+       PERF_PAPC_CLSM_CLIPPING_PRIM                     = 0x86,
+       PERF_PAPC_SU_CULLED_PRIM                         = 0x87,
+       PERF_PAPC_SU_OUTPUT_EOPG                         = 0x88,
+       PERF_PAPC_SU_SE2_PRIM_FILTER_CULL                = 0x89,
+       PERF_PAPC_SU_SE3_PRIM_FILTER_CULL                = 0x8a,
+       PERF_PAPC_SU_SE2_OUTPUT_PRIM                     = 0x8b,
+       PERF_PAPC_SU_SE3_OUTPUT_PRIM                     = 0x8c,
+       PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM                = 0x8d,
+       PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM                = 0x8e,
+       PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET            = 0x8f,
+       PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET            = 0x90,
+       PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET            = 0x91,
+       PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET            = 0x92,
+       PERF_PAPC_SU_SE0_OUTPUT_EOPG                     = 0x93,
+       PERF_PAPC_SU_SE1_OUTPUT_EOPG                     = 0x94,
+       PERF_PAPC_SU_SE2_OUTPUT_EOPG                     = 0x95,
+       PERF_PAPC_SU_SE3_OUTPUT_EOPG                     = 0x96,
+       PERF_PAPC_SU_SE2_STALLED_SC                      = 0x97,
+       PERF_PAPC_SU_SE3_STALLED_SC                      = 0x98,
+} SU_PERFCNT_SEL;
+typedef enum SC_PERFCNT_SEL {
+       SC_SRPS_WINDOW_VALID                             = 0x0,
+       SC_PSSW_WINDOW_VALID                             = 0x1,
+       SC_TPQZ_WINDOW_VALID                             = 0x2,
+       SC_QZQP_WINDOW_VALID                             = 0x3,
+       SC_TRPK_WINDOW_VALID                             = 0x4,
+       SC_SRPS_WINDOW_VALID_BUSY                        = 0x5,
+       SC_PSSW_WINDOW_VALID_BUSY                        = 0x6,
+       SC_TPQZ_WINDOW_VALID_BUSY                        = 0x7,
+       SC_QZQP_WINDOW_VALID_BUSY                        = 0x8,
+       SC_TRPK_WINDOW_VALID_BUSY                        = 0x9,
+       SC_STARVED_BY_PA                                 = 0xa,
+       SC_STALLED_BY_PRIMFIFO                           = 0xb,
+       SC_STALLED_BY_DB_TILE                            = 0xc,
+       SC_STARVED_BY_DB_TILE                            = 0xd,
+       SC_STALLED_BY_TILEORDERFIFO                      = 0xe,
+       SC_STALLED_BY_TILEFIFO                           = 0xf,
+       SC_STALLED_BY_DB_QUAD                            = 0x10,
+       SC_STARVED_BY_DB_QUAD                            = 0x11,
+       SC_STALLED_BY_QUADFIFO                           = 0x12,
+       SC_STALLED_BY_BCI                                = 0x13,
+       SC_STALLED_BY_SPI                                = 0x14,
+       SC_SCISSOR_DISCARD                               = 0x15,
+       SC_BB_DISCARD                                    = 0x16,
+       SC_SUPERTILE_COUNT                               = 0x17,
+       SC_SUPERTILE_PER_PRIM_H0                         = 0x18,
+       SC_SUPERTILE_PER_PRIM_H1                         = 0x19,
+       SC_SUPERTILE_PER_PRIM_H2                         = 0x1a,
+       SC_SUPERTILE_PER_PRIM_H3                         = 0x1b,
+       SC_SUPERTILE_PER_PRIM_H4                         = 0x1c,
+       SC_SUPERTILE_PER_PRIM_H5                         = 0x1d,
+       SC_SUPERTILE_PER_PRIM_H6                         = 0x1e,
+       SC_SUPERTILE_PER_PRIM_H7                         = 0x1f,
+       SC_SUPERTILE_PER_PRIM_H8                         = 0x20,
+       SC_SUPERTILE_PER_PRIM_H9                         = 0x21,
+       SC_SUPERTILE_PER_PRIM_H10                        = 0x22,
+       SC_SUPERTILE_PER_PRIM_H11                        = 0x23,
+       SC_SUPERTILE_PER_PRIM_H12                        = 0x24,
+       SC_SUPERTILE_PER_PRIM_H13                        = 0x25,
+       SC_SUPERTILE_PER_PRIM_H14                        = 0x26,
+       SC_SUPERTILE_PER_PRIM_H15                        = 0x27,
+       SC_SUPERTILE_PER_PRIM_H16                        = 0x28,
+       SC_TILE_PER_PRIM_H0                              = 0x29,
+       SC_TILE_PER_PRIM_H1                              = 0x2a,
+       SC_TILE_PER_PRIM_H2                              = 0x2b,
+       SC_TILE_PER_PRIM_H3                              = 0x2c,
+       SC_TILE_PER_PRIM_H4                              = 0x2d,
+       SC_TILE_PER_PRIM_H5                              = 0x2e,
+       SC_TILE_PER_PRIM_H6                              = 0x2f,
+       SC_TILE_PER_PRIM_H7                              = 0x30,
+       SC_TILE_PER_PRIM_H8                              = 0x31,
+       SC_TILE_PER_PRIM_H9                              = 0x32,
+       SC_TILE_PER_PRIM_H10                             = 0x33,
+       SC_TILE_PER_PRIM_H11                             = 0x34,
+       SC_TILE_PER_PRIM_H12                             = 0x35,
+       SC_TILE_PER_PRIM_H13                             = 0x36,
+       SC_TILE_PER_PRIM_H14                             = 0x37,
+       SC_TILE_PER_PRIM_H15                             = 0x38,
+       SC_TILE_PER_PRIM_H16                             = 0x39,
+       SC_TILE_PER_SUPERTILE_H0                         = 0x3a,
+       SC_TILE_PER_SUPERTILE_H1                         = 0x3b,
+       SC_TILE_PER_SUPERTILE_H2                         = 0x3c,
+       SC_TILE_PER_SUPERTILE_H3                         = 0x3d,
+       SC_TILE_PER_SUPERTILE_H4                         = 0x3e,
+       SC_TILE_PER_SUPERTILE_H5                         = 0x3f,
+       SC_TILE_PER_SUPERTILE_H6                         = 0x40,
+       SC_TILE_PER_SUPERTILE_H7                         = 0x41,
+       SC_TILE_PER_SUPERTILE_H8                         = 0x42,
+       SC_TILE_PER_SUPERTILE_H9                         = 0x43,
+       SC_TILE_PER_SUPERTILE_H10                        = 0x44,
+       SC_TILE_PER_SUPERTILE_H11                        = 0x45,
+       SC_TILE_PER_SUPERTILE_H12                        = 0x46,
+       SC_TILE_PER_SUPERTILE_H13                        = 0x47,
+       SC_TILE_PER_SUPERTILE_H14                        = 0x48,
+       SC_TILE_PER_SUPERTILE_H15                        = 0x49,
+       SC_TILE_PER_SUPERTILE_H16                        = 0x4a,
+       SC_TILE_PICKED_H1                                = 0x4b,
+       SC_TILE_PICKED_H2                                = 0x4c,
+       SC_TILE_PICKED_H3                                = 0x4d,
+       SC_TILE_PICKED_H4                                = 0x4e,
+       SC_QZ0_MULTI_GPU_TILE_DISCARD                    = 0x4f,
+       SC_QZ1_MULTI_GPU_TILE_DISCARD                    = 0x50,
+       SC_QZ2_MULTI_GPU_TILE_DISCARD                    = 0x51,
+       SC_QZ3_MULTI_GPU_TILE_DISCARD                    = 0x52,
+       SC_QZ0_TILE_COUNT                                = 0x53,
+       SC_QZ1_TILE_COUNT                                = 0x54,
+       SC_QZ2_TILE_COUNT                                = 0x55,
+       SC_QZ3_TILE_COUNT                                = 0x56,
+       SC_QZ0_TILE_COVERED_COUNT                        = 0x57,
+       SC_QZ1_TILE_COVERED_COUNT                        = 0x58,
+       SC_QZ2_TILE_COVERED_COUNT                        = 0x59,
+       SC_QZ3_TILE_COVERED_COUNT                        = 0x5a,
+       SC_QZ0_TILE_NOT_COVERED_COUNT                    = 0x5b,
+       SC_QZ1_TILE_NOT_COVERED_COUNT                    = 0x5c,
+       SC_QZ2_TILE_NOT_COVERED_COUNT                    = 0x5d,
+       SC_QZ3_TILE_NOT_COVERED_COUNT                    = 0x5e,
+       SC_QZ0_QUAD_PER_TILE_H0                          = 0x5f,
+       SC_QZ0_QUAD_PER_TILE_H1                          = 0x60,
+       SC_QZ0_QUAD_PER_TILE_H2                          = 0x61,
+       SC_QZ0_QUAD_PER_TILE_H3                          = 0x62,
+       SC_QZ0_QUAD_PER_TILE_H4                          = 0x63,
+       SC_QZ0_QUAD_PER_TILE_H5                          = 0x64,
+       SC_QZ0_QUAD_PER_TILE_H6                          = 0x65,
+       SC_QZ0_QUAD_PER_TILE_H7                          = 0x66,
+       SC_QZ0_QUAD_PER_TILE_H8                          = 0x67,
+       SC_QZ0_QUAD_PER_TILE_H9                          = 0x68,
+       SC_QZ0_QUAD_PER_TILE_H10                         = 0x69,
+       SC_QZ0_QUAD_PER_TILE_H11                         = 0x6a,
+       SC_QZ0_QUAD_PER_TILE_H12                         = 0x6b,
+       SC_QZ0_QUAD_PER_TILE_H13                         = 0x6c,
+       SC_QZ0_QUAD_PER_TILE_H14                         = 0x6d,
+       SC_QZ0_QUAD_PER_TILE_H15                         = 0x6e,
+       SC_QZ0_QUAD_PER_TILE_H16                         = 0x6f,
+       SC_QZ1_QUAD_PER_TILE_H0                          = 0x70,
+       SC_QZ1_QUAD_PER_TILE_H1                          = 0x71,
+       SC_QZ1_QUAD_PER_TILE_H2                          = 0x72,
+       SC_QZ1_QUAD_PER_TILE_H3                          = 0x73,
+       SC_QZ1_QUAD_PER_TILE_H4                          = 0x74,
+       SC_QZ1_QUAD_PER_TILE_H5                          = 0x75,
+       SC_QZ1_QUAD_PER_TILE_H6                          = 0x76,
+       SC_QZ1_QUAD_PER_TILE_H7                          = 0x77,
+       SC_QZ1_QUAD_PER_TILE_H8                          = 0x78,
+       SC_QZ1_QUAD_PER_TILE_H9                          = 0x79,
+       SC_QZ1_QUAD_PER_TILE_H10                         = 0x7a,
+       SC_QZ1_QUAD_PER_TILE_H11                         = 0x7b,
+       SC_QZ1_QUAD_PER_TILE_H12                         = 0x7c,
+       SC_QZ1_QUAD_PER_TILE_H13                         = 0x7d,
+       SC_QZ1_QUAD_PER_TILE_H14                         = 0x7e,
+       SC_QZ1_QUAD_PER_TILE_H15                         = 0x7f,
+       SC_QZ1_QUAD_PER_TILE_H16                         = 0x80,
+       SC_QZ2_QUAD_PER_TILE_H0                          = 0x81,
+       SC_QZ2_QUAD_PER_TILE_H1                          = 0x82,
+       SC_QZ2_QUAD_PER_TILE_H2                          = 0x83,
+       SC_QZ2_QUAD_PER_TILE_H3                          = 0x84,
+       SC_QZ2_QUAD_PER_TILE_H4                          = 0x85,
+       SC_QZ2_QUAD_PER_TILE_H5                          = 0x86,
+       SC_QZ2_QUAD_PER_TILE_H6                          = 0x87,
+       SC_QZ2_QUAD_PER_TILE_H7                          = 0x88,
+       SC_QZ2_QUAD_PER_TILE_H8                          = 0x89,
+       SC_QZ2_QUAD_PER_TILE_H9                          = 0x8a,
+       SC_QZ2_QUAD_PER_TILE_H10                         = 0x8b,
+       SC_QZ2_QUAD_PER_TILE_H11                         = 0x8c,
+       SC_QZ2_QUAD_PER_TILE_H12                         = 0x8d,
+       SC_QZ2_QUAD_PER_TILE_H13                         = 0x8e,
+       SC_QZ2_QUAD_PER_TILE_H14                         = 0x8f,
+       SC_QZ2_QUAD_PER_TILE_H15                         = 0x90,
+       SC_QZ2_QUAD_PER_TILE_H16                         = 0x91,
+       SC_QZ3_QUAD_PER_TILE_H0                          = 0x92,
+       SC_QZ3_QUAD_PER_TILE_H1                          = 0x93,
+       SC_QZ3_QUAD_PER_TILE_H2                          = 0x94,
+       SC_QZ3_QUAD_PER_TILE_H3                          = 0x95,
+       SC_QZ3_QUAD_PER_TILE_H4                          = 0x96,
+       SC_QZ3_QUAD_PER_TILE_H5                          = 0x97,
+       SC_QZ3_QUAD_PER_TILE_H6                          = 0x98,
+       SC_QZ3_QUAD_PER_TILE_H7                          = 0x99,
+       SC_QZ3_QUAD_PER_TILE_H8                          = 0x9a,
+       SC_QZ3_QUAD_PER_TILE_H9                          = 0x9b,
+       SC_QZ3_QUAD_PER_TILE_H10                         = 0x9c,
+       SC_QZ3_QUAD_PER_TILE_H11                         = 0x9d,
+       SC_QZ3_QUAD_PER_TILE_H12                         = 0x9e,
+       SC_QZ3_QUAD_PER_TILE_H13                         = 0x9f,
+       SC_QZ3_QUAD_PER_TILE_H14                         = 0xa0,
+       SC_QZ3_QUAD_PER_TILE_H15                         = 0xa1,
+       SC_QZ3_QUAD_PER_TILE_H16                         = 0xa2,
+       SC_QZ0_QUAD_COUNT                                = 0xa3,
+       SC_QZ1_QUAD_COUNT                                = 0xa4,
+       SC_QZ2_QUAD_COUNT                                = 0xa5,
+       SC_QZ3_QUAD_COUNT                                = 0xa6,
+       SC_P0_HIZ_TILE_COUNT                             = 0xa7,
+       SC_P1_HIZ_TILE_COUNT                             = 0xa8,
+       SC_P2_HIZ_TILE_COUNT                             = 0xa9,
+       SC_P3_HIZ_TILE_COUNT                             = 0xaa,
+       SC_P0_HIZ_QUAD_PER_TILE_H0                       = 0xab,
+       SC_P0_HIZ_QUAD_PER_TILE_H1                       = 0xac,
+       SC_P0_HIZ_QUAD_PER_TILE_H2                       = 0xad,
+       SC_P0_HIZ_QUAD_PER_TILE_H3                       = 0xae,
+       SC_P0_HIZ_QUAD_PER_TILE_H4                       = 0xaf,
+       SC_P0_HIZ_QUAD_PER_TILE_H5                       = 0xb0,
+       SC_P0_HIZ_QUAD_PER_TILE_H6                       = 0xb1,
+       SC_P0_HIZ_QUAD_PER_TILE_H7                       = 0xb2,
+       SC_P0_HIZ_QUAD_PER_TILE_H8                       = 0xb3,
+       SC_P0_HIZ_QUAD_PER_TILE_H9                       = 0xb4,
+       SC_P0_HIZ_QUAD_PER_TILE_H10                      = 0xb5,
+       SC_P0_HIZ_QUAD_PER_TILE_H11                      = 0xb6,
+       SC_P0_HIZ_QUAD_PER_TILE_H12                      = 0xb7,
+       SC_P0_HIZ_QUAD_PER_TILE_H13                      = 0xb8,
+       SC_P0_HIZ_QUAD_PER_TILE_H14                      = 0xb9,
+       SC_P0_HIZ_QUAD_PER_TILE_H15                      = 0xba,
+       SC_P0_HIZ_QUAD_PER_TILE_H16                      = 0xbb,
+       SC_P1_HIZ_QUAD_PER_TILE_H0                       = 0xbc,
+       SC_P1_HIZ_QUAD_PER_TILE_H1                       = 0xbd,
+       SC_P1_HIZ_QUAD_PER_TILE_H2                       = 0xbe,
+       SC_P1_HIZ_QUAD_PER_TILE_H3                       = 0xbf,
+       SC_P1_HIZ_QUAD_PER_TILE_H4                       = 0xc0,
+       SC_P1_HIZ_QUAD_PER_TILE_H5                       = 0xc1,
+       SC_P1_HIZ_QUAD_PER_TILE_H6                       = 0xc2,
+       SC_P1_HIZ_QUAD_PER_TILE_H7                       = 0xc3,
+       SC_P1_HIZ_QUAD_PER_TILE_H8                       = 0xc4,
+       SC_P1_HIZ_QUAD_PER_TILE_H9                       = 0xc5,
+       SC_P1_HIZ_QUAD_PER_TILE_H10                      = 0xc6,
+       SC_P1_HIZ_QUAD_PER_TILE_H11                      = 0xc7,
+       SC_P1_HIZ_QUAD_PER_TILE_H12                      = 0xc8,
+       SC_P1_HIZ_QUAD_PER_TILE_H13                      = 0xc9,
+       SC_P1_HIZ_QUAD_PER_TILE_H14                      = 0xca,
+       SC_P1_HIZ_QUAD_PER_TILE_H15                      = 0xcb,
+       SC_P1_HIZ_QUAD_PER_TILE_H16                      = 0xcc,
+       SC_P2_HIZ_QUAD_PER_TILE_H0                       = 0xcd,
+       SC_P2_HIZ_QUAD_PER_TILE_H1                       = 0xce,
+       SC_P2_HIZ_QUAD_PER_TILE_H2                       = 0xcf,
+       SC_P2_HIZ_QUAD_PER_TILE_H3                       = 0xd0,
+       SC_P2_HIZ_QUAD_PER_TILE_H4                       = 0xd1,
+       SC_P2_HIZ_QUAD_PER_TILE_H5                       = 0xd2,
+       SC_P2_HIZ_QUAD_PER_TILE_H6                       = 0xd3,
+       SC_P2_HIZ_QUAD_PER_TILE_H7                       = 0xd4,
+       SC_P2_HIZ_QUAD_PER_TILE_H8                       = 0xd5,
+       SC_P2_HIZ_QUAD_PER_TILE_H9                       = 0xd6,
+       SC_P2_HIZ_QUAD_PER_TILE_H10                      = 0xd7,
+       SC_P2_HIZ_QUAD_PER_TILE_H11                      = 0xd8,
+       SC_P2_HIZ_QUAD_PER_TILE_H12                      = 0xd9,
+       SC_P2_HIZ_QUAD_PER_TILE_H13                      = 0xda,
+       SC_P2_HIZ_QUAD_PER_TILE_H14                      = 0xdb,
+       SC_P2_HIZ_QUAD_PER_TILE_H15                      = 0xdc,
+       SC_P2_HIZ_QUAD_PER_TILE_H16                      = 0xdd,
+       SC_P3_HIZ_QUAD_PER_TILE_H0                       = 0xde,
+       SC_P3_HIZ_QUAD_PER_TILE_H1                       = 0xdf,
+       SC_P3_HIZ_QUAD_PER_TILE_H2                       = 0xe0,
+       SC_P3_HIZ_QUAD_PER_TILE_H3                       = 0xe1,
+       SC_P3_HIZ_QUAD_PER_TILE_H4                       = 0xe2,
+       SC_P3_HIZ_QUAD_PER_TILE_H5                       = 0xe3,
+       SC_P3_HIZ_QUAD_PER_TILE_H6                       = 0xe4,
+       SC_P3_HIZ_QUAD_PER_TILE_H7                       = 0xe5,
+       SC_P3_HIZ_QUAD_PER_TILE_H8                       = 0xe6,
+       SC_P3_HIZ_QUAD_PER_TILE_H9                       = 0xe7,
+       SC_P3_HIZ_QUAD_PER_TILE_H10                      = 0xe8,
+       SC_P3_HIZ_QUAD_PER_TILE_H11                      = 0xe9,
+       SC_P3_HIZ_QUAD_PER_TILE_H12                      = 0xea,
+       SC_P3_HIZ_QUAD_PER_TILE_H13                      = 0xeb,
+       SC_P3_HIZ_QUAD_PER_TILE_H14                      = 0xec,
+       SC_P3_HIZ_QUAD_PER_TILE_H15                      = 0xed,
+       SC_P3_HIZ_QUAD_PER_TILE_H16                      = 0xee,
+       SC_P0_HIZ_QUAD_COUNT                             = 0xef,
+       SC_P1_HIZ_QUAD_COUNT                             = 0xf0,
+       SC_P2_HIZ_QUAD_COUNT                             = 0xf1,
+       SC_P3_HIZ_QUAD_COUNT                             = 0xf2,
+       SC_P0_DETAIL_QUAD_COUNT                          = 0xf3,
+       SC_P1_DETAIL_QUAD_COUNT                          = 0xf4,
+       SC_P2_DETAIL_QUAD_COUNT                          = 0xf5,
+       SC_P3_DETAIL_QUAD_COUNT                          = 0xf6,
+       SC_P0_DETAIL_QUAD_WITH_1_PIX                     = 0xf7,
+       SC_P0_DETAIL_QUAD_WITH_2_PIX                     = 0xf8,
+       SC_P0_DETAIL_QUAD_WITH_3_PIX                     = 0xf9,
+       SC_P0_DETAIL_QUAD_WITH_4_PIX                     = 0xfa,
+       SC_P1_DETAIL_QUAD_WITH_1_PIX                     = 0xfb,
+       SC_P1_DETAIL_QUAD_WITH_2_PIX                     = 0xfc,
+       SC_P1_DETAIL_QUAD_WITH_3_PIX                     = 0xfd,
+       SC_P1_DETAIL_QUAD_WITH_4_PIX                     = 0xfe,
+       SC_P2_DETAIL_QUAD_WITH_1_PIX                     = 0xff,
+       SC_P2_DETAIL_QUAD_WITH_2_PIX                     = 0x100,
+       SC_P2_DETAIL_QUAD_WITH_3_PIX                     = 0x101,
+       SC_P2_DETAIL_QUAD_WITH_4_PIX                     = 0x102,
+       SC_P3_DETAIL_QUAD_WITH_1_PIX                     = 0x103,
+       SC_P3_DETAIL_QUAD_WITH_2_PIX                     = 0x104,
+       SC_P3_DETAIL_QUAD_WITH_3_PIX                     = 0x105,
+       SC_P3_DETAIL_QUAD_WITH_4_PIX                     = 0x106,
+       SC_EARLYZ_QUAD_COUNT                             = 0x107,
+       SC_EARLYZ_QUAD_WITH_1_PIX                        = 0x108,
+       SC_EARLYZ_QUAD_WITH_2_PIX                        = 0x109,
+       SC_EARLYZ_QUAD_WITH_3_PIX                        = 0x10a,
+       SC_EARLYZ_QUAD_WITH_4_PIX                        = 0x10b,
+       SC_PKR_QUAD_PER_ROW_H1                           = 0x10c,
+       SC_PKR_QUAD_PER_ROW_H2                           = 0x10d,
+       SC_PKR_QUAD_PER_ROW_H3                           = 0x10e,
+       SC_PKR_QUAD_PER_ROW_H4                           = 0x10f,
+       SC_PKR_END_OF_VECTOR                             = 0x110,
+       SC_PKR_CONTROL_XFER                              = 0x111,
+       SC_PKR_DBHANG_FORCE_EOV                          = 0x112,
+       SC_REG_SCLK_BUSY                                 = 0x113,
+       SC_GRP0_DYN_SCLK_BUSY                            = 0x114,
+       SC_GRP1_DYN_SCLK_BUSY                            = 0x115,
+       SC_GRP2_DYN_SCLK_BUSY                            = 0x116,
+       SC_GRP3_DYN_SCLK_BUSY                            = 0x117,
+       SC_GRP4_DYN_SCLK_BUSY                            = 0x118,
+       SC_PA0_SC_DATA_FIFO_RD                           = 0x119,
+       SC_PA0_SC_DATA_FIFO_WE                           = 0x11a,
+       SC_PA1_SC_DATA_FIFO_RD                           = 0x11b,
+       SC_PA1_SC_DATA_FIFO_WE                           = 0x11c,
+       SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES           = 0x11d,
+       SC_PS_ARB_XFC_ONLY_PRIM_CYCLES                   = 0x11e,
+       SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM              = 0x11f,
+       SC_PS_ARB_STALLED_FROM_BELOW                     = 0x120,
+       SC_PS_ARB_STARVED_FROM_ABOVE                     = 0x121,
+       SC_PS_ARB_SC_BUSY                                = 0x122,
+       SC_PS_ARB_PA_SC_BUSY                             = 0x123,
+       SC_PA2_SC_DATA_FIFO_RD                           = 0x124,
+       SC_PA2_SC_DATA_FIFO_WE                           = 0x125,
+       SC_PA3_SC_DATA_FIFO_RD                           = 0x126,
+       SC_PA3_SC_DATA_FIFO_WE                           = 0x127,
+       SC_PA_SC_DEALLOC_0_0_WE                          = 0x128,
+       SC_PA_SC_DEALLOC_0_1_WE                          = 0x129,
+       SC_PA_SC_DEALLOC_1_0_WE                          = 0x12a,
+       SC_PA_SC_DEALLOC_1_1_WE                          = 0x12b,
+       SC_PA_SC_DEALLOC_2_0_WE                          = 0x12c,
+       SC_PA_SC_DEALLOC_2_1_WE                          = 0x12d,
+       SC_PA_SC_DEALLOC_3_0_WE                          = 0x12e,
+       SC_PA_SC_DEALLOC_3_1_WE                          = 0x12f,
+       SC_PA0_SC_EOP_WE                                 = 0x130,
+       SC_PA0_SC_EOPG_WE                                = 0x131,
+       SC_PA0_SC_EVENT_WE                               = 0x132,
+       SC_PA1_SC_EOP_WE                                 = 0x133,
+       SC_PA1_SC_EOPG_WE                                = 0x134,
+       SC_PA1_SC_EVENT_WE                               = 0x135,
+       SC_PA2_SC_EOP_WE                                 = 0x136,
+       SC_PA2_SC_EOPG_WE                                = 0x137,
+       SC_PA2_SC_EVENT_WE                               = 0x138,
+       SC_PA3_SC_EOP_WE                                 = 0x139,
+       SC_PA3_SC_EOPG_WE                                = 0x13a,
+       SC_PA3_SC_EVENT_WE                               = 0x13b,
+       SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO   = 0x13c,
+       SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH                  = 0x13d,
+       SC_PS_ARB_NULL_PRIM_BUBBLE_POP                   = 0x13e,
+       SC_PS_ARB_EOP_POP_SYNC_POP                       = 0x13f,
+       SC_PS_ARB_EVENT_SYNC_POP                         = 0x140,
+       SC_SC_PS_ENG_MULTICYCLE_BUBBLE                   = 0x141,
+       SC_PA0_SC_FPOV_WE                                = 0x142,
+       SC_PA1_SC_FPOV_WE                                = 0x143,
+       SC_PA2_SC_FPOV_WE                                = 0x144,
+       SC_PA3_SC_FPOV_WE                                = 0x145,
+       SC_PA0_SC_LPOV_WE                                = 0x146,
+       SC_PA1_SC_LPOV_WE                                = 0x147,
+       SC_PA2_SC_LPOV_WE                                = 0x148,
+       SC_PA3_SC_LPOV_WE                                = 0x149,
+       SC_SC_SPI_DEALLOC_0_0                            = 0x14a,
+       SC_SC_SPI_DEALLOC_0_1                            = 0x14b,
+       SC_SC_SPI_DEALLOC_0_2                            = 0x14c,
+       SC_SC_SPI_DEALLOC_1_0                            = 0x14d,
+       SC_SC_SPI_DEALLOC_1_1                            = 0x14e,
+       SC_SC_SPI_DEALLOC_1_2                            = 0x14f,
+       SC_SC_SPI_DEALLOC_2_0                            = 0x150,
+       SC_SC_SPI_DEALLOC_2_1                            = 0x151,
+       SC_SC_SPI_DEALLOC_2_2                            = 0x152,
+       SC_SC_SPI_DEALLOC_3_0                            = 0x153,
+       SC_SC_SPI_DEALLOC_3_1                            = 0x154,
+       SC_SC_SPI_DEALLOC_3_2                            = 0x155,
+       SC_SC_SPI_FPOV_0                                 = 0x156,
+       SC_SC_SPI_FPOV_1                                 = 0x157,
+       SC_SC_SPI_FPOV_2                                 = 0x158,
+       SC_SC_SPI_FPOV_3                                 = 0x159,
+       SC_SC_SPI_EVENT                                  = 0x15a,
+       SC_PS_TS_EVENT_FIFO_PUSH                         = 0x15b,
+       SC_PS_TS_EVENT_FIFO_POP                          = 0x15c,
+       SC_PS_CTX_DONE_FIFO_PUSH                         = 0x15d,
+       SC_PS_CTX_DONE_FIFO_POP                          = 0x15e,
+       SC_MULTICYCLE_BUBBLE_FREEZE                      = 0x15f,
+       SC_EOP_SYNC_WINDOW                               = 0x160,
+       SC_PA0_SC_NULL_WE                                = 0x161,
+       SC_PA0_SC_NULL_DEALLOC_WE                        = 0x162,
+       SC_PA0_SC_DATA_FIFO_EOPG_RD                      = 0x163,
+       SC_PA0_SC_DATA_FIFO_EOP_RD                       = 0x164,
+       SC_PA0_SC_DEALLOC_0_RD                           = 0x165,
+       SC_PA0_SC_DEALLOC_1_RD                           = 0x166,
+       SC_PA1_SC_DATA_FIFO_EOPG_RD                      = 0x167,
+       SC_PA1_SC_DATA_FIFO_EOP_RD                       = 0x168,
+       SC_PA1_SC_DEALLOC_0_RD                           = 0x169,
+       SC_PA1_SC_DEALLOC_1_RD                           = 0x16a,
+       SC_PA1_SC_NULL_WE                                = 0x16b,
+       SC_PA1_SC_NULL_DEALLOC_WE                        = 0x16c,
+       SC_PA2_SC_DATA_FIFO_EOPG_RD                      = 0x16d,
+       SC_PA2_SC_DATA_FIFO_EOP_RD                       = 0x16e,
+       SC_PA2_SC_DEALLOC_0_RD                           = 0x16f,
+       SC_PA2_SC_DEALLOC_1_RD                           = 0x170,
+       SC_PA2_SC_NULL_WE                                = 0x171,
+       SC_PA2_SC_NULL_DEALLOC_WE                        = 0x172,
+       SC_PA3_SC_DATA_FIFO_EOPG_RD                      = 0x173,
+       SC_PA3_SC_DATA_FIFO_EOP_RD                       = 0x174,
+       SC_PA3_SC_DEALLOC_0_RD                           = 0x175,
+       SC_PA3_SC_DEALLOC_1_RD                           = 0x176,
+       SC_PA3_SC_NULL_WE                                = 0x177,
+       SC_PA3_SC_NULL_DEALLOC_WE                        = 0x178,
+       SC_PS_PA0_SC_FIFO_EMPTY                          = 0x179,
+       SC_PS_PA0_SC_FIFO_FULL                           = 0x17a,
+       SC_PA0_PS_DATA_SEND                              = 0x17b,
+       SC_PS_PA1_SC_FIFO_EMPTY                          = 0x17c,
+       SC_PS_PA1_SC_FIFO_FULL                           = 0x17d,
+       SC_PA1_PS_DATA_SEND                              = 0x17e,
+       SC_PS_PA2_SC_FIFO_EMPTY                          = 0x17f,
+       SC_PS_PA2_SC_FIFO_FULL                           = 0x180,
+       SC_PA2_PS_DATA_SEND                              = 0x181,
+       SC_PS_PA3_SC_FIFO_EMPTY                          = 0x182,
+       SC_PS_PA3_SC_FIFO_FULL                           = 0x183,
+       SC_PA3_PS_DATA_SEND                              = 0x184,
+       SC_BUSY_PROCESSING_MULTICYCLE_PRIM               = 0x185,
+       SC_BUSY_CNT_NOT_ZERO                             = 0x186,
+       SC_BM_BUSY                                       = 0x187,
+       SC_BACKEND_BUSY                                  = 0x188,
+       SC_SCF_SCB_INTERFACE_BUSY                        = 0x189,
+       SC_SCB_BUSY                                      = 0x18a,
+       SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY    = 0x18b,
+       SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL         = 0x18c,
+} SC_PERFCNT_SEL;
+typedef enum SePairXsel {
+       RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE           = 0x0,
+       RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE          = 0x1,
+       RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE          = 0x2,
+       RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE          = 0x3,
+} SePairXsel;
+typedef enum SePairYsel {
+       RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE           = 0x0,
+       RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE          = 0x1,
+       RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE          = 0x2,
+       RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE          = 0x3,
+} SePairYsel;
+typedef enum SePairMap {
+       RASTER_CONFIG_SE_PAIR_MAP_0                      = 0x0,
+       RASTER_CONFIG_SE_PAIR_MAP_1                      = 0x1,
+       RASTER_CONFIG_SE_PAIR_MAP_2                      = 0x2,
+       RASTER_CONFIG_SE_PAIR_MAP_3                      = 0x3,
+} SePairMap;
+typedef enum SeXsel {
+       RASTER_CONFIG_SE_XSEL_8_WIDE_TILE                = 0x0,
+       RASTER_CONFIG_SE_XSEL_16_WIDE_TILE               = 0x1,
+       RASTER_CONFIG_SE_XSEL_32_WIDE_TILE               = 0x2,
+       RASTER_CONFIG_SE_XSEL_64_WIDE_TILE               = 0x3,
+} SeXsel;
+typedef enum SeYsel {
+       RASTER_CONFIG_SE_YSEL_8_WIDE_TILE                = 0x0,
+       RASTER_CONFIG_SE_YSEL_16_WIDE_TILE               = 0x1,
+       RASTER_CONFIG_SE_YSEL_32_WIDE_TILE               = 0x2,
+       RASTER_CONFIG_SE_YSEL_64_WIDE_TILE               = 0x3,
+} SeYsel;
+typedef enum SeMap {
+       RASTER_CONFIG_SE_MAP_0                           = 0x0,
+       RASTER_CONFIG_SE_MAP_1                           = 0x1,
+       RASTER_CONFIG_SE_MAP_2                           = 0x2,
+       RASTER_CONFIG_SE_MAP_3                           = 0x3,
+} SeMap;
+typedef enum ScXsel {
+       RASTER_CONFIG_SC_XSEL_8_WIDE_TILE                = 0x0,
+       RASTER_CONFIG_SC_XSEL_16_WIDE_TILE               = 0x1,
+       RASTER_CONFIG_SC_XSEL_32_WIDE_TILE               = 0x2,
+       RASTER_CONFIG_SC_XSEL_64_WIDE_TILE               = 0x3,
+} ScXsel;
+typedef enum ScYsel {
+       RASTER_CONFIG_SC_YSEL_8_WIDE_TILE                = 0x0,
+       RASTER_CONFIG_SC_YSEL_16_WIDE_TILE               = 0x1,
+       RASTER_CONFIG_SC_YSEL_32_WIDE_TILE               = 0x2,
+       RASTER_CONFIG_SC_YSEL_64_WIDE_TILE               = 0x3,
+} ScYsel;
+typedef enum ScMap {
+       RASTER_CONFIG_SC_MAP_0                           = 0x0,
+       RASTER_CONFIG_SC_MAP_1                           = 0x1,
+       RASTER_CONFIG_SC_MAP_2                           = 0x2,
+       RASTER_CONFIG_SC_MAP_3                           = 0x3,
+} ScMap;
+typedef enum PkrXsel2 {
+       RASTER_CONFIG_PKR_XSEL2_0                        = 0x0,
+       RASTER_CONFIG_PKR_XSEL2_1                        = 0x1,
+       RASTER_CONFIG_PKR_XSEL2_2                        = 0x2,
+       RASTER_CONFIG_PKR_XSEL2_3                        = 0x3,
+} PkrXsel2;
+typedef enum PkrXsel {
+       RASTER_CONFIG_PKR_XSEL_0                         = 0x0,
+       RASTER_CONFIG_PKR_XSEL_1                         = 0x1,
+       RASTER_CONFIG_PKR_XSEL_2                         = 0x2,
+       RASTER_CONFIG_PKR_XSEL_3                         = 0x3,
+} PkrXsel;
+typedef enum PkrYsel {
+       RASTER_CONFIG_PKR_YSEL_0                         = 0x0,
+       RASTER_CONFIG_PKR_YSEL_1                         = 0x1,
+       RASTER_CONFIG_PKR_YSEL_2                         = 0x2,
+       RASTER_CONFIG_PKR_YSEL_3                         = 0x3,
+} PkrYsel;
+typedef enum PkrMap {
+       RASTER_CONFIG_PKR_MAP_0                          = 0x0,
+       RASTER_CONFIG_PKR_MAP_1                          = 0x1,
+       RASTER_CONFIG_PKR_MAP_2                          = 0x2,
+       RASTER_CONFIG_PKR_MAP_3                          = 0x3,
+} PkrMap;
+typedef enum RbXsel {
+       RASTER_CONFIG_RB_XSEL_0                          = 0x0,
+       RASTER_CONFIG_RB_XSEL_1                          = 0x1,
+} RbXsel;
+typedef enum RbYsel {
+       RASTER_CONFIG_RB_YSEL_0                          = 0x0,
+       RASTER_CONFIG_RB_YSEL_1                          = 0x1,
+} RbYsel;
+typedef enum RbXsel2 {
+       RASTER_CONFIG_RB_XSEL2_0                         = 0x0,
+       RASTER_CONFIG_RB_XSEL2_1                         = 0x1,
+       RASTER_CONFIG_RB_XSEL2_2                         = 0x2,
+       RASTER_CONFIG_RB_XSEL2_3                         = 0x3,
+} RbXsel2;
+typedef enum RbMap {
+       RASTER_CONFIG_RB_MAP_0                           = 0x0,
+       RASTER_CONFIG_RB_MAP_1                           = 0x1,
+       RASTER_CONFIG_RB_MAP_2                           = 0x2,
+       RASTER_CONFIG_RB_MAP_3                           = 0x3,
+} RbMap;
+typedef enum CSDATA_TYPE {
+       CSDATA_TYPE_TG                                   = 0x0,
+       CSDATA_TYPE_STATE                                = 0x1,
+       CSDATA_TYPE_EVENT                                = 0x2,
+       CSDATA_TYPE_PRIVATE                              = 0x3,
+} CSDATA_TYPE;
+#define CSDATA_TYPE_WIDTH                         0x2
+#define CSDATA_ADDR_WIDTH                         0x7
+#define CSDATA_DATA_WIDTH                         0x20
+typedef enum SPI_SAMPLE_CNTL {
+       CENTROIDS_ONLY                                   = 0x0,
+       CENTERS_ONLY                                     = 0x1,
+       CENTROIDS_AND_CENTERS                            = 0x2,
+       UNDEF                                            = 0x3,
+} SPI_SAMPLE_CNTL;
+typedef enum SPI_FOG_MODE {
+       SPI_FOG_NONE                                     = 0x0,
+       SPI_FOG_EXP                                      = 0x1,
+       SPI_FOG_EXP2                                     = 0x2,
+       SPI_FOG_LINEAR                                   = 0x3,
+} SPI_FOG_MODE;
+typedef enum SPI_PNT_SPRITE_OVERRIDE {
+       SPI_PNT_SPRITE_SEL_0                             = 0x0,
+       SPI_PNT_SPRITE_SEL_1                             = 0x1,
+       SPI_PNT_SPRITE_SEL_S                             = 0x2,
+       SPI_PNT_SPRITE_SEL_T                             = 0x3,
+       SPI_PNT_SPRITE_SEL_NONE                          = 0x4,
+} SPI_PNT_SPRITE_OVERRIDE;
+typedef enum SPI_PERFCNT_SEL {
+       SPI_PERF_VS_WINDOW_VALID                         = 0x0,
+       SPI_PERF_VS_BUSY                                 = 0x1,
+       SPI_PERF_VS_FIRST_WAVE                           = 0x2,
+       SPI_PERF_VS_LAST_WAVE                            = 0x3,
+       SPI_PERF_VS_LSHS_DEALLOC                         = 0x4,
+       SPI_PERF_VS_PC_STALL                             = 0x5,
+       SPI_PERF_VS_POS0_STALL                           = 0x6,
+       SPI_PERF_VS_POS1_STALL                           = 0x7,
+       SPI_PERF_VS_CRAWLER_STALL                        = 0x8,
+       SPI_PERF_VS_EVENT_WAVE                           = 0x9,
+       SPI_PERF_VS_WAVE                                 = 0xa,
+       SPI_PERF_VS_PERS_UPD_FULL0                       = 0xb,
+       SPI_PERF_VS_PERS_UPD_FULL1                       = 0xc,
+       SPI_PERF_VS_LATE_ALLOC_FULL                      = 0xd,
+       SPI_PERF_VS_FIRST_SUBGRP                         = 0xe,
+       SPI_PERF_VS_LAST_SUBGRP                          = 0xf,
+       SPI_PERF_GS_WINDOW_VALID                         = 0x10,
+       SPI_PERF_GS_BUSY                                 = 0x11,
+       SPI_PERF_GS_CRAWLER_STALL                        = 0x12,
+       SPI_PERF_GS_EVENT_WAVE                           = 0x13,
+       SPI_PERF_GS_WAVE                                 = 0x14,
+       SPI_PERF_GS_PERS_UPD_FULL0                       = 0x15,
+       SPI_PERF_GS_PERS_UPD_FULL1                       = 0x16,
+       SPI_PERF_GS_FIRST_SUBGRP                         = 0x17,
+       SPI_PERF_GS_LAST_SUBGRP                          = 0x18,
+       SPI_PERF_ES_WINDOW_VALID                         = 0x19,
+       SPI_PERF_ES_BUSY                                 = 0x1a,
+       SPI_PERF_ES_CRAWLER_STALL                        = 0x1b,
+       SPI_PERF_ES_FIRST_WAVE                           = 0x1c,
+       SPI_PERF_ES_LAST_WAVE                            = 0x1d,
+       SPI_PERF_ES_LSHS_DEALLOC                         = 0x1e,
+       SPI_PERF_ES_EVENT_WAVE                           = 0x1f,
+       SPI_PERF_ES_WAVE                                 = 0x20,
+       SPI_PERF_ES_PERS_UPD_FULL0                       = 0x21,
+       SPI_PERF_ES_PERS_UPD_FULL1                       = 0x22,
+       SPI_PERF_ES_FIRST_SUBGRP                         = 0x23,
+       SPI_PERF_ES_LAST_SUBGRP                          = 0x24,
+       SPI_PERF_HS_WINDOW_VALID                         = 0x25,
+       SPI_PERF_HS_BUSY                                 = 0x26,
+       SPI_PERF_HS_CRAWLER_STALL                        = 0x27,
+       SPI_PERF_HS_FIRST_WAVE                           = 0x28,
+       SPI_PERF_HS_LAST_WAVE                            = 0x29,
+       SPI_PERF_HS_LSHS_DEALLOC                         = 0x2a,
+       SPI_PERF_HS_EVENT_WAVE                           = 0x2b,
+       SPI_PERF_HS_WAVE                                 = 0x2c,
+       SPI_PERF_HS_PERS_UPD_FULL0                       = 0x2d,
+       SPI_PERF_HS_PERS_UPD_FULL1                       = 0x2e,
+       SPI_PERF_LS_WINDOW_VALID                         = 0x2f,
+       SPI_PERF_LS_BUSY                                 = 0x30,
+       SPI_PERF_LS_CRAWLER_STALL                        = 0x31,
+       SPI_PERF_LS_FIRST_WAVE                           = 0x32,
+       SPI_PERF_LS_LAST_WAVE                            = 0x33,
+       SPI_PERF_OFFCHIP_LDS_STALL_LS                    = 0x34,
+       SPI_PERF_LS_EVENT_WAVE                           = 0x35,
+       SPI_PERF_LS_WAVE                                 = 0x36,
+       SPI_PERF_LS_PERS_UPD_FULL0                       = 0x37,
+       SPI_PERF_LS_PERS_UPD_FULL1                       = 0x38,
+       SPI_PERF_CSG_WINDOW_VALID                        = 0x39,
+       SPI_PERF_CSG_BUSY                                = 0x3a,
+       SPI_PERF_CSG_NUM_THREADGROUPS                    = 0x3b,
+       SPI_PERF_CSG_CRAWLER_STALL                       = 0x3c,
+       SPI_PERF_CSG_EVENT_WAVE                          = 0x3d,
+       SPI_PERF_CSG_WAVE                                = 0x3e,
+       SPI_PERF_CSN_WINDOW_VALID                        = 0x3f,
+       SPI_PERF_CSN_BUSY                                = 0x40,
+       SPI_PERF_CSN_NUM_THREADGROUPS                    = 0x41,
+       SPI_PERF_CSN_CRAWLER_STALL                       = 0x42,
+       SPI_PERF_CSN_EVENT_WAVE                          = 0x43,
+       SPI_PERF_CSN_WAVE                                = 0x44,
+       SPI_PERF_PS_CTL_WINDOW_VALID                     = 0x45,
+       SPI_PERF_PS_CTL_BUSY                             = 0x46,
+       SPI_PERF_PS_CTL_ACTIVE                           = 0x47,
+       SPI_PERF_PS_CTL_DEALLOC_BIN0                     = 0x48,
+       SPI_PERF_PS_CTL_FPOS_BIN1_STALL                  = 0x49,
+       SPI_PERF_PS_CTL_EVENT_WAVE                       = 0x4a,
+       SPI_PERF_PS_CTL_WAVE                             = 0x4b,
+       SPI_PERF_PS_CTL_OPT_WAVE                         = 0x4c,
+       SPI_PERF_PS_CTL_PASS_BIN0                        = 0x4d,
+       SPI_PERF_PS_CTL_PASS_BIN1                        = 0x4e,
+       SPI_PERF_PS_CTL_FPOS_BIN2                        = 0x4f,
+       SPI_PERF_PS_CTL_PRIM_BIN0                        = 0x50,
+       SPI_PERF_PS_CTL_PRIM_BIN1                        = 0x51,
+       SPI_PERF_PS_CTL_CNF_BIN2                         = 0x52,
+       SPI_PERF_PS_CTL_CNF_BIN3                         = 0x53,
+       SPI_PERF_PS_CTL_CRAWLER_STALL                    = 0x54,
+       SPI_PERF_PS_CTL_LDS_RES_FULL                     = 0x55,
+       SPI_PERF_PS_PERS_UPD_FULL0                       = 0x56,
+       SPI_PERF_PS_PERS_UPD_FULL1                       = 0x57,
+       SPI_PERF_PIX_ALLOC_PEND_CNT                      = 0x58,
+       SPI_PERF_PIX_ALLOC_SCB_STALL                     = 0x59,
+       SPI_PERF_PIX_ALLOC_DB0_STALL                     = 0x5a,
+       SPI_PERF_PIX_ALLOC_DB1_STALL                     = 0x5b,
+       SPI_PERF_PIX_ALLOC_DB2_STALL                     = 0x5c,
+       SPI_PERF_PIX_ALLOC_DB3_STALL                     = 0x5d,
+       SPI_PERF_LDS0_PC_VALID                           = 0x5e,
+       SPI_PERF_LDS1_PC_VALID                           = 0x5f,
+       SPI_PERF_RA_PIPE_REQ_BIN2                        = 0x60,
+       SPI_PERF_RA_TASK_REQ_BIN3                        = 0x61,
+       SPI_PERF_RA_WR_CTL_FULL                          = 0x62,
+       SPI_PERF_RA_REQ_NO_ALLOC                         = 0x63,
+       SPI_PERF_RA_REQ_NO_ALLOC_PS                      = 0x64,
+       SPI_PERF_RA_REQ_NO_ALLOC_VS                      = 0x65,
+       SPI_PERF_RA_REQ_NO_ALLOC_GS                      = 0x66,
+       SPI_PERF_RA_REQ_NO_ALLOC_ES                      = 0x67,
+       SPI_PERF_RA_REQ_NO_ALLOC_HS                      = 0x68,
+       SPI_PERF_RA_REQ_NO_ALLOC_LS                      = 0x69,
+       SPI_PERF_RA_REQ_NO_ALLOC_CSG                     = 0x6a,
+       SPI_PERF_RA_REQ_NO_ALLOC_CSN                     = 0x6b,
+       SPI_PERF_RA_RES_STALL_PS                         = 0x6c,
+       SPI_PERF_RA_RES_STALL_VS                         = 0x6d,
+       SPI_PERF_RA_RES_STALL_GS                         = 0x6e,
+       SPI_PERF_RA_RES_STALL_ES                         = 0x6f,
+       SPI_PERF_RA_RES_STALL_HS                         = 0x70,
+       SPI_PERF_RA_RES_STALL_LS                         = 0x71,
+       SPI_PERF_RA_RES_STALL_CSG                        = 0x72,
+       SPI_PERF_RA_RES_STALL_CSN                        = 0x73,
+       SPI_PERF_RA_TMP_STALL_PS                         = 0x74,
+       SPI_PERF_RA_TMP_STALL_VS                         = 0x75,
+       SPI_PERF_RA_TMP_STALL_GS                         = 0x76,
+       SPI_PERF_RA_TMP_STALL_ES                         = 0x77,
+       SPI_PERF_RA_TMP_STALL_HS                         = 0x78,
+       SPI_PERF_RA_TMP_STALL_LS                         = 0x79,
+       SPI_PERF_RA_TMP_STALL_CSG                        = 0x7a,
+       SPI_PERF_RA_TMP_STALL_CSN                        = 0x7b,
+       SPI_PERF_RA_WAVE_SIMD_FULL_PS                    = 0x7c,
+       SPI_PERF_RA_WAVE_SIMD_FULL_VS                    = 0x7d,
+       SPI_PERF_RA_WAVE_SIMD_FULL_GS                    = 0x7e,
+       SPI_PERF_RA_WAVE_SIMD_FULL_ES                    = 0x7f,
+       SPI_PERF_RA_WAVE_SIMD_FULL_HS                    = 0x80,
+       SPI_PERF_RA_WAVE_SIMD_FULL_LS                    = 0x81,
+       SPI_PERF_RA_WAVE_SIMD_FULL_CSG                   = 0x82,
+       SPI_PERF_RA_WAVE_SIMD_FULL_CSN                   = 0x83,
+       SPI_PERF_RA_VGPR_SIMD_FULL_PS                    = 0x84,
+       SPI_PERF_RA_VGPR_SIMD_FULL_VS                    = 0x85,
+       SPI_PERF_RA_VGPR_SIMD_FULL_GS                    = 0x86,
+       SPI_PERF_RA_VGPR_SIMD_FULL_ES                    = 0x87,
+       SPI_PERF_RA_VGPR_SIMD_FULL_HS                    = 0x88,
+       SPI_PERF_RA_VGPR_SIMD_FULL_LS                    = 0x89,
+       SPI_PERF_RA_VGPR_SIMD_FULL_CSG                   = 0x8a,
+       SPI_PERF_RA_VGPR_SIMD_FULL_CSN                   = 0x8b,
+       SPI_PERF_RA_SGPR_SIMD_FULL_PS                    = 0x8c,
+       SPI_PERF_RA_SGPR_SIMD_FULL_VS                    = 0x8d,
+       SPI_PERF_RA_SGPR_SIMD_FULL_GS                    = 0x8e,
+       SPI_PERF_RA_SGPR_SIMD_FULL_ES                    = 0x8f,
+       SPI_PERF_RA_SGPR_SIMD_FULL_HS                    = 0x90,
+       SPI_PERF_RA_SGPR_SIMD_FULL_LS                    = 0x91,
+       SPI_PERF_RA_SGPR_SIMD_FULL_CSG                   = 0x92,
+       SPI_PERF_RA_SGPR_SIMD_FULL_CSN                   = 0x93,
+       SPI_PERF_RA_LDS_CU_FULL_PS                       = 0x94,
+       SPI_PERF_RA_LDS_CU_FULL_LS                       = 0x95,
+       SPI_PERF_RA_LDS_CU_FULL_ES                       = 0x96,
+       SPI_PERF_RA_LDS_CU_FULL_CSG                      = 0x97,
+       SPI_PERF_RA_LDS_CU_FULL_CSN                      = 0x98,
+       SPI_PERF_RA_BAR_CU_FULL_HS                       = 0x99,
+       SPI_PERF_RA_BAR_CU_FULL_CSG                      = 0x9a,
+       SPI_PERF_RA_BAR_CU_FULL_CSN                      = 0x9b,
+       SPI_PERF_RA_BULKY_CU_FULL_CSG                    = 0x9c,
+       SPI_PERF_RA_BULKY_CU_FULL_CSN                    = 0x9d,
+       SPI_PERF_RA_TGLIM_CU_FULL_CSG                    = 0x9e,
+       SPI_PERF_RA_TGLIM_CU_FULL_CSN                    = 0x9f,
+       SPI_PERF_RA_WVLIM_STALL_PS                       = 0xa0,
+       SPI_PERF_RA_WVLIM_STALL_VS                       = 0xa1,
+       SPI_PERF_RA_WVLIM_STALL_GS                       = 0xa2,
+       SPI_PERF_RA_WVLIM_STALL_ES                       = 0xa3,
+       SPI_PERF_RA_WVLIM_STALL_HS                       = 0xa4,
+       SPI_PERF_RA_WVLIM_STALL_LS                       = 0xa5,
+       SPI_PERF_RA_WVLIM_STALL_CSG                      = 0xa6,
+       SPI_PERF_RA_WVLIM_STALL_CSN                      = 0xa7,
+       SPI_PERF_RA_PS_LOCK_NA                           = 0xa8,
+       SPI_PERF_RA_VS_LOCK                              = 0xa9,
+       SPI_PERF_RA_GS_LOCK                              = 0xaa,
+       SPI_PERF_RA_ES_LOCK                              = 0xab,
+       SPI_PERF_RA_HS_LOCK                              = 0xac,
+       SPI_PERF_RA_LS_LOCK                              = 0xad,
+       SPI_PERF_RA_CSG_LOCK                             = 0xae,
+       SPI_PERF_RA_CSN_LOCK                             = 0xaf,
+       SPI_PERF_RA_RSV_UPD                              = 0xb0,
+       SPI_PERF_EXP_ARB_COL_CNT                         = 0xb1,
+       SPI_PERF_EXP_ARB_PAR_CNT                         = 0xb2,
+       SPI_PERF_EXP_ARB_POS_CNT                         = 0xb3,
+       SPI_PERF_EXP_ARB_GDS_CNT                         = 0xb4,
+       SPI_PERF_CLKGATE_BUSY_STALL                      = 0xb5,
+       SPI_PERF_CLKGATE_ACTIVE_STALL                    = 0xb6,
+       SPI_PERF_CLKGATE_ALL_CLOCKS_ON                   = 0xb7,
+       SPI_PERF_CLKGATE_CGTT_DYN_ON                     = 0xb8,
+       SPI_PERF_CLKGATE_CGTT_REG_ON                     = 0xb9,
+       SPI_PERF_NUM_VS_POS_EXPORTS                      = 0xba,
+       SPI_PERF_NUM_VS_PARAM_EXPORTS                    = 0xbb,
+       SPI_PERF_NUM_PS_COL_EXPORTS                      = 0xbc,
+       SPI_PERF_ES_GRP_FIFO_FULL                        = 0xbd,
+       SPI_PERF_GS_GRP_FIFO_FULL                        = 0xbe,
+       SPI_PERF_HS_GRP_FIFO_FULL                        = 0xbf,
+       SPI_PERF_LS_GRP_FIFO_FULL                        = 0xc0,
+       SPI_PERF_VS_ALLOC_CNT                            = 0xc1,
+       SPI_PERF_VS_LATE_ALLOC_ACCUM                     = 0xc2,
+       SPI_PERF_PC_ALLOC_CNT                            = 0xc3,
+       SPI_PERF_PC_ALLOC_ACCUM                          = 0xc4,
+} SPI_PERFCNT_SEL;
+typedef enum SPI_SHADER_FORMAT {
+       SPI_SHADER_NONE                                  = 0x0,
+       SPI_SHADER_1COMP                                 = 0x1,
+       SPI_SHADER_2COMP                                 = 0x2,
+       SPI_SHADER_4COMPRESS                             = 0x3,
+       SPI_SHADER_4COMP                                 = 0x4,
+} SPI_SHADER_FORMAT;
+typedef enum SPI_SHADER_EX_FORMAT {
+       SPI_SHADER_ZERO                                  = 0x0,
+       SPI_SHADER_32_R                                  = 0x1,
+       SPI_SHADER_32_GR                                 = 0x2,
+       SPI_SHADER_32_AR                                 = 0x3,
+       SPI_SHADER_FP16_ABGR                             = 0x4,
+       SPI_SHADER_UNORM16_ABGR                          = 0x5,
+       SPI_SHADER_SNORM16_ABGR                          = 0x6,
+       SPI_SHADER_UINT16_ABGR                           = 0x7,
+       SPI_SHADER_SINT16_ABGR                           = 0x8,
+       SPI_SHADER_32_ABGR                               = 0x9,
+} SPI_SHADER_EX_FORMAT;
+typedef enum CLKGATE_SM_MODE {
+       ON_SEQ                                           = 0x0,
+       OFF_SEQ                                          = 0x1,
+       PROG_SEQ                                         = 0x2,
+       READ_SEQ                                         = 0x3,
+       SM_MODE_RESERVED                                 = 0x4,
+} CLKGATE_SM_MODE;
+typedef enum CLKGATE_BASE_MODE {
+       MULT_8                                           = 0x0,
+       MULT_16                                          = 0x1,
+} CLKGATE_BASE_MODE;
+typedef enum SQ_TEX_CLAMP {
+       SQ_TEX_WRAP                                      = 0x0,
+       SQ_TEX_MIRROR                                    = 0x1,
+       SQ_TEX_CLAMP_LAST_TEXEL                          = 0x2,
+       SQ_TEX_MIRROR_ONCE_LAST_TEXEL                    = 0x3,
+       SQ_TEX_CLAMP_HALF_BORDER                         = 0x4,
+       SQ_TEX_MIRROR_ONCE_HALF_BORDER                   = 0x5,
+       SQ_TEX_CLAMP_BORDER                              = 0x6,
+       SQ_TEX_MIRROR_ONCE_BORDER                        = 0x7,
+} SQ_TEX_CLAMP;
+typedef enum SQ_TEX_XY_FILTER {
+       SQ_TEX_XY_FILTER_POINT                           = 0x0,
+       SQ_TEX_XY_FILTER_BILINEAR                        = 0x1,
+       SQ_TEX_XY_FILTER_ANISO_POINT                     = 0x2,
+       SQ_TEX_XY_FILTER_ANISO_BILINEAR                  = 0x3,
+} SQ_TEX_XY_FILTER;
+typedef enum SQ_TEX_Z_FILTER {
+       SQ_TEX_Z_FILTER_NONE                             = 0x0,
+       SQ_TEX_Z_FILTER_POINT                            = 0x1,
+       SQ_TEX_Z_FILTER_LINEAR                           = 0x2,
+} SQ_TEX_Z_FILTER;
+typedef enum SQ_TEX_MIP_FILTER {
+       SQ_TEX_MIP_FILTER_NONE                           = 0x0,
+       SQ_TEX_MIP_FILTER_POINT                          = 0x1,
+       SQ_TEX_MIP_FILTER_LINEAR                         = 0x2,
+       SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ                = 0x3,
+} SQ_TEX_MIP_FILTER;
+typedef enum SQ_TEX_ANISO_RATIO {
+       SQ_TEX_ANISO_RATIO_1                             = 0x0,
+       SQ_TEX_ANISO_RATIO_2                             = 0x1,
+       SQ_TEX_ANISO_RATIO_4                             = 0x2,
+       SQ_TEX_ANISO_RATIO_8                             = 0x3,
+       SQ_TEX_ANISO_RATIO_16                            = 0x4,
+} SQ_TEX_ANISO_RATIO;
+typedef enum SQ_TEX_DEPTH_COMPARE {
+       SQ_TEX_DEPTH_COMPARE_NEVER                       = 0x0,
+       SQ_TEX_DEPTH_COMPARE_LESS                        = 0x1,
+       SQ_TEX_DEPTH_COMPARE_EQUAL                       = 0x2,
+       SQ_TEX_DEPTH_COMPARE_LESSEQUAL                   = 0x3,
+       SQ_TEX_DEPTH_COMPARE_GREATER                     = 0x4,
+       SQ_TEX_DEPTH_COMPARE_NOTEQUAL                    = 0x5,
+       SQ_TEX_DEPTH_COMPARE_GREATEREQUAL                = 0x6,
+       SQ_TEX_DEPTH_COMPARE_ALWAYS                      = 0x7,
+} SQ_TEX_DEPTH_COMPARE;
+typedef enum SQ_TEX_BORDER_COLOR {
+       SQ_TEX_BORDER_COLOR_TRANS_BLACK                  = 0x0,
+       SQ_TEX_BORDER_COLOR_OPAQUE_BLACK                 = 0x1,
+       SQ_TEX_BORDER_COLOR_OPAQUE_WHITE                 = 0x2,
+       SQ_TEX_BORDER_COLOR_REGISTER                     = 0x3,
+} SQ_TEX_BORDER_COLOR;
+typedef enum SQ_RSRC_BUF_TYPE {
+       SQ_RSRC_BUF                                      = 0x0,
+       SQ_RSRC_BUF_RSVD_1                               = 0x1,
+       SQ_RSRC_BUF_RSVD_2                               = 0x2,
+       SQ_RSRC_BUF_RSVD_3                               = 0x3,
+} SQ_RSRC_BUF_TYPE;
+typedef enum SQ_RSRC_IMG_TYPE {
+       SQ_RSRC_IMG_RSVD_0                               = 0x0,
+       SQ_RSRC_IMG_RSVD_1                               = 0x1,
+       SQ_RSRC_IMG_RSVD_2                               = 0x2,
+       SQ_RSRC_IMG_RSVD_3                               = 0x3,
+       SQ_RSRC_IMG_RSVD_4                               = 0x4,
+       SQ_RSRC_IMG_RSVD_5                               = 0x5,
+       SQ_RSRC_IMG_RSVD_6                               = 0x6,
+       SQ_RSRC_IMG_RSVD_7                               = 0x7,
+       SQ_RSRC_IMG_1D                                   = 0x8,
+       SQ_RSRC_IMG_2D                                   = 0x9,
+       SQ_RSRC_IMG_3D                                   = 0xa,
+       SQ_RSRC_IMG_CUBE                                 = 0xb,
+       SQ_RSRC_IMG_1D_ARRAY                             = 0xc,
+       SQ_RSRC_IMG_2D_ARRAY                             = 0xd,
+       SQ_RSRC_IMG_2D_MSAA                              = 0xe,
+       SQ_RSRC_IMG_2D_MSAA_ARRAY                        = 0xf,
+} SQ_RSRC_IMG_TYPE;
+typedef enum SQ_RSRC_FLAT_TYPE {
+       SQ_RSRC_FLAT_RSVD_0                              = 0x0,
+       SQ_RSRC_FLAT                                     = 0x1,
+       SQ_RSRC_FLAT_RSVD_2                              = 0x2,
+       SQ_RSRC_FLAT_RSVD_3                              = 0x3,
+} SQ_RSRC_FLAT_TYPE;
+typedef enum SQ_IMG_FILTER_TYPE {
+       SQ_IMG_FILTER_MODE_BLEND                         = 0x0,
+       SQ_IMG_FILTER_MODE_MIN                           = 0x1,
+       SQ_IMG_FILTER_MODE_MAX                           = 0x2,
+} SQ_IMG_FILTER_TYPE;
+typedef enum SQ_SEL_XYZW01 {
+       SQ_SEL_0                                         = 0x0,
+       SQ_SEL_1                                         = 0x1,
+       SQ_SEL_RESERVED_0                                = 0x2,
+       SQ_SEL_RESERVED_1                                = 0x3,
+       SQ_SEL_X                                         = 0x4,
+       SQ_SEL_Y                                         = 0x5,
+       SQ_SEL_Z                                         = 0x6,
+       SQ_SEL_W                                         = 0x7,
+} SQ_SEL_XYZW01;
+typedef enum SQ_WAVE_TYPE {
+       SQ_WAVE_TYPE_PS                                  = 0x0,
+       SQ_WAVE_TYPE_VS                                  = 0x1,
+       SQ_WAVE_TYPE_GS                                  = 0x2,
+       SQ_WAVE_TYPE_ES                                  = 0x3,
+       SQ_WAVE_TYPE_HS                                  = 0x4,
+       SQ_WAVE_TYPE_LS                                  = 0x5,
+       SQ_WAVE_TYPE_CS                                  = 0x6,
+       SQ_WAVE_TYPE_PS1                                 = 0x7,
+} SQ_WAVE_TYPE;
+typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
+       SQ_THREAD_TRACE_TOKEN_MISC                       = 0x0,
+       SQ_THREAD_TRACE_TOKEN_TIMESTAMP                  = 0x1,
+       SQ_THREAD_TRACE_TOKEN_REG                        = 0x2,
+       SQ_THREAD_TRACE_TOKEN_WAVE_START                 = 0x3,
+       SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC                 = 0x4,
+       SQ_THREAD_TRACE_TOKEN_REG_CSPRIV                 = 0x5,
+       SQ_THREAD_TRACE_TOKEN_WAVE_END                   = 0x6,
+       SQ_THREAD_TRACE_TOKEN_EVENT                      = 0x7,
+       SQ_THREAD_TRACE_TOKEN_EVENT_CS                   = 0x8,
+       SQ_THREAD_TRACE_TOKEN_EVENT_GFX1                 = 0x9,
+       SQ_THREAD_TRACE_TOKEN_INST                       = 0xa,
+       SQ_THREAD_TRACE_TOKEN_INST_PC                    = 0xb,
+       SQ_THREAD_TRACE_TOKEN_INST_USERDATA              = 0xc,
+       SQ_THREAD_TRACE_TOKEN_ISSUE                      = 0xd,
+       SQ_THREAD_TRACE_TOKEN_PERF                       = 0xe,
+       SQ_THREAD_TRACE_TOKEN_REG_CS                     = 0xf,
+} SQ_THREAD_TRACE_TOKEN_TYPE;
+typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
+       SQ_THREAD_TRACE_MISC_TOKEN_TIME                  = 0x0,
+       SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET            = 0x1,
+       SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST           = 0x2,
+       SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC             = 0x3,
+       SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN    = 0x4,
+       SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END      = 0x5,
+       SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX               = 0x6,
+       SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN            = 0x7,
+} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
+typedef enum SQ_THREAD_TRACE_INST_TYPE {
+       SQ_THREAD_TRACE_INST_TYPE_SMEM_RD                = 0x0,
+       SQ_THREAD_TRACE_INST_TYPE_SALU_32                = 0x1,
+       SQ_THREAD_TRACE_INST_TYPE_VMEM_RD                = 0x2,
+       SQ_THREAD_TRACE_INST_TYPE_VMEM_WR                = 0x3,
+       SQ_THREAD_TRACE_INST_TYPE_FLAT_WR                = 0x4,
+       SQ_THREAD_TRACE_INST_TYPE_VALU_32                = 0x5,
+       SQ_THREAD_TRACE_INST_TYPE_LDS                    = 0x6,
+       SQ_THREAD_TRACE_INST_TYPE_PC                     = 0x7,
+       SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS             = 0x8,
+       SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX             = 0x9,
+       SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL         = 0xa,
+       SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS         = 0xb,
+       SQ_THREAD_TRACE_INST_TYPE_JUMP                   = 0xc,
+       SQ_THREAD_TRACE_INST_TYPE_NEXT                   = 0xd,
+       SQ_THREAD_TRACE_INST_TYPE_FLAT_RD                = 0xe,
+       SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG              = 0xf,
+       SQ_THREAD_TRACE_INST_TYPE_SMEM_WR                = 0x10,
+       SQ_THREAD_TRACE_INST_TYPE_SALU_64                = 0x11,
+       SQ_THREAD_TRACE_INST_TYPE_VALU_64                = 0x12,
+       SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY         = 0x13,
+       SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY         = 0x14,
+       SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY         = 0x15,
+       SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY         = 0x16,
+       SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY         = 0x17,
+       SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY         = 0x18,
+} SQ_THREAD_TRACE_INST_TYPE;
+typedef enum SQ_THREAD_TRACE_REG_TYPE {
+       SQ_THREAD_TRACE_REG_TYPE_EVENT                   = 0x0,
+       SQ_THREAD_TRACE_REG_TYPE_DRAW                    = 0x1,
+       SQ_THREAD_TRACE_REG_TYPE_DISPATCH                = 0x2,
+       SQ_THREAD_TRACE_REG_TYPE_USERDATA                = 0x3,
+       SQ_THREAD_TRACE_REG_TYPE_MARKER                  = 0x4,
+       SQ_THREAD_TRACE_REG_TYPE_GFXDEC                  = 0x5,
+       SQ_THREAD_TRACE_REG_TYPE_SHDEC                   = 0x6,
+       SQ_THREAD_TRACE_REG_TYPE_OTHER                   = 0x7,
+} SQ_THREAD_TRACE_REG_TYPE;
+typedef enum SQ_THREAD_TRACE_REG_OP {
+       SQ_THREAD_TRACE_REG_OP_READ                      = 0x0,
+       SQ_THREAD_TRACE_REG_OP_WRITE                     = 0x1,
+} SQ_THREAD_TRACE_REG_OP;
+typedef enum SQ_THREAD_TRACE_MODE_SEL {
+       SQ_THREAD_TRACE_MODE_OFF                         = 0x0,
+       SQ_THREAD_TRACE_MODE_ON                          = 0x1,
+} SQ_THREAD_TRACE_MODE_SEL;
+typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
+       SQ_THREAD_TRACE_CAPTURE_MODE_ALL                 = 0x0,
+       SQ_THREAD_TRACE_CAPTURE_MODE_SELECT              = 0x1,
+       SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL       = 0x2,
+} SQ_THREAD_TRACE_CAPTURE_MODE;
+typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
+       SQ_THREAD_TRACE_VM_ID_MASK_SINGLE                = 0x0,
+       SQ_THREAD_TRACE_VM_ID_MASK_ALL                   = 0x1,
+       SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL         = 0x2,
+} SQ_THREAD_TRACE_VM_ID_MASK;
+typedef enum SQ_THREAD_TRACE_WAVE_MASK {
+       SQ_THREAD_TRACE_WAVE_MASK_NONE                   = 0x0,
+       SQ_THREAD_TRACE_WAVE_MASK_ALL                    = 0x1,
+} SQ_THREAD_TRACE_WAVE_MASK;
+typedef enum SQ_THREAD_TRACE_ISSUE {
+       SQ_THREAD_TRACE_ISSUE_NULL                       = 0x0,
+       SQ_THREAD_TRACE_ISSUE_STALL                      = 0x1,
+       SQ_THREAD_TRACE_ISSUE_INST                       = 0x2,
+       SQ_THREAD_TRACE_ISSUE_IMMED                      = 0x3,
+} SQ_THREAD_TRACE_ISSUE;
+typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
+       SQ_THREAD_TRACE_ISSUE_MASK_ALL                   = 0x0,
+       SQ_THREAD_TRACE_ISSUE_MASK_STALLED               = 0x1,
+       SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED     = 0x2,
+       SQ_THREAD_TRACE_ISSUE_MASK_IMMED                 = 0x3,
+} SQ_THREAD_TRACE_ISSUE_MASK;
+typedef enum SQ_PERF_SEL {
+       SQ_PERF_SEL_NONE                                 = 0x0,
+       SQ_PERF_SEL_ACCUM_PREV                           = 0x1,
+       SQ_PERF_SEL_CYCLES                               = 0x2,
+       SQ_PERF_SEL_BUSY_CYCLES                          = 0x3,
+       SQ_PERF_SEL_WAVES                                = 0x4,
+       SQ_PERF_SEL_LEVEL_WAVES                          = 0x5,
+       SQ_PERF_SEL_WAVES_EQ_64                          = 0x6,
+       SQ_PERF_SEL_WAVES_LT_64                          = 0x7,
+       SQ_PERF_SEL_WAVES_LT_48                          = 0x8,
+       SQ_PERF_SEL_WAVES_LT_32                          = 0x9,
+       SQ_PERF_SEL_WAVES_LT_16                          = 0xa,
+       SQ_PERF_SEL_WAVES_CU                             = 0xb,
+       SQ_PERF_SEL_LEVEL_WAVES_CU                       = 0xc,
+       SQ_PERF_SEL_BUSY_CU_CYCLES                       = 0xd,
+       SQ_PERF_SEL_ITEMS                                = 0xe,
+       SQ_PERF_SEL_QUADS                                = 0xf,
+       SQ_PERF_SEL_EVENTS                               = 0x10,
+       SQ_PERF_SEL_SURF_SYNCS                           = 0x11,
+       SQ_PERF_SEL_TTRACE_REQS                          = 0x12,
+       SQ_PERF_SEL_TTRACE_INFLIGHT_REQS                 = 0x13,
+       SQ_PERF_SEL_TTRACE_STALL                         = 0x14,
+       SQ_PERF_SEL_MSG_CNTR                             = 0x15,
+       SQ_PERF_SEL_MSG_PERF                             = 0x16,
+       SQ_PERF_SEL_MSG_GSCNT                            = 0x17,
+       SQ_PERF_SEL_MSG_INTERRUPT                        = 0x18,
+       SQ_PERF_SEL_INSTS                                = 0x19,
+       SQ_PERF_SEL_INSTS_VALU                           = 0x1a,
+       SQ_PERF_SEL_INSTS_VMEM_WR                        = 0x1b,
+       SQ_PERF_SEL_INSTS_VMEM_RD                        = 0x1c,
+       SQ_PERF_SEL_INSTS_VMEM                           = 0x1d,
+       SQ_PERF_SEL_INSTS_SALU                           = 0x1e,
+       SQ_PERF_SEL_INSTS_SMEM                           = 0x1f,
+       SQ_PERF_SEL_INSTS_FLAT                           = 0x20,
+       SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY                  = 0x21,
+       SQ_PERF_SEL_INSTS_LDS                            = 0x22,
+       SQ_PERF_SEL_INSTS_GDS                            = 0x23,
+       SQ_PERF_SEL_INSTS_EXP                            = 0x24,
+       SQ_PERF_SEL_INSTS_EXP_GDS                        = 0x25,
+       SQ_PERF_SEL_INSTS_BRANCH                         = 0x26,
+       SQ_PERF_SEL_INSTS_SENDMSG                        = 0x27,
+       SQ_PERF_SEL_INSTS_VSKIPPED                       = 0x28,
+       SQ_PERF_SEL_INST_LEVEL_VMEM                      = 0x29,
+       SQ_PERF_SEL_INST_LEVEL_SMEM                      = 0x2a,
+       SQ_PERF_SEL_INST_LEVEL_LDS                       = 0x2b,
+       SQ_PERF_SEL_INST_LEVEL_GDS                       = 0x2c,
+       SQ_PERF_SEL_INST_LEVEL_EXP                       = 0x2d,
+       SQ_PERF_SEL_WAVE_CYCLES                          = 0x2e,
+       SQ_PERF_SEL_WAVE_READY                           = 0x2f,
+       SQ_PERF_SEL_WAIT_CNT_VM                          = 0x30,
+       SQ_PERF_SEL_WAIT_CNT_LGKM                        = 0x31,
+       SQ_PERF_SEL_WAIT_CNT_EXP                         = 0x32,
+       SQ_PERF_SEL_WAIT_CNT_ANY                         = 0x33,
+       SQ_PERF_SEL_WAIT_BARRIER                         = 0x34,
+       SQ_PERF_SEL_WAIT_EXP_ALLOC                       = 0x35,
+       SQ_PERF_SEL_WAIT_SLEEP                           = 0x36,
+       SQ_PERF_SEL_WAIT_OTHER                           = 0x37,
+       SQ_PERF_SEL_WAIT_ANY                             = 0x38,
+       SQ_PERF_SEL_WAIT_TTRACE                          = 0x39,
+       SQ_PERF_SEL_WAIT_IFETCH                          = 0x3a,
+       SQ_PERF_SEL_WAIT_INST_VMEM                       = 0x3b,
+       SQ_PERF_SEL_WAIT_INST_SCA                        = 0x3c,
+       SQ_PERF_SEL_WAIT_INST_LDS                        = 0x3d,
+       SQ_PERF_SEL_WAIT_INST_VALU                       = 0x3e,
+       SQ_PERF_SEL_WAIT_INST_EXP_GDS                    = 0x3f,
+       SQ_PERF_SEL_WAIT_INST_MISC                       = 0x40,
+       SQ_PERF_SEL_WAIT_INST_FLAT                       = 0x41,
+       SQ_PERF_SEL_ACTIVE_INST_ANY                      = 0x42,
+       SQ_PERF_SEL_ACTIVE_INST_VMEM                     = 0x43,
+       SQ_PERF_SEL_ACTIVE_INST_LDS                      = 0x44,
+       SQ_PERF_SEL_ACTIVE_INST_VALU                     = 0x45,
+       SQ_PERF_SEL_ACTIVE_INST_SCA                      = 0x46,
+       SQ_PERF_SEL_ACTIVE_INST_EXP_GDS                  = 0x47,
+       SQ_PERF_SEL_ACTIVE_INST_MISC                     = 0x48,
+       SQ_PERF_SEL_ACTIVE_INST_FLAT                     = 0x49,
+       SQ_PERF_SEL_INST_CYCLES_VMEM_WR                  = 0x4a,
+       SQ_PERF_SEL_INST_CYCLES_VMEM_RD                  = 0x4b,
+       SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR                = 0x4c,
+       SQ_PERF_SEL_INST_CYCLES_VMEM_DATA                = 0x4d,
+       SQ_PERF_SEL_INST_CYCLES_VMEM_CMD                 = 0x4e,
+       SQ_PERF_SEL_INST_CYCLES_VMEM                     = 0x4f,
+       SQ_PERF_SEL_INST_CYCLES_LDS                      = 0x50,
+       SQ_PERF_SEL_INST_CYCLES_VALU                     = 0x51,
+       SQ_PERF_SEL_INST_CYCLES_EXP                      = 0x52,
+       SQ_PERF_SEL_INST_CYCLES_GDS                      = 0x53,
+       SQ_PERF_SEL_INST_CYCLES_SCA                      = 0x54,
+       SQ_PERF_SEL_INST_CYCLES_SMEM                     = 0x55,
+       SQ_PERF_SEL_INST_CYCLES_SALU                     = 0x56,
+       SQ_PERF_SEL_INST_CYCLES_EXP_GDS                  = 0x57,
+       SQ_PERF_SEL_INST_CYCLES_MISC                     = 0x58,
+       SQ_PERF_SEL_THREAD_CYCLES_VALU                   = 0x59,
+       SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX               = 0x5a,
+       SQ_PERF_SEL_IFETCH                               = 0x5b,
+       SQ_PERF_SEL_IFETCH_LEVEL                         = 0x5c,
+       SQ_PERF_SEL_CBRANCH_FORK                         = 0x5d,
+       SQ_PERF_SEL_CBRANCH_FORK_SPLIT                   = 0x5e,
+       SQ_PERF_SEL_VALU_LDS_DIRECT_RD                   = 0x5f,
+       SQ_PERF_SEL_VALU_LDS_INTERP_OP                   = 0x60,
+       SQ_PERF_SEL_LDS_BANK_CONFLICT                    = 0x61,
+       SQ_PERF_SEL_LDS_ADDR_CONFLICT                    = 0x62,
+       SQ_PERF_SEL_LDS_UNALIGNED_STALL                  = 0x63,
+       SQ_PERF_SEL_LDS_MEM_VIOLATIONS                   = 0x64,
+       SQ_PERF_SEL_LDS_ATOMIC_RETURN                    = 0x65,
+       SQ_PERF_SEL_LDS_IDX_ACTIVE                       = 0x66,
+       SQ_PERF_SEL_VALU_DEP_STALL                       = 0x67,
+       SQ_PERF_SEL_VALU_STARVE                          = 0x68,
+       SQ_PERF_SEL_EXP_REQ_FIFO_FULL                    = 0x69,
+       SQ_PERF_SEL_LDS_BACK2BACK_STALL                  = 0x6a,
+       SQ_PERF_SEL_LDS_DATA_FIFO_FULL                   = 0x6b,
+       SQ_PERF_SEL_LDS_CMD_FIFO_FULL                    = 0x6c,
+       SQ_PERF_SEL_VMEM_BACK2BACK_STALL                 = 0x6d,
+       SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL               = 0x6e,
+       SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL                = 0x6f,
+       SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY                = 0x70,
+       SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL              = 0x71,
+       SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL            = 0x72,
+       SQ_PERF_SEL_VALU_SRC_C_CONFLICT                  = 0x73,
+       SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT              = 0x74,
+       SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT              = 0x75,
+       SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT                 = 0x76,
+       SQ_PERF_SEL_LDS_SRC_CD_CONFLICT                  = 0x77,
+       SQ_PERF_SEL_SRC_CD_BUSY                          = 0x78,
+       SQ_PERF_SEL_PT_POWER_STALL                       = 0x79,
+       SQ_PERF_SEL_USER0                                = 0x7a,
+       SQ_PERF_SEL_USER1                                = 0x7b,
+       SQ_PERF_SEL_USER2                                = 0x7c,
+       SQ_PERF_SEL_USER3                                = 0x7d,
+       SQ_PERF_SEL_USER4                                = 0x7e,
+       SQ_PERF_SEL_USER5                                = 0x7f,
+       SQ_PERF_SEL_USER6                                = 0x80,
+       SQ_PERF_SEL_USER7                                = 0x81,
+       SQ_PERF_SEL_USER8                                = 0x82,
+       SQ_PERF_SEL_USER9                                = 0x83,
+       SQ_PERF_SEL_USER10                               = 0x84,
+       SQ_PERF_SEL_USER11                               = 0x85,
+       SQ_PERF_SEL_USER12                               = 0x86,
+       SQ_PERF_SEL_USER13                               = 0x87,
+       SQ_PERF_SEL_USER14                               = 0x88,
+       SQ_PERF_SEL_USER15                               = 0x89,
+       SQ_PERF_SEL_USER_LEVEL0                          = 0x8a,
+       SQ_PERF_SEL_USER_LEVEL1                          = 0x8b,
+       SQ_PERF_SEL_USER_LEVEL2                          = 0x8c,
+       SQ_PERF_SEL_USER_LEVEL3                          = 0x8d,
+       SQ_PERF_SEL_USER_LEVEL4                          = 0x8e,
+       SQ_PERF_SEL_USER_LEVEL5                          = 0x8f,
+       SQ_PERF_SEL_USER_LEVEL6                          = 0x90,
+       SQ_PERF_SEL_USER_LEVEL7                          = 0x91,
+       SQ_PERF_SEL_USER_LEVEL8                          = 0x92,
+       SQ_PERF_SEL_USER_LEVEL9                          = 0x93,
+       SQ_PERF_SEL_USER_LEVEL10                         = 0x94,
+       SQ_PERF_SEL_USER_LEVEL11                         = 0x95,
+       SQ_PERF_SEL_USER_LEVEL12                         = 0x96,
+       SQ_PERF_SEL_USER_LEVEL13                         = 0x97,
+       SQ_PERF_SEL_USER_LEVEL14                         = 0x98,
+       SQ_PERF_SEL_USER_LEVEL15                         = 0x99,
+       SQ_PERF_SEL_POWER_VALU                           = 0x9a,
+       SQ_PERF_SEL_POWER_VALU0                          = 0x9b,
+       SQ_PERF_SEL_POWER_VALU1                          = 0x9c,
+       SQ_PERF_SEL_POWER_VALU2                          = 0x9d,
+       SQ_PERF_SEL_POWER_GPR_RD                         = 0x9e,
+       SQ_PERF_SEL_POWER_GPR_WR                         = 0x9f,
+       SQ_PERF_SEL_POWER_LDS_BUSY                       = 0xa0,
+       SQ_PERF_SEL_POWER_ALU_BUSY                       = 0xa1,
+       SQ_PERF_SEL_POWER_TEX_BUSY                       = 0xa2,
+       SQ_PERF_SEL_ACCUM_PREV_HIRES                     = 0xa3,
+       SQ_PERF_SEL_WAVES_RESTORED                       = 0xa4,
+       SQ_PERF_SEL_WAVES_SAVED                          = 0xa5,
+       SQ_PERF_SEL_DUMMY_LAST                           = 0xa7,
+       SQC_PERF_SEL_ICACHE_INPUT_VALID_READY            = 0xa8,
+       SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB           = 0xa9,
+       SQC_PERF_SEL_ICACHE_INPUT_VALIDB                 = 0xaa,
+       SQC_PERF_SEL_DCACHE_INPUT_VALID_READY            = 0xab,
+       SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB           = 0xac,
+       SQC_PERF_SEL_DCACHE_INPUT_VALIDB                 = 0xad,
+       SQC_PERF_SEL_TC_REQ                              = 0xae,
+       SQC_PERF_SEL_TC_INST_REQ                         = 0xaf,
+       SQC_PERF_SEL_TC_DATA_READ_REQ                    = 0xb0,
+       SQC_PERF_SEL_TC_DATA_WRITE_REQ                   = 0xb1,
+       SQC_PERF_SEL_TC_DATA_ATOMIC_REQ                  = 0xb2,
+       SQC_PERF_SEL_TC_STALL                            = 0xb3,
+       SQC_PERF_SEL_TC_STARVE                           = 0xb4,
+       SQC_PERF_SEL_ICACHE_BUSY_CYCLES                  = 0xb5,
+       SQC_PERF_SEL_ICACHE_REQ                          = 0xb6,
+       SQC_PERF_SEL_ICACHE_HITS                         = 0xb7,
+       SQC_PERF_SEL_ICACHE_MISSES                       = 0xb8,
+       SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE             = 0xb9,
+       SQC_PERF_SEL_ICACHE_INVAL_INST                   = 0xba,
+       SQC_PERF_SEL_ICACHE_INVAL_ASYNC                  = 0xbb,
+       SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT     = 0xbc,
+       SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB      = 0xbd,
+       SQC_PERF_SEL_ICACHE_CACHE_STALLED                = 0xbe,
+       SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf,
+       SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX     = 0xc0,
+       SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT           = 0xc1,
+       SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2,
+       SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xc3,
+       SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xc4,
+       SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xc5,
+       SQC_PERF_SEL_DCACHE_BUSY_CYCLES                  = 0xc6,
+       SQC_PERF_SEL_DCACHE_REQ                          = 0xc7,
+       SQC_PERF_SEL_DCACHE_HITS                         = 0xc8,
+       SQC_PERF_SEL_DCACHE_MISSES                       = 0xc9,
+       SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE             = 0xca,
+       SQC_PERF_SEL_DCACHE_HIT_LRU_READ                 = 0xcb,
+       SQC_PERF_SEL_DCACHE_MISS_EVICT_READ              = 0xcc,
+       SQC_PERF_SEL_DCACHE_WC_LRU_WRITE                 = 0xcd,
+       SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE               = 0xce,
+       SQC_PERF_SEL_DCACHE_ATOMIC                       = 0xcf,
+       SQC_PERF_SEL_DCACHE_VOLATILE                     = 0xd0,
+       SQC_PERF_SEL_DCACHE_INVAL_INST                   = 0xd1,
+       SQC_PERF_SEL_DCACHE_INVAL_ASYNC                  = 0xd2,
+       SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST          = 0xd3,
+       SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC         = 0xd4,
+       SQC_PERF_SEL_DCACHE_WB_INST                      = 0xd5,
+       SQC_PERF_SEL_DCACHE_WB_ASYNC                     = 0xd6,
+       SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST             = 0xd7,
+       SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC            = 0xd8,
+       SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT     = 0xd9,
+       SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB      = 0xda,
+       SQC_PERF_SEL_DCACHE_CACHE_STALLED                = 0xdb,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX     = 0xdc,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT           = 0xdd,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT            = 0xde,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED        = 0xdf,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT      = 0xe1,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH      = 0xe2,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE       = 0xe3,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xe5,
+       SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xe6,
+       SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xe7,
+       SQC_PERF_SEL_DCACHE_REQ_READ_1                   = 0xe8,
+       SQC_PERF_SEL_DCACHE_REQ_READ_2                   = 0xe9,
+       SQC_PERF_SEL_DCACHE_REQ_READ_4                   = 0xea,
+       SQC_PERF_SEL_DCACHE_REQ_READ_8                   = 0xeb,
+       SQC_PERF_SEL_DCACHE_REQ_READ_16                  = 0xec,
+       SQC_PERF_SEL_DCACHE_REQ_TIME                     = 0xed,
+       SQC_PERF_SEL_DCACHE_REQ_WRITE_1                  = 0xee,
+       SQC_PERF_SEL_DCACHE_REQ_WRITE_2                  = 0xef,
+       SQC_PERF_SEL_DCACHE_REQ_WRITE_4                  = 0xf0,
+       SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE                = 0xf1,
+       SQC_PERF_SEL_SQ_DCACHE_REQS                      = 0xf2,
+       SQC_PERF_SEL_DCACHE_FLAT_REQ                     = 0xf3,
+       SQC_PERF_SEL_DCACHE_NONFLAT_REQ                  = 0xf4,
+       SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL               = 0xf5,
+       SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL               = 0xf6,
+       SQC_PERF_SEL_TC_INFLIGHT_LEVEL                   = 0xf7,
+       SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL            = 0xf8,
+       SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL            = 0xf9,
+       SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS      = 0xfa,
+       SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS       = 0xfb,
+       SQC_PERF_SEL_ICACHE_GATCL1_REQUEST               = 0xfc,
+       SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX    = 0xfd,
+       SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT    = 0xfe,
+       SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL            = 0xff,
+       SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES   = 0x100,
+       SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101,
+       SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT        = 0x102,
+       SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL   = 0x103,
+       SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS      = 0x104,
+       SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS       = 0x105,
+       SQC_PERF_SEL_DCACHE_GATCL1_REQUEST               = 0x106,
+       SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX    = 0x107,
+       SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT    = 0x108,
+       SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL            = 0x109,
+       SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES   = 0x10a,
+       SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b,
+       SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT        = 0x10c,
+       SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL   = 0x10d,
+       SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS      = 0x10e,
+       SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL         = 0x10f,
+       SQC_PERF_SEL_DUMMY_LAST                          = 0x110,
+       SQ_PERF_SEL_INSTS_SMEM_NORM                      = 0x111,
+       SQ_PERF_SEL_ATC_INSTS_VMEM                       = 0x112,
+       SQ_PERF_SEL_ATC_INST_LEVEL_VMEM                  = 0x113,
+       SQ_PERF_SEL_ATC_XNACK_FIRST                      = 0x114,
+       SQ_PERF_SEL_ATC_XNACK_ALL                        = 0x115,
+       SQ_PERF_SEL_ATC_XNACK_FIFO_FULL                  = 0x116,
+       SQ_PERF_SEL_ATC_INSTS_SMEM                       = 0x117,
+       SQ_PERF_SEL_ATC_INST_LEVEL_SMEM                  = 0x118,
+       SQ_PERF_SEL_IFETCH_XNACK                         = 0x119,
+       SQ_PERF_SEL_TLB_SHOOTDOWN                        = 0x11a,
+       SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES                 = 0x11b,
+       SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY                 = 0x11c,
+       SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY                 = 0x11d,
+       SQ_PERF_SEL_INSTS_VMEM_REPLAY                    = 0x11e,
+       SQ_PERF_SEL_INSTS_SMEM_REPLAY                    = 0x11f,
+       SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY               = 0x120,
+       SQ_PERF_SEL_INSTS_FLAT_REPLAY                    = 0x121,
+       SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY                = 0x122,
+       SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY                = 0x123,
+       SQ_PERF_SEL_DUMMY_LAST1                          = 0x12a,
+} SQ_PERF_SEL;
+typedef enum SQ_CAC_POWER_SEL {
+       SQ_CAC_POWER_VALU                                = 0x0,
+       SQ_CAC_POWER_VALU0                               = 0x1,
+       SQ_CAC_POWER_VALU1                               = 0x2,
+       SQ_CAC_POWER_VALU2                               = 0x3,
+       SQ_CAC_POWER_GPR_RD                              = 0x4,
+       SQ_CAC_POWER_GPR_WR                              = 0x5,
+       SQ_CAC_POWER_LDS_BUSY                            = 0x6,
+       SQ_CAC_POWER_ALU_BUSY                            = 0x7,
+       SQ_CAC_POWER_TEX_BUSY                            = 0x8,
+} SQ_CAC_POWER_SEL;
+typedef enum SQ_IND_CMD_CMD {
+       SQ_IND_CMD_CMD_NULL                              = 0x0,
+       SQ_IND_CMD_CMD_SETHALT                           = 0x1,
+       SQ_IND_CMD_CMD_SAVECTX                           = 0x2,
+       SQ_IND_CMD_CMD_KILL                              = 0x3,
+       SQ_IND_CMD_CMD_DEBUG                             = 0x4,
+       SQ_IND_CMD_CMD_TRAP                              = 0x5,
+       SQ_IND_CMD_CMD_SET_SPI_PRIO                      = 0x6,
+} SQ_IND_CMD_CMD;
+typedef enum SQ_IND_CMD_MODE {
+       SQ_IND_CMD_MODE_SINGLE                           = 0x0,
+       SQ_IND_CMD_MODE_BROADCAST                        = 0x1,
+       SQ_IND_CMD_MODE_BROADCAST_QUEUE                  = 0x2,
+       SQ_IND_CMD_MODE_BROADCAST_PIPE                   = 0x3,
+       SQ_IND_CMD_MODE_BROADCAST_ME                     = 0x4,
+} SQ_IND_CMD_MODE;
+typedef enum SQ_EDC_INFO_SOURCE {
+       SQ_EDC_INFO_SOURCE_INVALID                       = 0x0,
+       SQ_EDC_INFO_SOURCE_INST                          = 0x1,
+       SQ_EDC_INFO_SOURCE_SGPR                          = 0x2,
+       SQ_EDC_INFO_SOURCE_VGPR                          = 0x3,
+       SQ_EDC_INFO_SOURCE_LDS                           = 0x4,
+       SQ_EDC_INFO_SOURCE_GDS                           = 0x5,
+       SQ_EDC_INFO_SOURCE_TA                            = 0x6,
+} SQ_EDC_INFO_SOURCE;
+typedef enum SQ_ROUND_MODE {
+       SQ_ROUND_NEAREST_EVEN                            = 0x0,
+       SQ_ROUND_PLUS_INFINITY                           = 0x1,
+       SQ_ROUND_MINUS_INFINITY                          = 0x2,
+       SQ_ROUND_TO_ZERO                                 = 0x3,
+} SQ_ROUND_MODE;
+typedef enum SQ_INTERRUPT_WORD_ENCODING {
+       SQ_INTERRUPT_WORD_ENCODING_AUTO                  = 0x0,
+       SQ_INTERRUPT_WORD_ENCODING_INST                  = 0x1,
+       SQ_INTERRUPT_WORD_ENCODING_ERROR                 = 0x2,
+} SQ_INTERRUPT_WORD_ENCODING;
+typedef enum ENUM_SQ_EXPORT_RAT_INST {
+       SQ_EXPORT_RAT_INST_NOP                           = 0x0,
+       SQ_EXPORT_RAT_INST_STORE_TYPED                   = 0x1,
+       SQ_EXPORT_RAT_INST_STORE_RAW                     = 0x2,
+       SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM             = 0x3,
+       SQ_EXPORT_RAT_INST_CMPXCHG_INT                   = 0x4,
+       SQ_EXPORT_RAT_INST_CMPXCHG_FLT                   = 0x5,
+       SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM               = 0x6,
+       SQ_EXPORT_RAT_INST_ADD                           = 0x7,
+       SQ_EXPORT_RAT_INST_SUB                           = 0x8,
+       SQ_EXPORT_RAT_INST_RSUB                          = 0x9,
+       SQ_EXPORT_RAT_INST_MIN_INT                       = 0xa,
+       SQ_EXPORT_RAT_INST_MIN_UINT                      = 0xb,
+       SQ_EXPORT_RAT_INST_MAX_INT                       = 0xc,
+       SQ_EXPORT_RAT_INST_MAX_UINT                      = 0xd,
+       SQ_EXPORT_RAT_INST_AND                           = 0xe,
+       SQ_EXPORT_RAT_INST_OR                            = 0xf,
+       SQ_EXPORT_RAT_INST_XOR                           = 0x10,
+       SQ_EXPORT_RAT_INST_MSKOR                         = 0x11,
+       SQ_EXPORT_RAT_INST_INC_UINT                      = 0x12,
+       SQ_EXPORT_RAT_INST_DEC_UINT                      = 0x13,
+       SQ_EXPORT_RAT_INST_STORE_DWORD                   = 0x14,
+       SQ_EXPORT_RAT_INST_STORE_SHORT                   = 0x15,
+       SQ_EXPORT_RAT_INST_STORE_BYTE                    = 0x16,
+       SQ_EXPORT_RAT_INST_NOP_RTN                       = 0x20,
+       SQ_EXPORT_RAT_INST_XCHG_RTN                      = 0x22,
+       SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN              = 0x23,
+       SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN               = 0x24,
+       SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN               = 0x25,
+       SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN           = 0x26,
+       SQ_EXPORT_RAT_INST_ADD_RTN                       = 0x27,
+       SQ_EXPORT_RAT_INST_SUB_RTN                       = 0x28,
+       SQ_EXPORT_RAT_INST_RSUB_RTN                      = 0x29,
+       SQ_EXPORT_RAT_INST_MIN_INT_RTN                   = 0x2a,
+       SQ_EXPORT_RAT_INST_MIN_UINT_RTN                  = 0x2b,
+       SQ_EXPORT_RAT_INST_MAX_INT_RTN                   = 0x2c,
+       SQ_EXPORT_RAT_INST_MAX_UINT_RTN                  = 0x2d,
+       SQ_EXPORT_RAT_INST_AND_RTN                       = 0x2e,
+       SQ_EXPORT_RAT_INST_OR_RTN                        = 0x2f,
+       SQ_EXPORT_RAT_INST_XOR_RTN                       = 0x30,
+       SQ_EXPORT_RAT_INST_MSKOR_RTN                     = 0x31,
+       SQ_EXPORT_RAT_INST_INC_UINT_RTN                  = 0x32,
+       SQ_EXPORT_RAT_INST_DEC_UINT_RTN                  = 0x33,
+} ENUM_SQ_EXPORT_RAT_INST;
+typedef enum SQ_IBUF_ST {
+       SQ_IBUF_IB_IDLE                                  = 0x0,
+       SQ_IBUF_IB_INI_WAIT_GNT                          = 0x1,
+       SQ_IBUF_IB_INI_WAIT_DRET                         = 0x2,
+       SQ_IBUF_IB_LE_4DW                                = 0x3,
+       SQ_IBUF_IB_WAIT_DRET                             = 0x4,
+       SQ_IBUF_IB_EMPTY_WAIT_DRET                       = 0x5,
+       SQ_IBUF_IB_DRET                                  = 0x6,
+       SQ_IBUF_IB_EMPTY_WAIT_GNT                        = 0x7,
+} SQ_IBUF_ST;
+typedef enum SQ_INST_STR_ST {
+       SQ_INST_STR_IB_WAVE_NORML                        = 0x0,
+       SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV            = 0x1,
+       SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV             = 0x2,
+       SQ_INST_STR_IB_WAVE_INST_SKIP_AV                 = 0x3,
+       SQ_INST_STR_IB_WAVE_SETVSKIP_ST0                 = 0x4,
+       SQ_INST_STR_IB_WAVE_SETVSKIP_ST1                 = 0x5,
+       SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT               = 0x6,
+       SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT        = 0x7,
+} SQ_INST_STR_ST;
+typedef enum SQ_WAVE_IB_ECC_ST {
+       SQ_WAVE_IB_ECC_CLEAN                             = 0x0,
+       SQ_WAVE_IB_ECC_ERR_CONTINUE                      = 0x1,
+       SQ_WAVE_IB_ECC_ERR_HALT                          = 0x2,
+       SQ_WAVE_IB_ECC_WITH_ERR_MSG                      = 0x3,
+} SQ_WAVE_IB_ECC_ST;
+typedef enum SH_MEM_ADDRESS_MODE {
+       SH_MEM_ADDRESS_MODE_GPUVM64                      = 0x0,
+       SH_MEM_ADDRESS_MODE_GPUVM32                      = 0x1,
+       SH_MEM_ADDRESS_MODE_HSA64                        = 0x2,
+       SH_MEM_ADDRESS_MODE_HSA32                        = 0x3,
+} SH_MEM_ADDRESS_MODE;
+typedef enum SH_MEM_ALIGNMENT_MODE {
+       SH_MEM_ALIGNMENT_MODE_DWORD                      = 0x0,
+       SH_MEM_ALIGNMENT_MODE_DWORD_STRICT               = 0x1,
+       SH_MEM_ALIGNMENT_MODE_STRICT                     = 0x2,
+       SH_MEM_ALIGNMENT_MODE_UNALIGNED                  = 0x3,
+} SH_MEM_ALIGNMENT_MODE;
+typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
+       SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC   = 0x18,
+       SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE  = 0x19,
+} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
+#define SQ_WAVE_TYPE_PS0                          0x0
+#define SQIND_GLOBAL_REGS_OFFSET                  0x0
+#define SQIND_GLOBAL_REGS_SIZE                    0x8
+#define SQIND_LOCAL_REGS_OFFSET                   0x8
+#define SQIND_LOCAL_REGS_SIZE                     0x8
+#define SQIND_WAVE_HWREGS_OFFSET                  0x10
+#define SQIND_WAVE_HWREGS_SIZE                    0x1f0
+#define SQIND_WAVE_SGPRS_OFFSET                   0x200
+#define SQIND_WAVE_SGPRS_SIZE                     0x200
+#define SQ_GFXDEC_BEGIN                           0xa000
+#define SQ_GFXDEC_END                             0xc000
+#define SQ_GFXDEC_STATE_ID_SHIFT                  0xa
+#define SQDEC_BEGIN                               0x2300
+#define SQDEC_END                                 0x23ff
+#define SQPERFSDEC_BEGIN                          0xd9c0
+#define SQPERFSDEC_END                            0xda40
+#define SQPERFDDEC_BEGIN                          0xd1c0
+#define SQPERFDDEC_END                            0xd240
+#define SQGFXUDEC_BEGIN                           0xc330
+#define SQGFXUDEC_END                             0xc380
+#define SQPWRDEC_BEGIN                            0xf08c
+#define SQPWRDEC_END                              0xf094
+#define SQ_DISPATCHER_GFX_MIN                     0x10
+#define SQ_DISPATCHER_GFX_CNT_PER_RING            0x8
+#define SQ_MAX_PGM_SGPRS                          0x68
+#define SQ_MAX_PGM_VGPRS                          0x100
+#define SQ_THREAD_TRACE_TIME_UNIT                 0x4
+#define SQ_EX_MODE_EXCP_VALU_BASE                 0x0
+#define SQ_EX_MODE_EXCP_VALU_SIZE                 0x7
+#define SQ_EX_MODE_EXCP_INVALID                   0x0
+#define SQ_EX_MODE_EXCP_INPUT_DENORM              0x1
+#define SQ_EX_MODE_EXCP_DIV0                      0x2
+#define SQ_EX_MODE_EXCP_OVERFLOW                  0x3
+#define SQ_EX_MODE_EXCP_UNDERFLOW                 0x4
+#define SQ_EX_MODE_EXCP_INEXACT                   0x5
+#define SQ_EX_MODE_EXCP_INT_DIV0                  0x6
+#define SQ_EX_MODE_EXCP_ADDR_WATCH                0x7
+#define SQ_EX_MODE_EXCP_MEM_VIOL                  0x8
+#define INST_ID_PRIV_START                        0x80000000
+#define INST_ID_ECC_INTERRUPT_MSG                 0xfffffff0
+#define INST_ID_TTRACE_NEW_PC_MSG                 0xfffffff1
+#define INST_ID_HW_TRAP                           0xfffffff2
+#define INST_ID_KILL_SEQ                          0xfffffff3
+#define INST_ID_SPI_WREXEC                        0xfffffff4
+#define INST_ID_HOST_REG_TRAP_MSG                 0xfffffffe
+#define SQ_ENC_SOP1_BITS                          0xbe800000
+#define SQ_ENC_SOP1_MASK                          0xff800000
+#define SQ_ENC_SOP1_FIELD                         0x17d
+#define SQ_ENC_SOPC_BITS                          0xbf000000
+#define SQ_ENC_SOPC_MASK                          0xff800000
+#define SQ_ENC_SOPC_FIELD                         0x17e
+#define SQ_ENC_SOPP_BITS                          0xbf800000
+#define SQ_ENC_SOPP_MASK                          0xff800000
+#define SQ_ENC_SOPP_FIELD                         0x17f
+#define SQ_ENC_SOPK_BITS                          0xb0000000
+#define SQ_ENC_SOPK_MASK                          0xf0000000
+#define SQ_ENC_SOPK_FIELD                         0xb
+#define SQ_ENC_SOP2_BITS                          0x80000000
+#define SQ_ENC_SOP2_MASK                          0xc0000000
+#define SQ_ENC_SOP2_FIELD                         0x2
+#define SQ_ENC_SMEM_BITS                          0xc0000000
+#define SQ_ENC_SMEM_MASK                          0xfc000000
+#define SQ_ENC_SMEM_FIELD                         0x30
+#define SQ_ENC_VOP1_BITS                          0x7e000000
+#define SQ_ENC_VOP1_MASK                          0xfe000000
+#define SQ_ENC_VOP1_FIELD                         0x3f
+#define SQ_ENC_VOPC_BITS                          0x7c000000
+#define SQ_ENC_VOPC_MASK                          0xfe000000
+#define SQ_ENC_VOPC_FIELD                         0x3e
+#define SQ_ENC_VOP2_BITS                          0x0
+#define SQ_ENC_VOP2_MASK                          0x80000000
+#define SQ_ENC_VOP2_FIELD                         0x0
+#define SQ_ENC_VINTRP_BITS                        0xd4000000
+#define SQ_ENC_VINTRP_MASK                        0xfc000000
+#define SQ_ENC_VINTRP_FIELD                       0x35
+#define SQ_ENC_VOP3_BITS                          0xd0000000
+#define SQ_ENC_VOP3_MASK                          0xfc000000
+#define SQ_ENC_VOP3_FIELD                         0x34
+#define SQ_ENC_DS_BITS                            0xd8000000
+#define SQ_ENC_DS_MASK                            0xfc000000
+#define SQ_ENC_DS_FIELD                           0x36
+#define SQ_ENC_MUBUF_BITS                         0xe0000000
+#define SQ_ENC_MUBUF_MASK                         0xfc000000
+#define SQ_ENC_MUBUF_FIELD                        0x38
+#define SQ_ENC_MTBUF_BITS                         0xe8000000
+#define SQ_ENC_MTBUF_MASK                         0xfc000000
+#define SQ_ENC_MTBUF_FIELD                        0x3a
+#define SQ_ENC_MIMG_BITS                          0xf0000000
+#define SQ_ENC_MIMG_MASK                          0xfc000000
+#define SQ_ENC_MIMG_FIELD                         0x3c
+#define SQ_ENC_EXP_BITS                           0xc4000000
+#define SQ_ENC_EXP_MASK                           0xfc000000
+#define SQ_ENC_EXP_FIELD                          0x31
+#define SQ_ENC_FLAT_BITS                          0xdc000000
+#define SQ_ENC_FLAT_MASK                          0xfc000000
+#define SQ_ENC_FLAT_FIELD                         0x37
+#define SQ_V_OP3_INTRP_OFFSET                     0x274
+#define SQ_WAITCNT_VM_SHIFT                       0x0
+#define SQ_SENDMSG_STREAMID_SIZE                  0x2
+#define SQ_V_OPC_COUNT                            0x100
+#define SQ_V_OP3_INTRP_COUNT                      0xc
+#define SQ_XLATE_VOP3_TO_VOP2_OFFSET              0x100
+#define SQ_HWREG_OFFSET_SIZE                      0x5
+#define SQ_HWREG_OFFSET_SHIFT                     0x6
+#define SQ_V_OP3_3IN_OFFSET                       0x1c0
+#define SQ_NUM_ATTR                               0x21
+#define SQ_NUM_VGPR                               0x100
+#define SQ_XLATE_VOP3_TO_VINTRP_COUNT             0x4
+#define SQ_SENDMSG_MSG_SIZE                       0x4
+#define SQ_NUM_TTMP                               0xc
+#define SQ_HWREG_ID_SIZE                          0x6
+#define SQ_SENDMSG_GSOP_SIZE                      0x2
+#define SQ_NUM_SGPR                               0x66
+#define SQ_EXP_NUM_MRT                            0x8
+#define SQ_SENDMSG_SYSTEM_SIZE                    0x3
+#define SQ_WAITCNT_LGKM_SHIFT                     0x8
+#define SQ_XLATE_VOP3_TO_VOP2_COUNT               0x40
+#define SQ_V_OP3_3IN_COUNT                        0xb0
+#define SQ_V_INTRP_COUNT                          0x4
+#define SQ_WAITCNT_EXP_SIZE                       0x3
+#define SQ_SENDMSG_SYSTEM_SHIFT                   0x4
+#define SQ_EXP_NUM_GDS                            0x5
+#define SQ_HWREG_SIZE_SHIFT                       0xb
+#define SQ_XLATE_VOP3_TO_VOPC_OFFSET              0x0
+#define SQ_V_OP3_2IN_COUNT                        0x80
+#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET            0x270
+#define SQ_SENDMSG_MSG_SHIFT                      0x0
+#define SQ_WAITCNT_EXP_SHIFT                      0x4
+#define SQ_WAITCNT_VM_SIZE                        0x4
+#define SQ_XLATE_VOP3_TO_VOP1_OFFSET              0x140
+#define SQ_SENDMSG_GSOP_SHIFT                     0x4
+#define SQ_XLATE_VOP3_TO_VOP1_COUNT               0x80
+#define SQ_SRC_VGPR_BIT                           0x100
+#define SQ_V_OP2_COUNT                            0x40
+#define SQ_EXP_NUM_PARAM                          0x20
+#define SQ_V_OP1_COUNT                            0x80
+#define SQ_SENDMSG_STREAMID_SHIFT                 0x8
+#define SQ_V_OP3_2IN_OFFSET                       0x280
+#define SQ_WAITCNT_LGKM_SIZE                      0x4
+#define SQ_XLATE_VOP3_TO_VOPC_COUNT               0x100
+#define SQ_EXP_NUM_POS                            0x4
+#define SQ_HWREG_SIZE_SIZE                        0x5
+#define SQ_HWREG_ID_SHIFT                         0x0
+#define SQ_S_MOV_B32                              0x0
+#define SQ_S_MOV_B64                              0x1
+#define SQ_S_CMOV_B32                             0x2
+#define SQ_S_CMOV_B64                             0x3
+#define SQ_S_NOT_B32                              0x4
+#define SQ_S_NOT_B64                              0x5
+#define SQ_S_WQM_B32                              0x6
+#define SQ_S_WQM_B64                              0x7
+#define SQ_S_BREV_B32                             0x8
+#define SQ_S_BREV_B64                             0x9
+#define SQ_S_BCNT0_I32_B32                        0xa
+#define SQ_S_BCNT0_I32_B64                        0xb
+#define SQ_S_BCNT1_I32_B32                        0xc
+#define SQ_S_BCNT1_I32_B64                        0xd
+#define SQ_S_FF0_I32_B32                          0xe
+#define SQ_S_FF0_I32_B64                          0xf
+#define SQ_S_FF1_I32_B32                          0x10
+#define SQ_S_FF1_I32_B64                          0x11
+#define SQ_S_FLBIT_I32_B32                        0x12
+#define SQ_S_FLBIT_I32_B64                        0x13
+#define SQ_S_FLBIT_I32                            0x14
+#define SQ_S_FLBIT_I32_I64                        0x15
+#define SQ_S_SEXT_I32_I8                          0x16
+#define SQ_S_SEXT_I32_I16                         0x17
+#define SQ_S_BITSET0_B32                          0x18
+#define SQ_S_BITSET0_B64                          0x19
+#define SQ_S_BITSET1_B32                          0x1a
+#define SQ_S_BITSET1_B64                          0x1b
+#define SQ_S_GETPC_B64                            0x1c
+#define SQ_S_SETPC_B64                            0x1d
+#define SQ_S_SWAPPC_B64                           0x1e
+#define SQ_S_RFE_B64                              0x1f
+#define SQ_S_AND_SAVEEXEC_B64                     0x20
+#define SQ_S_OR_SAVEEXEC_B64                      0x21
+#define SQ_S_XOR_SAVEEXEC_B64                     0x22
+#define SQ_S_ANDN2_SAVEEXEC_B64                   0x23
+#define SQ_S_ORN2_SAVEEXEC_B64                    0x24
+#define SQ_S_NAND_SAVEEXEC_B64                    0x25
+#define SQ_S_NOR_SAVEEXEC_B64                     0x26
+#define SQ_S_XNOR_SAVEEXEC_B64                    0x27
+#define SQ_S_QUADMASK_B32                         0x28
+#define SQ_S_QUADMASK_B64                         0x29
+#define SQ_S_MOVRELS_B32                          0x2a
+#define SQ_S_MOVRELS_B64                          0x2b
+#define SQ_S_MOVRELD_B32                          0x2c
+#define SQ_S_MOVRELD_B64                          0x2d
+#define SQ_S_CBRANCH_JOIN                         0x2e
+#define SQ_S_MOV_REGRD_B32                        0x2f
+#define SQ_S_ABS_I32                              0x30
+#define SQ_S_MOV_FED_B32                          0x31
+#define SQ_S_SET_GPR_IDX_IDX                      0x32
+#define SQ_ATTR0                                  0x0
+#define SQ_S_MOVK_I32                             0x0
+#define SQ_S_CMOVK_I32                            0x1
+#define SQ_S_CMPK_EQ_I32                          0x2
+#define SQ_S_CMPK_LG_I32                          0x3
+#define SQ_S_CMPK_GT_I32                          0x4
+#define SQ_S_CMPK_GE_I32                          0x5
+#define SQ_S_CMPK_LT_I32                          0x6
+#define SQ_S_CMPK_LE_I32                          0x7
+#define SQ_S_CMPK_EQ_U32                          0x8
+#define SQ_S_CMPK_LG_U32                          0x9
+#define SQ_S_CMPK_GT_U32                          0xa
+#define SQ_S_CMPK_GE_U32                          0xb
+#define SQ_S_CMPK_LT_U32                          0xc
+#define SQ_S_CMPK_LE_U32                          0xd
+#define SQ_S_ADDK_I32                             0xe
+#define SQ_S_MULK_I32                             0xf
+#define SQ_S_CBRANCH_I_FORK                       0x10
+#define SQ_S_GETREG_B32                           0x11
+#define SQ_S_SETREG_B32                           0x12
+#define SQ_S_GETREG_REGRD_B32                     0x13
+#define SQ_S_SETREG_IMM32_B32                     0x14
+#define SQ_TBA_LO                                 0x6c
+#define SQ_TBA_HI                                 0x6d
+#define SQ_TMA_LO                                 0x6e
+#define SQ_TMA_HI                                 0x6f
+#define SQ_TTMP0                                  0x70
+#define SQ_TTMP1                                  0x71
+#define SQ_TTMP2                                  0x72
+#define SQ_TTMP3                                  0x73
+#define SQ_TTMP4                                  0x74
+#define SQ_TTMP5                                  0x75
+#define SQ_TTMP6                                  0x76
+#define SQ_TTMP7                                  0x77
+#define SQ_TTMP8                                  0x78
+#define SQ_TTMP9                                  0x79
+#define SQ_TTMP10                                 0x7a
+#define SQ_TTMP11                                 0x7b
+#define SQ_VGPR0                                  0x0
+#define SQ_EXP                                    0x0
+#define SQ_EXP_MRT0                               0x0
+#define SQ_EXP_MRTZ                               0x8
+#define SQ_EXP_NULL                               0x9
+#define SQ_EXP_POS0                               0xc
+#define SQ_EXP_PARAM0                             0x20
+#define SQ_CNT1                                   0x0
+#define SQ_CNT2                                   0x1
+#define SQ_CNT3                                   0x2
+#define SQ_CNT4                                   0x3
+#define SQ_S_LOAD_DWORD                           0x0
+#define SQ_S_LOAD_DWORDX2                         0x1
+#define SQ_S_LOAD_DWORDX4                         0x2
+#define SQ_S_LOAD_DWORDX8                         0x3
+#define SQ_S_LOAD_DWORDX16                        0x4
+#define SQ_S_BUFFER_LOAD_DWORD                    0x8
+#define SQ_S_BUFFER_LOAD_DWORDX2                  0x9
+#define SQ_S_BUFFER_LOAD_DWORDX4                  0xa
+#define SQ_S_BUFFER_LOAD_DWORDX8                  0xb
+#define SQ_S_BUFFER_LOAD_DWORDX16                 0xc
+#define SQ_S_STORE_DWORD                          0x10
+#define SQ_S_STORE_DWORDX2                        0x11
+#define SQ_S_STORE_DWORDX4                        0x12
+#define SQ_S_BUFFER_STORE_DWORD                   0x18
+#define SQ_S_BUFFER_STORE_DWORDX2                 0x19
+#define SQ_S_BUFFER_STORE_DWORDX4                 0x1a
+#define SQ_S_DCACHE_INV                           0x20
+#define SQ_S_DCACHE_WB                            0x21
+#define SQ_S_DCACHE_INV_VOL                       0x22
+#define SQ_S_DCACHE_WB_VOL                        0x23
+#define SQ_S_MEMTIME                              0x24
+#define SQ_S_MEMREALTIME                          0x25
+#define SQ_S_ATC_PROBE                            0x26
+#define SQ_S_ATC_PROBE_BUFFER                     0x27
+#define SQ_S_BUFFER_ATOMIC_SWAP                   0x40
+#define SQ_S_BUFFER_ATOMIC_CMPSWAP                0x41
+#define SQ_S_BUFFER_ATOMIC_ADD                    0x42
+#define SQ_S_BUFFER_ATOMIC_SUB                    0x43
+#define SQ_S_BUFFER_ATOMIC_SMIN                   0x44
+#define SQ_S_BUFFER_ATOMIC_UMIN                   0x45
+#define SQ_S_BUFFER_ATOMIC_SMAX                   0x46
+#define SQ_S_BUFFER_ATOMIC_UMAX                   0x47
+#define SQ_S_BUFFER_ATOMIC_AND                    0x48
+#define SQ_S_BUFFER_ATOMIC_OR                     0x49
+#define SQ_S_BUFFER_ATOMIC_XOR                    0x4a
+#define SQ_S_BUFFER_ATOMIC_INC                    0x4b
+#define SQ_S_BUFFER_ATOMIC_DEC                    0x4c
+#define SQ_S_BUFFER_ATOMIC_SWAP_X2                0x60
+#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2             0x61
+#define SQ_S_BUFFER_ATOMIC_ADD_X2                 0x62
+#define SQ_S_BUFFER_ATOMIC_SUB_X2                 0x63
+#define SQ_S_BUFFER_ATOMIC_SMIN_X2                0x64
+#define SQ_S_BUFFER_ATOMIC_UMIN_X2                0x65
+#define SQ_S_BUFFER_ATOMIC_SMAX_X2                0x66
+#define SQ_S_BUFFER_ATOMIC_UMAX_X2                0x67
+#define SQ_S_BUFFER_ATOMIC_AND_X2                 0x68
+#define SQ_S_BUFFER_ATOMIC_OR_X2                  0x69
+#define SQ_S_BUFFER_ATOMIC_XOR_X2                 0x6a
+#define SQ_S_BUFFER_ATOMIC_INC_X2                 0x6b
+#define SQ_S_BUFFER_ATOMIC_DEC_X2                 0x6c
+#define SQ_F                                      0x0
+#define SQ_LT                                     0x1
+#define SQ_EQ                                     0x2
+#define SQ_LE                                     0x3
+#define SQ_GT                                     0x4
+#define SQ_LG                                     0x5
+#define SQ_GE                                     0x6
+#define SQ_O                                      0x7
+#define SQ_U                                      0x8
+#define SQ_NGE                                    0x9
+#define SQ_NLG                                    0xa
+#define SQ_NGT                                    0xb
+#define SQ_NLE                                    0xc
+#define SQ_NEQ                                    0xd
+#define SQ_NLT                                    0xe
+#define SQ_TRU                                    0xf
+#define SQ_V_CMP_CLASS_F32                        0x10
+#define SQ_V_CMPX_CLASS_F32                       0x11
+#define SQ_V_CMP_CLASS_F64                        0x12
+#define SQ_V_CMPX_CLASS_F64                       0x13
+#define SQ_V_CMP_CLASS_F16                        0x14
+#define SQ_V_CMPX_CLASS_F16                       0x15
+#define SQ_V_CMP_F_F16                            0x20
+#define SQ_V_CMP_LT_F16                           0x21
+#define SQ_V_CMP_EQ_F16                           0x22
+#define SQ_V_CMP_LE_F16                           0x23
+#define SQ_V_CMP_GT_F16                           0x24
+#define SQ_V_CMP_LG_F16                           0x25
+#define SQ_V_CMP_GE_F16                           0x26
+#define SQ_V_CMP_O_F16                            0x27
+#define SQ_V_CMP_U_F16                            0x28
+#define SQ_V_CMP_NGE_F16                          0x29
+#define SQ_V_CMP_NLG_F16                          0x2a
+#define SQ_V_CMP_NGT_F16                          0x2b
+#define SQ_V_CMP_NLE_F16                          0x2c
+#define SQ_V_CMP_NEQ_F16                          0x2d
+#define SQ_V_CMP_NLT_F16                          0x2e
+#define SQ_V_CMP_TRU_F16                          0x2f
+#define SQ_V_CMPX_F_F16                           0x30
+#define SQ_V_CMPX_LT_F16                          0x31
+#define SQ_V_CMPX_EQ_F16                          0x32
+#define SQ_V_CMPX_LE_F16                          0x33
+#define SQ_V_CMPX_GT_F16                          0x34
+#define SQ_V_CMPX_LG_F16                          0x35
+#define SQ_V_CMPX_GE_F16                          0x36
+#define SQ_V_CMPX_O_F16                           0x37
+#define SQ_V_CMPX_U_F16                           0x38
+#define SQ_V_CMPX_NGE_F16                         0x39
+#define SQ_V_CMPX_NLG_F16                         0x3a
+#define SQ_V_CMPX_NGT_F16                         0x3b
+#define SQ_V_CMPX_NLE_F16                         0x3c
+#define SQ_V_CMPX_NEQ_F16                         0x3d
+#define SQ_V_CMPX_NLT_F16                         0x3e
+#define SQ_V_CMPX_TRU_F16                         0x3f
+#define SQ_V_CMP_F_F32                            0x40
+#define SQ_V_CMP_LT_F32                           0x41
+#define SQ_V_CMP_EQ_F32                           0x42
+#define SQ_V_CMP_LE_F32                           0x43
+#define SQ_V_CMP_GT_F32                           0x44
+#define SQ_V_CMP_LG_F32                           0x45
+#define SQ_V_CMP_GE_F32                           0x46
+#define SQ_V_CMP_O_F32                            0x47
+#define SQ_V_CMP_U_F32                            0x48
+#define SQ_V_CMP_NGE_F32                          0x49
+#define SQ_V_CMP_NLG_F32                          0x4a
+#define SQ_V_CMP_NGT_F32                          0x4b
+#define SQ_V_CMP_NLE_F32                          0x4c
+#define SQ_V_CMP_NEQ_F32                          0x4d
+#define SQ_V_CMP_NLT_F32                          0x4e
+#define SQ_V_CMP_TRU_F32                          0x4f
+#define SQ_V_CMPX_F_F32                           0x50
+#define SQ_V_CMPX_LT_F32                          0x51
+#define SQ_V_CMPX_EQ_F32                          0x52
+#define SQ_V_CMPX_LE_F32                          0x53
+#define SQ_V_CMPX_GT_F32                          0x54
+#define SQ_V_CMPX_LG_F32                          0x55
+#define SQ_V_CMPX_GE_F32                          0x56
+#define SQ_V_CMPX_O_F32                           0x57
+#define SQ_V_CMPX_U_F32                           0x58
+#define SQ_V_CMPX_NGE_F32                         0x59
+#define SQ_V_CMPX_NLG_F32                         0x5a
+#define SQ_V_CMPX_NGT_F32                         0x5b
+#define SQ_V_CMPX_NLE_F32                         0x5c
+#define SQ_V_CMPX_NEQ_F32                         0x5d
+#define SQ_V_CMPX_NLT_F32                         0x5e
+#define SQ_V_CMPX_TRU_F32                         0x5f
+#define SQ_V_CMP_F_F64                            0x60
+#define SQ_V_CMP_LT_F64                           0x61
+#define SQ_V_CMP_EQ_F64                           0x62
+#define SQ_V_CMP_LE_F64                           0x63
+#define SQ_V_CMP_GT_F64                           0x64
+#define SQ_V_CMP_LG_F64                           0x65
+#define SQ_V_CMP_GE_F64                           0x66
+#define SQ_V_CMP_O_F64                            0x67
+#define SQ_V_CMP_U_F64                            0x68
+#define SQ_V_CMP_NGE_F64                          0x69
+#define SQ_V_CMP_NLG_F64                          0x6a
+#define SQ_V_CMP_NGT_F64                          0x6b
+#define SQ_V_CMP_NLE_F64                          0x6c
+#define SQ_V_CMP_NEQ_F64                          0x6d
+#define SQ_V_CMP_NLT_F64                          0x6e
+#define SQ_V_CMP_TRU_F64                          0x6f
+#define SQ_V_CMPX_F_F64                           0x70
+#define SQ_V_CMPX_LT_F64                          0x71
+#define SQ_V_CMPX_EQ_F64                          0x72
+#define SQ_V_CMPX_LE_F64                          0x73
+#define SQ_V_CMPX_GT_F64                          0x74
+#define SQ_V_CMPX_LG_F64                          0x75
+#define SQ_V_CMPX_GE_F64                          0x76
+#define SQ_V_CMPX_O_F64                           0x77
+#define SQ_V_CMPX_U_F64                           0x78
+#define SQ_V_CMPX_NGE_F64                         0x79
+#define SQ_V_CMPX_NLG_F64                         0x7a
+#define SQ_V_CMPX_NGT_F64                         0x7b
+#define SQ_V_CMPX_NLE_F64                         0x7c
+#define SQ_V_CMPX_NEQ_F64                         0x7d
+#define SQ_V_CMPX_NLT_F64                         0x7e
+#define SQ_V_CMPX_TRU_F64                         0x7f
+#define SQ_V_CMP_F_I16                            0xa0
+#define SQ_V_CMP_LT_I16                           0xa1
+#define SQ_V_CMP_EQ_I16                           0xa2
+#define SQ_V_CMP_LE_I16                           0xa3
+#define SQ_V_CMP_GT_I16                           0xa4
+#define SQ_V_CMP_NE_I16                           0xa5
+#define SQ_V_CMP_GE_I16                           0xa6
+#define SQ_V_CMP_T_I16                            0xa7
+#define SQ_V_CMP_F_U16                            0xa8
+#define SQ_V_CMP_LT_U16                           0xa9
+#define SQ_V_CMP_EQ_U16                           0xaa
+#define SQ_V_CMP_LE_U16                           0xab
+#define SQ_V_CMP_GT_U16                           0xac
+#define SQ_V_CMP_NE_U16                           0xad
+#define SQ_V_CMP_GE_U16                           0xae
+#define SQ_V_CMP_T_U16                            0xaf
+#define SQ_V_CMPX_F_I16                           0xb0
+#define SQ_V_CMPX_LT_I16                          0xb1
+#define SQ_V_CMPX_EQ_I16                          0xb2
+#define SQ_V_CMPX_LE_I16                          0xb3
+#define SQ_V_CMPX_GT_I16                          0xb4
+#define SQ_V_CMPX_NE_I16                          0xb5
+#define SQ_V_CMPX_GE_I16                          0xb6
+#define SQ_V_CMPX_T_I16                           0xb7
+#define SQ_V_CMPX_F_U16                           0xb8
+#define SQ_V_CMPX_LT_U16                          0xb9
+#define SQ_V_CMPX_EQ_U16                          0xba
+#define SQ_V_CMPX_LE_U16                          0xbb
+#define SQ_V_CMPX_GT_U16                          0xbc
+#define SQ_V_CMPX_NE_U16                          0xbd
+#define SQ_V_CMPX_GE_U16                          0xbe
+#define SQ_V_CMPX_T_U16                           0xbf
+#define SQ_V_CMP_F_I32                            0xc0
+#define SQ_V_CMP_LT_I32                           0xc1
+#define SQ_V_CMP_EQ_I32                           0xc2
+#define SQ_V_CMP_LE_I32                           0xc3
+#define SQ_V_CMP_GT_I32                           0xc4
+#define SQ_V_CMP_NE_I32                           0xc5
+#define SQ_V_CMP_GE_I32                           0xc6
+#define SQ_V_CMP_T_I32                            0xc7
+#define SQ_V_CMP_F_U32                            0xc8
+#define SQ_V_CMP_LT_U32                           0xc9
+#define SQ_V_CMP_EQ_U32                           0xca
+#define SQ_V_CMP_LE_U32                           0xcb
+#define SQ_V_CMP_GT_U32                           0xcc
+#define SQ_V_CMP_NE_U32                           0xcd
+#define SQ_V_CMP_GE_U32                           0xce
+#define SQ_V_CMP_T_U32                            0xcf
+#define SQ_V_CMPX_F_I32                           0xd0
+#define SQ_V_CMPX_LT_I32                          0xd1
+#define SQ_V_CMPX_EQ_I32                          0xd2
+#define SQ_V_CMPX_LE_I32                          0xd3
+#define SQ_V_CMPX_GT_I32                          0xd4
+#define SQ_V_CMPX_NE_I32                          0xd5
+#define SQ_V_CMPX_GE_I32                          0xd6
+#define SQ_V_CMPX_T_I32                           0xd7
+#define SQ_V_CMPX_F_U32                           0xd8
+#define SQ_V_CMPX_LT_U32                          0xd9
+#define SQ_V_CMPX_EQ_U32                          0xda
+#define SQ_V_CMPX_LE_U32                          0xdb
+#define SQ_V_CMPX_GT_U32                          0xdc
+#define SQ_V_CMPX_NE_U32                          0xdd
+#define SQ_V_CMPX_GE_U32                          0xde
+#define SQ_V_CMPX_T_U32                           0xdf
+#define SQ_V_CMP_F_I64                            0xe0
+#define SQ_V_CMP_LT_I64                           0xe1
+#define SQ_V_CMP_EQ_I64                           0xe2
+#define SQ_V_CMP_LE_I64                           0xe3
+#define SQ_V_CMP_GT_I64                           0xe4
+#define SQ_V_CMP_NE_I64                           0xe5
+#define SQ_V_CMP_GE_I64                           0xe6
+#define SQ_V_CMP_T_I64                            0xe7
+#define SQ_V_CMP_F_U64                            0xe8
+#define SQ_V_CMP_LT_U64                           0xe9
+#define SQ_V_CMP_EQ_U64                           0xea
+#define SQ_V_CMP_LE_U64                           0xeb
+#define SQ_V_CMP_GT_U64                           0xec
+#define SQ_V_CMP_NE_U64                           0xed
+#define SQ_V_CMP_GE_U64                           0xee
+#define SQ_V_CMP_T_U64                            0xef
+#define SQ_V_CMPX_F_I64                           0xf0
+#define SQ_V_CMPX_LT_I64                          0xf1
+#define SQ_V_CMPX_EQ_I64                          0xf2
+#define SQ_V_CMPX_LE_I64                          0xf3
+#define SQ_V_CMPX_GT_I64                          0xf4
+#define SQ_V_CMPX_NE_I64                          0xf5
+#define SQ_V_CMPX_GE_I64                          0xf6
+#define SQ_V_CMPX_T_I64                           0xf7
+#define SQ_V_CMPX_F_U64                           0xf8
+#define SQ_V_CMPX_LT_U64                          0xf9
+#define SQ_V_CMPX_EQ_U64                          0xfa
+#define SQ_V_CMPX_LE_U64                          0xfb
+#define SQ_V_CMPX_GT_U64                          0xfc
+#define SQ_V_CMPX_NE_U64                          0xfd
+#define SQ_V_CMPX_GE_U64                          0xfe
+#define SQ_V_CMPX_T_U64                           0xff
+#define SQ_L1                                     0x1
+#define SQ_L2                                     0x2
+#define SQ_L3                                     0x3
+#define SQ_L4                                     0x4
+#define SQ_L5                                     0x5
+#define SQ_L6                                     0x6
+#define SQ_L7                                     0x7
+#define SQ_L8                                     0x8
+#define SQ_L9                                     0x9
+#define SQ_L10                                    0xa
+#define SQ_L11                                    0xb
+#define SQ_L12                                    0xc
+#define SQ_L13                                    0xd
+#define SQ_L14                                    0xe
+#define SQ_L15                                    0xf
+#define SQ_SGPR0                                  0x0
+#define SQ_SDWA_UNUSED_PAD                        0x0
+#define SQ_SDWA_UNUSED_SEXT                       0x1
+#define SQ_SDWA_UNUSED_PRESERVE                   0x2
+#define SQ_F                                      0x0
+#define SQ_LT                                     0x1
+#define SQ_EQ                                     0x2
+#define SQ_LE                                     0x3
+#define SQ_GT                                     0x4
+#define SQ_NE                                     0x5
+#define SQ_GE                                     0x6
+#define SQ_T                                      0x7
+#define SQ_SRC_64_INT                             0xc0
+#define SQ_SRC_M_1_INT                            0xc1
+#define SQ_SRC_M_2_INT                            0xc2
+#define SQ_SRC_M_3_INT                            0xc3
+#define SQ_SRC_M_4_INT                            0xc4
+#define SQ_SRC_M_5_INT                            0xc5
+#define SQ_SRC_M_6_INT                            0xc6
+#define SQ_SRC_M_7_INT                            0xc7
+#define SQ_SRC_M_8_INT                            0xc8
+#define SQ_SRC_M_9_INT                            0xc9
+#define SQ_SRC_M_10_INT                           0xca
+#define SQ_SRC_M_11_INT                           0xcb
+#define SQ_SRC_M_12_INT                           0xcc
+#define SQ_SRC_M_13_INT                           0xcd
+#define SQ_SRC_M_14_INT                           0xce
+#define SQ_SRC_M_15_INT                           0xcf
+#define SQ_SRC_M_16_INT                           0xd0
+#define SQ_SRC_0_5                                0xf0
+#define SQ_SRC_M_0_5                              0xf1
+#define SQ_SRC_1                                  0xf2
+#define SQ_SRC_M_1                                0xf3
+#define SQ_SRC_2                                  0xf4
+#define SQ_SRC_M_2                                0xf5
+#define SQ_SRC_4                                  0xf6
+#define SQ_SRC_M_4                                0xf7
+#define SQ_SRC_INV_2PI                            0xf8
+#define SQ_SRC_0                                  0x80
+#define SQ_SRC_1_INT                              0x81
+#define SQ_SRC_2_INT                              0x82
+#define SQ_SRC_3_INT                              0x83
+#define SQ_SRC_4_INT                              0x84
+#define SQ_SRC_5_INT                              0x85
+#define SQ_SRC_6_INT                              0x86
+#define SQ_SRC_7_INT                              0x87
+#define SQ_SRC_8_INT                              0x88
+#define SQ_SRC_9_INT                              0x89
+#define SQ_SRC_10_INT                             0x8a
+#define SQ_SRC_11_INT                             0x8b
+#define SQ_SRC_12_INT                             0x8c
+#define SQ_SRC_13_INT                             0x8d
+#define SQ_SRC_14_INT                             0x8e
+#define SQ_SRC_15_INT                             0x8f
+#define SQ_SRC_16_INT                             0x90
+#define SQ_SRC_17_INT                             0x91
+#define SQ_SRC_18_INT                             0x92
+#define SQ_SRC_19_INT                             0x93
+#define SQ_SRC_20_INT                             0x94
+#define SQ_SRC_21_INT                             0x95
+#define SQ_SRC_22_INT                             0x96
+#define SQ_SRC_23_INT                             0x97
+#define SQ_SRC_24_INT                             0x98
+#define SQ_SRC_25_INT                             0x99
+#define SQ_SRC_26_INT                             0x9a
+#define SQ_SRC_27_INT                             0x9b
+#define SQ_SRC_28_INT                             0x9c
+#define SQ_SRC_29_INT                             0x9d
+#define SQ_SRC_30_INT                             0x9e
+#define SQ_SRC_31_INT                             0x9f
+#define SQ_SRC_32_INT                             0xa0
+#define SQ_SRC_33_INT                             0xa1
+#define SQ_SRC_34_INT                             0xa2
+#define SQ_SRC_35_INT                             0xa3
+#define SQ_SRC_36_INT                             0xa4
+#define SQ_SRC_37_INT                             0xa5
+#define SQ_SRC_38_INT                             0xa6
+#define SQ_SRC_39_INT                             0xa7
+#define SQ_SRC_40_INT                             0xa8
+#define SQ_SRC_41_INT                             0xa9
+#define SQ_SRC_42_INT                             0xaa
+#define SQ_SRC_43_INT                             0xab
+#define SQ_SRC_44_INT                             0xac
+#define SQ_SRC_45_INT                             0xad
+#define SQ_SRC_46_INT                             0xae
+#define SQ_SRC_47_INT                             0xaf
+#define SQ_SRC_48_INT                             0xb0
+#define SQ_SRC_49_INT                             0xb1
+#define SQ_SRC_50_INT                             0xb2
+#define SQ_SRC_51_INT                             0xb3
+#define SQ_SRC_52_INT                             0xb4
+#define SQ_SRC_53_INT                             0xb5
+#define SQ_SRC_54_INT                             0xb6
+#define SQ_SRC_55_INT                             0xb7
+#define SQ_SRC_56_INT                             0xb8
+#define SQ_SRC_57_INT                             0xb9
+#define SQ_SRC_58_INT                             0xba
+#define SQ_SRC_59_INT                             0xbb
+#define SQ_SRC_60_INT                             0xbc
+#define SQ_SRC_61_INT                             0xbd
+#define SQ_SRC_62_INT                             0xbe
+#define SQ_SRC_63_INT                             0xbf
+#define SQ_DS_ADD_U32                             0x0
+#define SQ_DS_SUB_U32                             0x1
+#define SQ_DS_RSUB_U32                            0x2
+#define SQ_DS_INC_U32                             0x3
+#define SQ_DS_DEC_U32                             0x4
+#define SQ_DS_MIN_I32                             0x5
+#define SQ_DS_MAX_I32                             0x6
+#define SQ_DS_MIN_U32                             0x7
+#define SQ_DS_MAX_U32                             0x8
+#define SQ_DS_AND_B32                             0x9
+#define SQ_DS_OR_B32                              0xa
+#define SQ_DS_XOR_B32                             0xb
+#define SQ_DS_MSKOR_B32                           0xc
+#define SQ_DS_WRITE_B32                           0xd
+#define SQ_DS_WRITE2_B32                          0xe
+#define SQ_DS_WRITE2ST64_B32                      0xf
+#define SQ_DS_CMPST_B32                           0x10
+#define SQ_DS_CMPST_F32                           0x11
+#define SQ_DS_MIN_F32                             0x12
+#define SQ_DS_MAX_F32                             0x13
+#define SQ_DS_NOP                                 0x14
+#define SQ_DS_ADD_F32                             0x15
+#define SQ_DS_WRITE_B8                            0x1e
+#define SQ_DS_WRITE_B16                           0x1f
+#define SQ_DS_ADD_RTN_U32                         0x20
+#define SQ_DS_SUB_RTN_U32                         0x21
+#define SQ_DS_RSUB_RTN_U32                        0x22
+#define SQ_DS_INC_RTN_U32                         0x23
+#define SQ_DS_DEC_RTN_U32                         0x24
+#define SQ_DS_MIN_RTN_I32                         0x25
+#define SQ_DS_MAX_RTN_I32                         0x26
+#define SQ_DS_MIN_RTN_U32                         0x27
+#define SQ_DS_MAX_RTN_U32                         0x28
+#define SQ_DS_AND_RTN_B32                         0x29
+#define SQ_DS_OR_RTN_B32                          0x2a
+#define SQ_DS_XOR_RTN_B32                         0x2b
+#define SQ_DS_MSKOR_RTN_B32                       0x2c
+#define SQ_DS_WRXCHG_RTN_B32                      0x2d
+#define SQ_DS_WRXCHG2_RTN_B32                     0x2e
+#define SQ_DS_WRXCHG2ST64_RTN_B32                 0x2f
+#define SQ_DS_CMPST_RTN_B32                       0x30
+#define SQ_DS_CMPST_RTN_F32                       0x31
+#define SQ_DS_MIN_RTN_F32                         0x32
+#define SQ_DS_MAX_RTN_F32                         0x33
+#define SQ_DS_WRAP_RTN_B32                        0x34
+#define SQ_DS_ADD_RTN_F32                         0x35
+#define SQ_DS_READ_B32                            0x36
+#define SQ_DS_READ2_B32                           0x37
+#define SQ_DS_READ2ST64_B32                       0x38
+#define SQ_DS_READ_I8                             0x39
+#define SQ_DS_READ_U8                             0x3a
+#define SQ_DS_READ_I16                            0x3b
+#define SQ_DS_READ_U16                            0x3c
+#define SQ_DS_SWIZZLE_B32                         0x3d
+#define SQ_DS_PERMUTE_B32                         0x3e
+#define SQ_DS_BPERMUTE_B32                        0x3f
+#define SQ_DS_ADD_U64                             0x40
+#define SQ_DS_SUB_U64                             0x41
+#define SQ_DS_RSUB_U64                            0x42
+#define SQ_DS_INC_U64                             0x43
+#define SQ_DS_DEC_U64                             0x44
+#define SQ_DS_MIN_I64                             0x45
+#define SQ_DS_MAX_I64                             0x46
+#define SQ_DS_MIN_U64                             0x47
+#define SQ_DS_MAX_U64                             0x48
+#define SQ_DS_AND_B64                             0x49
+#define SQ_DS_OR_B64                              0x4a
+#define SQ_DS_XOR_B64                             0x4b
+#define SQ_DS_MSKOR_B64                           0x4c
+#define SQ_DS_WRITE_B64                           0x4d
+#define SQ_DS_WRITE2_B64                          0x4e
+#define SQ_DS_WRITE2ST64_B64                      0x4f
+#define SQ_DS_CMPST_B64                           0x50
+#define SQ_DS_CMPST_F64                           0x51
+#define SQ_DS_MIN_F64                             0x52
+#define SQ_DS_MAX_F64                             0x53
+#define SQ_DS_ADD_RTN_U64                         0x60
+#define SQ_DS_SUB_RTN_U64                         0x61
+#define SQ_DS_RSUB_RTN_U64                        0x62
+#define SQ_DS_INC_RTN_U64                         0x63
+#define SQ_DS_DEC_RTN_U64                         0x64
+#define SQ_DS_MIN_RTN_I64                         0x65
+#define SQ_DS_MAX_RTN_I64                         0x66
+#define SQ_DS_MIN_RTN_U64                         0x67
+#define SQ_DS_MAX_RTN_U64                         0x68
+#define SQ_DS_AND_RTN_B64                         0x69
+#define SQ_DS_OR_RTN_B64                          0x6a
+#define SQ_DS_XOR_RTN_B64                         0x6b
+#define SQ_DS_MSKOR_RTN_B64                       0x6c
+#define SQ_DS_WRXCHG_RTN_B64                      0x6d
+#define SQ_DS_WRXCHG2_RTN_B64                     0x6e
+#define SQ_DS_WRXCHG2ST64_RTN_B64                 0x6f
+#define SQ_DS_CMPST_RTN_B64                       0x70
+#define SQ_DS_CMPST_RTN_F64                       0x71
+#define SQ_DS_MIN_RTN_F64                         0x72
+#define SQ_DS_MAX_RTN_F64                         0x73
+#define SQ_DS_READ_B64                            0x76
+#define SQ_DS_READ2_B64                           0x77
+#define SQ_DS_READ2ST64_B64                       0x78
+#define SQ_DS_CONDXCHG32_RTN_B64                  0x7e
+#define SQ_DS_ADD_SRC2_U32                        0x80
+#define SQ_DS_SUB_SRC2_U32                        0x81
+#define SQ_DS_RSUB_SRC2_U32                       0x82
+#define SQ_DS_INC_SRC2_U32                        0x83
+#define SQ_DS_DEC_SRC2_U32                        0x84
+#define SQ_DS_MIN_SRC2_I32                        0x85
+#define SQ_DS_MAX_SRC2_I32                        0x86
+#define SQ_DS_MIN_SRC2_U32                        0x87
+#define SQ_DS_MAX_SRC2_U32                        0x88
+#define SQ_DS_AND_SRC2_B32                        0x89
+#define SQ_DS_OR_SRC2_B32                         0x8a
+#define SQ_DS_XOR_SRC2_B32                        0x8b
+#define SQ_DS_WRITE_SRC2_B32                      0x8d
+#define SQ_DS_MIN_SRC2_F32                        0x92
+#define SQ_DS_MAX_SRC2_F32                        0x93
+#define SQ_DS_ADD_SRC2_F32                        0x95
+#define SQ_DS_GWS_SEMA_RELEASE_ALL                0x98
+#define SQ_DS_GWS_INIT                            0x99
+#define SQ_DS_GWS_SEMA_V                          0x9a
+#define SQ_DS_GWS_SEMA_BR                         0x9b
+#define SQ_DS_GWS_SEMA_P                          0x9c
+#define SQ_DS_GWS_BARRIER                         0x9d
+#define SQ_DS_CONSUME                             0xbd
+#define SQ_DS_APPEND                              0xbe
+#define SQ_DS_ORDERED_COUNT                       0xbf
+#define SQ_DS_ADD_SRC2_U64                        0xc0
+#define SQ_DS_SUB_SRC2_U64                        0xc1
+#define SQ_DS_RSUB_SRC2_U64                       0xc2
+#define SQ_DS_INC_SRC2_U64                        0xc3
+#define SQ_DS_DEC_SRC2_U64                        0xc4
+#define SQ_DS_MIN_SRC2_I64                        0xc5
+#define SQ_DS_MAX_SRC2_I64                        0xc6
+#define SQ_DS_MIN_SRC2_U64                        0xc7
+#define SQ_DS_MAX_SRC2_U64                        0xc8
+#define SQ_DS_AND_SRC2_B64                        0xc9
+#define SQ_DS_OR_SRC2_B64                         0xca
+#define SQ_DS_XOR_SRC2_B64                        0xcb
+#define SQ_DS_WRITE_SRC2_B64                      0xcd
+#define SQ_DS_MIN_SRC2_F64                        0xd2
+#define SQ_DS_MAX_SRC2_F64                        0xd3
+#define SQ_DS_WRITE_B96                           0xde
+#define SQ_DS_WRITE_B128                          0xdf
+#define SQ_DS_CONDXCHG32_RTN_B128                 0xfd
+#define SQ_DS_READ_B96                            0xfe
+#define SQ_DS_READ_B128                           0xff
+#define SQ_BUFFER_LOAD_FORMAT_X                   0x0
+#define SQ_BUFFER_LOAD_FORMAT_XY                  0x1
+#define SQ_BUFFER_LOAD_FORMAT_XYZ                 0x2
+#define SQ_BUFFER_LOAD_FORMAT_XYZW                0x3
+#define SQ_BUFFER_STORE_FORMAT_X                  0x4
+#define SQ_BUFFER_STORE_FORMAT_XY                 0x5
+#define SQ_BUFFER_STORE_FORMAT_XYZ                0x6
+#define SQ_BUFFER_STORE_FORMAT_XYZW               0x7
+#define SQ_BUFFER_LOAD_FORMAT_D16_X               0x8
+#define SQ_BUFFER_LOAD_FORMAT_D16_XY              0x9
+#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ             0xa
+#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW            0xb
+#define SQ_BUFFER_STORE_FORMAT_D16_X              0xc
+#define SQ_BUFFER_STORE_FORMAT_D16_XY             0xd
+#define SQ_BUFFER_STORE_FORMAT_D16_XYZ            0xe
+#define SQ_BUFFER_STORE_FORMAT_D16_XYZW           0xf
+#define SQ_BUFFER_LOAD_UBYTE                      0x10
+#define SQ_BUFFER_LOAD_SBYTE                      0x11
+#define SQ_BUFFER_LOAD_USHORT                     0x12
+#define SQ_BUFFER_LOAD_SSHORT                     0x13
+#define SQ_BUFFER_LOAD_DWORD                      0x14
+#define SQ_BUFFER_LOAD_DWORDX2                    0x15
+#define SQ_BUFFER_LOAD_DWORDX3                    0x16
+#define SQ_BUFFER_LOAD_DWORDX4                    0x17
+#define SQ_BUFFER_STORE_BYTE                      0x18
+#define SQ_BUFFER_STORE_SHORT                     0x1a
+#define SQ_BUFFER_STORE_DWORD                     0x1c
+#define SQ_BUFFER_STORE_DWORDX2                   0x1d
+#define SQ_BUFFER_STORE_DWORDX3                   0x1e
+#define SQ_BUFFER_STORE_DWORDX4                   0x1f
+#define SQ_BUFFER_STORE_LDS_DWORD                 0x3d
+#define SQ_BUFFER_WBINVL1                         0x3e
+#define SQ_BUFFER_WBINVL1_VOL                     0x3f
+#define SQ_BUFFER_ATOMIC_SWAP                     0x40
+#define SQ_BUFFER_ATOMIC_CMPSWAP                  0x41
+#define SQ_BUFFER_ATOMIC_ADD                      0x42
+#define SQ_BUFFER_ATOMIC_SUB                      0x43
+#define SQ_BUFFER_ATOMIC_SMIN                     0x44
+#define SQ_BUFFER_ATOMIC_UMIN                     0x45
+#define SQ_BUFFER_ATOMIC_SMAX                     0x46
+#define SQ_BUFFER_ATOMIC_UMAX                     0x47
+#define SQ_BUFFER_ATOMIC_AND                      0x48
+#define SQ_BUFFER_ATOMIC_OR                       0x49
+#define SQ_BUFFER_ATOMIC_XOR                      0x4a
+#define SQ_BUFFER_ATOMIC_INC                      0x4b
+#define SQ_BUFFER_ATOMIC_DEC                      0x4c
+#define SQ_BUFFER_ATOMIC_SWAP_X2                  0x60
+#define SQ_BUFFER_ATOMIC_CMPSWAP_X2               0x61
+#define SQ_BUFFER_ATOMIC_ADD_X2                   0x62
+#define SQ_BUFFER_ATOMIC_SUB_X2                   0x63
+#define SQ_BUFFER_ATOMIC_SMIN_X2                  0x64
+#define SQ_BUFFER_ATOMIC_UMIN_X2                  0x65
+#define SQ_BUFFER_ATOMIC_SMAX_X2                  0x66
+#define SQ_BUFFER_ATOMIC_UMAX_X2                  0x67
+#define SQ_BUFFER_ATOMIC_AND_X2                   0x68
+#define SQ_BUFFER_ATOMIC_OR_X2                    0x69
+#define SQ_BUFFER_ATOMIC_XOR_X2                   0x6a
+#define SQ_BUFFER_ATOMIC_INC_X2                   0x6b
+#define SQ_BUFFER_ATOMIC_DEC_X2                   0x6c
+#define SQ_EXEC_LO                                0x7e
+#define SQ_EXEC_HI                                0x7f
+#define SQ_SRC_SCC                                0xfd
+#define SQ_OMOD_OFF                               0x0
+#define SQ_OMOD_M2                                0x1
+#define SQ_OMOD_M4                                0x2
+#define SQ_OMOD_D2                                0x3
+#define SQ_DPP_QUAD_PERM                          0x0
+#define SQ_DPP_ROW_SL1                            0x101
+#define SQ_DPP_ROW_SL2                            0x102
+#define SQ_DPP_ROW_SL3                            0x103
+#define SQ_DPP_ROW_SL4                            0x104
+#define SQ_DPP_ROW_SL5                            0x105
+#define SQ_DPP_ROW_SL6                            0x106
+#define SQ_DPP_ROW_SL7                            0x107
+#define SQ_DPP_ROW_SL8                            0x108
+#define SQ_DPP_ROW_SL9                            0x109
+#define SQ_DPP_ROW_SL10                           0x10a
+#define SQ_DPP_ROW_SL11                           0x10b
+#define SQ_DPP_ROW_SL12                           0x10c
+#define SQ_DPP_ROW_SL13                           0x10d
+#define SQ_DPP_ROW_SL14                           0x10e
+#define SQ_DPP_ROW_SL15                           0x10f
+#define SQ_DPP_ROW_SR1                            0x111
+#define SQ_DPP_ROW_SR2                            0x112
+#define SQ_DPP_ROW_SR3                            0x113
+#define SQ_DPP_ROW_SR4                            0x114
+#define SQ_DPP_ROW_SR5                            0x115
+#define SQ_DPP_ROW_SR6                            0x116
+#define SQ_DPP_ROW_SR7                            0x117
+#define SQ_DPP_ROW_SR8                            0x118
+#define SQ_DPP_ROW_SR9                            0x119
+#define SQ_DPP_ROW_SR10                           0x11a
+#define SQ_DPP_ROW_SR11                           0x11b
+#define SQ_DPP_ROW_SR12                           0x11c
+#define SQ_DPP_ROW_SR13                           0x11d
+#define SQ_DPP_ROW_SR14                           0x11e
+#define SQ_DPP_ROW_SR15                           0x11f
+#define SQ_DPP_ROW_RR1                            0x121
+#define SQ_DPP_ROW_RR2                            0x122
+#define SQ_DPP_ROW_RR3                            0x123
+#define SQ_DPP_ROW_RR4                            0x124
+#define SQ_DPP_ROW_RR5                            0x125
+#define SQ_DPP_ROW_RR6                            0x126
+#define SQ_DPP_ROW_RR7                            0x127
+#define SQ_DPP_ROW_RR8                            0x128
+#define SQ_DPP_ROW_RR9                            0x129
+#define SQ_DPP_ROW_RR10                           0x12a
+#define SQ_DPP_ROW_RR11                           0x12b
+#define SQ_DPP_ROW_RR12                           0x12c
+#define SQ_DPP_ROW_RR13                           0x12d
+#define SQ_DPP_ROW_RR14                           0x12e
+#define SQ_DPP_ROW_RR15                           0x12f
+#define SQ_DPP_WF_SL1                             0x130
+#define SQ_DPP_WF_RL1                             0x134
+#define SQ_DPP_WF_SR1                             0x138
+#define SQ_DPP_WF_RR1                             0x13c
+#define SQ_DPP_ROW_MIRROR                         0x140
+#define SQ_DPP_ROW_HALF_MIRROR                    0x141
+#define SQ_DPP_ROW_BCAST15                        0x142
+#define SQ_DPP_ROW_BCAST31                        0x143
+#define SQ_EXP_GDS0                               0x18
+#define SQ_GS_OP_NOP                              0x0
+#define SQ_GS_OP_CUT                              0x1
+#define SQ_GS_OP_EMIT                             0x2
+#define SQ_GS_OP_EMIT_CUT                         0x3
+#define SQ_IMAGE_LOAD                             0x0
+#define SQ_IMAGE_LOAD_MIP                         0x1
+#define SQ_IMAGE_LOAD_PCK                         0x2
+#define SQ_IMAGE_LOAD_PCK_SGN                     0x3
+#define SQ_IMAGE_LOAD_MIP_PCK                     0x4
+#define SQ_IMAGE_LOAD_MIP_PCK_SGN                 0x5
+#define SQ_IMAGE_STORE                            0x8
+#define SQ_IMAGE_STORE_MIP                        0x9
+#define SQ_IMAGE_STORE_PCK                        0xa
+#define SQ_IMAGE_STORE_MIP_PCK                    0xb
+#define SQ_IMAGE_GET_RESINFO                      0xe
+#define SQ_IMAGE_ATOMIC_SWAP                      0x10
+#define SQ_IMAGE_ATOMIC_CMPSWAP                   0x11
+#define SQ_IMAGE_ATOMIC_ADD                       0x12
+#define SQ_IMAGE_ATOMIC_SUB                       0x13
+#define SQ_IMAGE_ATOMIC_SMIN                      0x14
+#define SQ_IMAGE_ATOMIC_UMIN                      0x15
+#define SQ_IMAGE_ATOMIC_SMAX                      0x16
+#define SQ_IMAGE_ATOMIC_UMAX                      0x17
+#define SQ_IMAGE_ATOMIC_AND                       0x18
+#define SQ_IMAGE_ATOMIC_OR                        0x19
+#define SQ_IMAGE_ATOMIC_XOR                       0x1a
+#define SQ_IMAGE_ATOMIC_INC                       0x1b
+#define SQ_IMAGE_ATOMIC_DEC                       0x1c
+#define SQ_IMAGE_SAMPLE                           0x20
+#define SQ_IMAGE_SAMPLE_CL                        0x21
+#define SQ_IMAGE_SAMPLE_D                         0x22
+#define SQ_IMAGE_SAMPLE_D_CL                      0x23
+#define SQ_IMAGE_SAMPLE_L                         0x24
+#define SQ_IMAGE_SAMPLE_B                         0x25
+#define SQ_IMAGE_SAMPLE_B_CL                      0x26
+#define SQ_IMAGE_SAMPLE_LZ                        0x27
+#define SQ_IMAGE_SAMPLE_C                         0x28
+#define SQ_IMAGE_SAMPLE_C_CL                      0x29
+#define SQ_IMAGE_SAMPLE_C_D                       0x2a
+#define SQ_IMAGE_SAMPLE_C_D_CL                    0x2b
+#define SQ_IMAGE_SAMPLE_C_L                       0x2c
+#define SQ_IMAGE_SAMPLE_C_B                       0x2d
+#define SQ_IMAGE_SAMPLE_C_B_CL                    0x2e
+#define SQ_IMAGE_SAMPLE_C_LZ                      0x2f
+#define SQ_IMAGE_SAMPLE_O                         0x30
+#define SQ_IMAGE_SAMPLE_CL_O                      0x31
+#define SQ_IMAGE_SAMPLE_D_O                       0x32
+#define SQ_IMAGE_SAMPLE_D_CL_O                    0x33
+#define SQ_IMAGE_SAMPLE_L_O                       0x34
+#define SQ_IMAGE_SAMPLE_B_O                       0x35
+#define SQ_IMAGE_SAMPLE_B_CL_O                    0x36
+#define SQ_IMAGE_SAMPLE_LZ_O                      0x37
+#define SQ_IMAGE_SAMPLE_C_O                       0x38
+#define SQ_IMAGE_SAMPLE_C_CL_O                    0x39
+#define SQ_IMAGE_SAMPLE_C_D_O                     0x3a
+#define SQ_IMAGE_SAMPLE_C_D_CL_O                  0x3b
+#define SQ_IMAGE_SAMPLE_C_L_O                     0x3c
+#define SQ_IMAGE_SAMPLE_C_B_O                     0x3d
+#define SQ_IMAGE_SAMPLE_C_B_CL_O                  0x3e
+#define SQ_IMAGE_SAMPLE_C_LZ_O                    0x3f
+#define SQ_IMAGE_GATHER4                          0x40
+#define SQ_IMAGE_GATHER4_CL                       0x41
+#define SQ_IMAGE_GATHER4_L                        0x44
+#define SQ_IMAGE_GATHER4_B                        0x45
+#define SQ_IMAGE_GATHER4_B_CL                     0x46
+#define SQ_IMAGE_GATHER4_LZ                       0x47
+#define SQ_IMAGE_GATHER4_C                        0x48
+#define SQ_IMAGE_GATHER4_C_CL                     0x49
+#define SQ_IMAGE_GATHER4_C_L                      0x4c
+#define SQ_IMAGE_GATHER4_C_B                      0x4d
+#define SQ_IMAGE_GATHER4_C_B_CL                   0x4e
+#define SQ_IMAGE_GATHER4_C_LZ                     0x4f
+#define SQ_IMAGE_GATHER4_O                        0x50
+#define SQ_IMAGE_GATHER4_CL_O                     0x51
+#define SQ_IMAGE_GATHER4_L_O                      0x54
+#define SQ_IMAGE_GATHER4_B_O                      0x55
+#define SQ_IMAGE_GATHER4_B_CL_O                   0x56
+#define SQ_IMAGE_GATHER4_LZ_O                     0x57
+#define SQ_IMAGE_GATHER4_C_O                      0x58
+#define SQ_IMAGE_GATHER4_C_CL_O                   0x59
+#define SQ_IMAGE_GATHER4_C_L_O                    0x5c
+#define SQ_IMAGE_GATHER4_C_B_O                    0x5d
+#define SQ_IMAGE_GATHER4_C_B_CL_O                 0x5e
+#define SQ_IMAGE_GATHER4_C_LZ_O                   0x5f
+#define SQ_IMAGE_GET_LOD                          0x60
+#define SQ_IMAGE_SAMPLE_CD                        0x68
+#define SQ_IMAGE_SAMPLE_CD_CL                     0x69
+#define SQ_IMAGE_SAMPLE_C_CD                      0x6a
+#define SQ_IMAGE_SAMPLE_C_CD_CL                   0x6b
+#define SQ_IMAGE_SAMPLE_CD_O                      0x6c
+#define SQ_IMAGE_SAMPLE_CD_CL_O                   0x6d
+#define SQ_IMAGE_SAMPLE_C_CD_O                    0x6e
+#define SQ_IMAGE_SAMPLE_C_CD_CL_O                 0x6f
+#define SQ_IMAGE_RSRC256                          0x7e
+#define SQ_IMAGE_SAMPLER                          0x7f
+#define SQ_SRC_VCCZ                               0xfb
+#define SQ_SRC_VGPR0                              0x100
+#define SQ_SDWA_BYTE_0                            0x0
+#define SQ_SDWA_BYTE_1                            0x1
+#define SQ_SDWA_BYTE_2                            0x2
+#define SQ_SDWA_BYTE_3                            0x3
+#define SQ_SDWA_WORD_0                            0x4
+#define SQ_SDWA_WORD_1                            0x5
+#define SQ_SDWA_DWORD                             0x6
+#define SQ_XNACK_MASK_LO                          0x68
+#define SQ_XNACK_MASK_HI                          0x69
+#define SQ_TBUFFER_LOAD_FORMAT_X                  0x0
+#define SQ_TBUFFER_LOAD_FORMAT_XY                 0x1
+#define SQ_TBUFFER_LOAD_FORMAT_XYZ                0x2
+#define SQ_TBUFFER_LOAD_FORMAT_XYZW               0x3
+#define SQ_TBUFFER_STORE_FORMAT_X                 0x4
+#define SQ_TBUFFER_STORE_FORMAT_XY                0x5
+#define SQ_TBUFFER_STORE_FORMAT_XYZ               0x6
+#define SQ_TBUFFER_STORE_FORMAT_XYZW              0x7
+#define SQ_TBUFFER_LOAD_FORMAT_D16_X              0x8
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XY             0x9
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ            0xa
+#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW           0xb
+#define SQ_TBUFFER_STORE_FORMAT_D16_X             0xc
+#define SQ_TBUFFER_STORE_FORMAT_D16_XY            0xd
+#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ           0xe
+#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW          0xf
+#define SQ_CHAN_X                                 0x0
+#define SQ_CHAN_Y                                 0x1
+#define SQ_CHAN_Z                                 0x2
+#define SQ_CHAN_W                                 0x3
+#define SQ_V_NOP                                  0x0
+#define SQ_V_MOV_B32                              0x1
+#define SQ_V_READFIRSTLANE_B32                    0x2
+#define SQ_V_CVT_I32_F64                          0x3
+#define SQ_V_CVT_F64_I32                          0x4
+#define SQ_V_CVT_F32_I32                          0x5
+#define SQ_V_CVT_F32_U32                          0x6
+#define SQ_V_CVT_U32_F32                          0x7
+#define SQ_V_CVT_I32_F32                          0x8
+#define SQ_V_MOV_FED_B32                          0x9
+#define SQ_V_CVT_F16_F32                          0xa
+#define SQ_V_CVT_F32_F16                          0xb
+#define SQ_V_CVT_RPI_I32_F32                      0xc
+#define SQ_V_CVT_FLR_I32_F32                      0xd
+#define SQ_V_CVT_OFF_F32_I4                       0xe
+#define SQ_V_CVT_F32_F64                          0xf
+#define SQ_V_CVT_F64_F32                          0x10
+#define SQ_V_CVT_F32_UBYTE0                       0x11
+#define SQ_V_CVT_F32_UBYTE1                       0x12
+#define SQ_V_CVT_F32_UBYTE2                       0x13
+#define SQ_V_CVT_F32_UBYTE3                       0x14
+#define SQ_V_CVT_U32_F64                          0x15
+#define SQ_V_CVT_F64_U32                          0x16
+#define SQ_V_TRUNC_F64                            0x17
+#define SQ_V_CEIL_F64                             0x18
+#define SQ_V_RNDNE_F64                            0x19
+#define SQ_V_FLOOR_F64                            0x1a
+#define SQ_V_FRACT_F32                            0x1b
+#define SQ_V_TRUNC_F32                            0x1c
+#define SQ_V_CEIL_F32                             0x1d
+#define SQ_V_RNDNE_F32                            0x1e
+#define SQ_V_FLOOR_F32                            0x1f
+#define SQ_V_EXP_F32                              0x20
+#define SQ_V_LOG_F32                              0x21
+#define SQ_V_RCP_F32                              0x22
+#define SQ_V_RCP_IFLAG_F32                        0x23
+#define SQ_V_RSQ_F32                              0x24
+#define SQ_V_RCP_F64                              0x25
+#define SQ_V_RSQ_F64                              0x26
+#define SQ_V_SQRT_F32                             0x27
+#define SQ_V_SQRT_F64                             0x28
+#define SQ_V_SIN_F32                              0x29
+#define SQ_V_COS_F32                              0x2a
+#define SQ_V_NOT_B32                              0x2b
+#define SQ_V_BFREV_B32                            0x2c
+#define SQ_V_FFBH_U32                             0x2d
+#define SQ_V_FFBL_B32                             0x2e
+#define SQ_V_FFBH_I32                             0x2f
+#define SQ_V_FREXP_EXP_I32_F64                    0x30
+#define SQ_V_FREXP_MANT_F64                       0x31
+#define SQ_V_FRACT_F64                            0x32
+#define SQ_V_FREXP_EXP_I32_F32                    0x33
+#define SQ_V_FREXP_MANT_F32                       0x34
+#define SQ_V_CLREXCP                              0x35
+#define SQ_V_MOVRELD_B32                          0x36
+#define SQ_V_MOVRELS_B32                          0x37
+#define SQ_V_MOVRELSD_B32                         0x38
+#define SQ_V_CVT_F16_U16                          0x39
+#define SQ_V_CVT_F16_I16                          0x3a
+#define SQ_V_CVT_U16_F16                          0x3b
+#define SQ_V_CVT_I16_F16                          0x3c
+#define SQ_V_RCP_F16                              0x3d
+#define SQ_V_SQRT_F16                             0x3e
+#define SQ_V_RSQ_F16                              0x3f
+#define SQ_V_LOG_F16                              0x40
+#define SQ_V_EXP_F16                              0x41
+#define SQ_V_FREXP_MANT_F16                       0x42
+#define SQ_V_FREXP_EXP_I16_F16                    0x43
+#define SQ_V_FLOOR_F16                            0x44
+#define SQ_V_CEIL_F16                             0x45
+#define SQ_V_TRUNC_F16                            0x46
+#define SQ_V_RNDNE_F16                            0x47
+#define SQ_V_FRACT_F16                            0x48
+#define SQ_V_SIN_F16                              0x49
+#define SQ_V_COS_F16                              0x4a
+#define SQ_V_EXP_LEGACY_F32                       0x4b
+#define SQ_V_LOG_LEGACY_F32                       0x4c
+#define SQ_SRC_SDWA                               0xf9
+#define SQ_V_OPC_OFFSET                           0x0
+#define SQ_V_OP2_OFFSET                           0x100
+#define SQ_V_OP1_OFFSET                           0x140
+#define SQ_V_INTRP_OFFSET                         0x270
+#define SQ_V_INTERP_P1_F32                        0x0
+#define SQ_V_INTERP_P2_F32                        0x1
+#define SQ_V_INTERP_MOV_F32                       0x2
+#define SQ_S_NOP                                  0x0
+#define SQ_S_ENDPGM                               0x1
+#define SQ_S_BRANCH                               0x2
+#define SQ_S_WAKEUP                               0x3
+#define SQ_S_CBRANCH_SCC0                         0x4
+#define SQ_S_CBRANCH_SCC1                         0x5
+#define SQ_S_CBRANCH_VCCZ                         0x6
+#define SQ_S_CBRANCH_VCCNZ                        0x7
+#define SQ_S_CBRANCH_EXECZ                        0x8
+#define SQ_S_CBRANCH_EXECNZ                       0x9
+#define SQ_S_BARRIER                              0xa
+#define SQ_S_SETKILL                              0xb
+#define SQ_S_WAITCNT                              0xc
+#define SQ_S_SETHALT                              0xd
+#define SQ_S_SLEEP                                0xe
+#define SQ_S_SETPRIO                              0xf
+#define SQ_S_SENDMSG                              0x10
+#define SQ_S_SENDMSGHALT                          0x11
+#define SQ_S_TRAP                                 0x12
+#define SQ_S_ICACHE_INV                           0x13
+#define SQ_S_INCPERFLEVEL                         0x14
+#define SQ_S_DECPERFLEVEL                         0x15
+#define SQ_S_TTRACEDATA                           0x16
+#define SQ_S_CBRANCH_CDBGSYS                      0x17
+#define SQ_S_CBRANCH_CDBGUSER                     0x18
+#define SQ_S_CBRANCH_CDBGSYS_OR_USER              0x19
+#define SQ_S_CBRANCH_CDBGSYS_AND_USER             0x1a
+#define SQ_S_ENDPGM_SAVED                         0x1b
+#define SQ_S_SET_GPR_IDX_OFF                      0x1c
+#define SQ_S_SET_GPR_IDX_MODE                     0x1d
+#define SQ_SRC_DPP                                0xfa
+#define SQ_SRC_LITERAL                            0xff
+#define SQ_VCC_LO                                 0x6a
+#define SQ_VCC_HI                                 0x6b
+#define SQ_PARAM_P10                              0x0
+#define SQ_PARAM_P20                              0x1
+#define SQ_PARAM_P0                               0x2
+#define SQ_SRC_LDS_DIRECT                         0xfe
+#define SQ_V_CNDMASK_B32                          0x0
+#define SQ_V_ADD_F32                              0x1
+#define SQ_V_SUB_F32                              0x2
+#define SQ_V_SUBREV_F32                           0x3
+#define SQ_V_MUL_LEGACY_F32                       0x4
+#define SQ_V_MUL_F32                              0x5
+#define SQ_V_MUL_I32_I24                          0x6
+#define SQ_V_MUL_HI_I32_I24                       0x7
+#define SQ_V_MUL_U32_U24                          0x8
+#define SQ_V_MUL_HI_U32_U24                       0x9
+#define SQ_V_MIN_F32                              0xa
+#define SQ_V_MAX_F32                              0xb
+#define SQ_V_MIN_I32                              0xc
+#define SQ_V_MAX_I32                              0xd
+#define SQ_V_MIN_U32                              0xe
+#define SQ_V_MAX_U32                              0xf
+#define SQ_V_LSHRREV_B32                          0x10
+#define SQ_V_ASHRREV_I32                          0x11
+#define SQ_V_LSHLREV_B32                          0x12
+#define SQ_V_AND_B32                              0x13
+#define SQ_V_OR_B32                               0x14
+#define SQ_V_XOR_B32                              0x15
+#define SQ_V_MAC_F32                              0x16
+#define SQ_V_MADMK_F32                            0x17
+#define SQ_V_MADAK_F32                            0x18
+#define SQ_V_ADD_U32                              0x19
+#define SQ_V_SUB_U32                              0x1a
+#define SQ_V_SUBREV_U32                           0x1b
+#define SQ_V_ADDC_U32                             0x1c
+#define SQ_V_SUBB_U32                             0x1d
+#define SQ_V_SUBBREV_U32                          0x1e
+#define SQ_V_ADD_F16                              0x1f
+#define SQ_V_SUB_F16                              0x20
+#define SQ_V_SUBREV_F16                           0x21
+#define SQ_V_MUL_F16                              0x22
+#define SQ_V_MAC_F16                              0x23
+#define SQ_V_MADMK_F16                            0x24
+#define SQ_V_MADAK_F16                            0x25
+#define SQ_V_ADD_U16                              0x26
+#define SQ_V_SUB_U16                              0x27
+#define SQ_V_SUBREV_U16                           0x28
+#define SQ_V_MUL_LO_U16                           0x29
+#define SQ_V_LSHLREV_B16                          0x2a
+#define SQ_V_LSHRREV_B16                          0x2b
+#define SQ_V_ASHRREV_I16                          0x2c
+#define SQ_V_MAX_F16                              0x2d
+#define SQ_V_MIN_F16                              0x2e
+#define SQ_V_MAX_U16                              0x2f
+#define SQ_V_MAX_I16                              0x30
+#define SQ_V_MIN_U16                              0x31
+#define SQ_V_MIN_I16                              0x32
+#define SQ_V_LDEXP_F16                            0x33
+#define SQ_FLAT_LOAD_UBYTE                        0x10
+#define SQ_FLAT_LOAD_SBYTE                        0x11
+#define SQ_FLAT_LOAD_USHORT                       0x12
+#define SQ_FLAT_LOAD_SSHORT                       0x13
+#define SQ_FLAT_LOAD_DWORD                        0x14
+#define SQ_FLAT_LOAD_DWORDX2                      0x15
+#define SQ_FLAT_LOAD_DWORDX3                      0x16
+#define SQ_FLAT_LOAD_DWORDX4                      0x17
+#define SQ_FLAT_STORE_BYTE                        0x18
+#define SQ_FLAT_STORE_SHORT                       0x1a
+#define SQ_FLAT_STORE_DWORD                       0x1c
+#define SQ_FLAT_STORE_DWORDX2                     0x1d
+#define SQ_FLAT_STORE_DWORDX3                     0x1e
+#define SQ_FLAT_STORE_DWORDX4                     0x1f
+#define SQ_FLAT_ATOMIC_SWAP                       0x40
+#define SQ_FLAT_ATOMIC_CMPSWAP                    0x41
+#define SQ_FLAT_ATOMIC_ADD                        0x42
+#define SQ_FLAT_ATOMIC_SUB                        0x43
+#define SQ_FLAT_ATOMIC_SMIN                       0x44
+#define SQ_FLAT_ATOMIC_UMIN                       0x45
+#define SQ_FLAT_ATOMIC_SMAX                       0x46
+#define SQ_FLAT_ATOMIC_UMAX                       0x47
+#define SQ_FLAT_ATOMIC_AND                        0x48
+#define SQ_FLAT_ATOMIC_OR                         0x49
+#define SQ_FLAT_ATOMIC_XOR                        0x4a
+#define SQ_FLAT_ATOMIC_INC                        0x4b
+#define SQ_FLAT_ATOMIC_DEC                        0x4c
+#define SQ_FLAT_ATOMIC_SWAP_X2                    0x60
+#define SQ_FLAT_ATOMIC_CMPSWAP_X2                 0x61
+#define SQ_FLAT_ATOMIC_ADD_X2                     0x62
+#define SQ_FLAT_ATOMIC_SUB_X2                     0x63
+#define SQ_FLAT_ATOMIC_SMIN_X2                    0x64
+#define SQ_FLAT_ATOMIC_UMIN_X2                    0x65
+#define SQ_FLAT_ATOMIC_SMAX_X2                    0x66
+#define SQ_FLAT_ATOMIC_UMAX_X2                    0x67
+#define SQ_FLAT_ATOMIC_AND_X2                     0x68
+#define SQ_FLAT_ATOMIC_OR_X2                      0x69
+#define SQ_FLAT_ATOMIC_XOR_X2                     0x6a
+#define SQ_FLAT_ATOMIC_INC_X2                     0x6b
+#define SQ_FLAT_ATOMIC_DEC_X2                     0x6c
+#define SQ_S_CMP_EQ_I32                           0x0
+#define SQ_S_CMP_LG_I32                           0x1
+#define SQ_S_CMP_GT_I32                           0x2
+#define SQ_S_CMP_GE_I32                           0x3
+#define SQ_S_CMP_LT_I32                           0x4
+#define SQ_S_CMP_LE_I32                           0x5
+#define SQ_S_CMP_EQ_U32                           0x6
+#define SQ_S_CMP_LG_U32                           0x7
+#define SQ_S_CMP_GT_U32                           0x8
+#define SQ_S_CMP_GE_U32                           0x9
+#define SQ_S_CMP_LT_U32                           0xa
+#define SQ_S_CMP_LE_U32                           0xb
+#define SQ_S_BITCMP0_B32                          0xc
+#define SQ_S_BITCMP1_B32                          0xd
+#define SQ_S_BITCMP0_B64                          0xe
+#define SQ_S_BITCMP1_B64                          0xf
+#define SQ_S_SETVSKIP                             0x10
+#define SQ_S_SET_GPR_IDX_ON                       0x11
+#define SQ_S_CMP_EQ_U64                           0x12
+#define SQ_S_CMP_LG_U64                           0x13
+#define SQ_M0                                     0x7c
+#define SQ_V_MAD_LEGACY_F32                       0x1c0
+#define SQ_V_MAD_F32                              0x1c1
+#define SQ_V_MAD_I32_I24                          0x1c2
+#define SQ_V_MAD_U32_U24                          0x1c3
+#define SQ_V_CUBEID_F32                           0x1c4
+#define SQ_V_CUBESC_F32                           0x1c5
+#define SQ_V_CUBETC_F32                           0x1c6
+#define SQ_V_CUBEMA_F32                           0x1c7
+#define SQ_V_BFE_U32                              0x1c8
+#define SQ_V_BFE_I32                              0x1c9
+#define SQ_V_BFI_B32                              0x1ca
+#define SQ_V_FMA_F32                              0x1cb
+#define SQ_V_FMA_F64                              0x1cc
+#define SQ_V_LERP_U8                              0x1cd
+#define SQ_V_ALIGNBIT_B32                         0x1ce
+#define SQ_V_ALIGNBYTE_B32                        0x1cf
+#define SQ_V_MIN3_F32                             0x1d0
+#define SQ_V_MIN3_I32                             0x1d1
+#define SQ_V_MIN3_U32                             0x1d2
+#define SQ_V_MAX3_F32                             0x1d3
+#define SQ_V_MAX3_I32                             0x1d4
+#define SQ_V_MAX3_U32                             0x1d5
+#define SQ_V_MED3_F32                             0x1d6
+#define SQ_V_MED3_I32                             0x1d7
+#define SQ_V_MED3_U32                             0x1d8
+#define SQ_V_SAD_U8                               0x1d9
+#define SQ_V_SAD_HI_U8                            0x1da
+#define SQ_V_SAD_U16                              0x1db
+#define SQ_V_SAD_U32                              0x1dc
+#define SQ_V_CVT_PK_U8_F32                        0x1dd
+#define SQ_V_DIV_FIXUP_F32                        0x1de
+#define SQ_V_DIV_FIXUP_F64                        0x1df
+#define SQ_V_DIV_SCALE_F32                        0x1e0
+#define SQ_V_DIV_SCALE_F64                        0x1e1
+#define SQ_V_DIV_FMAS_F32                         0x1e2
+#define SQ_V_DIV_FMAS_F64                         0x1e3
+#define SQ_V_MSAD_U8                              0x1e4
+#define SQ_V_QSAD_PK_U16_U8                       0x1e5
+#define SQ_V_MQSAD_PK_U16_U8                      0x1e6
+#define SQ_V_MQSAD_U32_U8                         0x1e7
+#define SQ_V_MAD_U64_U32                          0x1e8
+#define SQ_V_MAD_I64_I32                          0x1e9
+#define SQ_V_MAD_F16                              0x1ea
+#define SQ_V_MAD_U16                              0x1eb
+#define SQ_V_MAD_I16                              0x1ec
+#define SQ_V_PERM_B32                             0x1ed
+#define SQ_V_FMA_F16                              0x1ee
+#define SQ_V_DIV_FIXUP_F16                        0x1ef
+#define SQ_V_CVT_PKACCUM_U8_F32                   0x1f0
+#define SQ_V_INTERP_P1LL_F16                      0x274
+#define SQ_V_INTERP_P1LV_F16                      0x275
+#define SQ_V_INTERP_P2_F16                        0x276
+#define SQ_V_ADD_F64                              0x280
+#define SQ_V_MUL_F64                              0x281
+#define SQ_V_MIN_F64                              0x282
+#define SQ_V_MAX_F64                              0x283
+#define SQ_V_LDEXP_F64                            0x284
+#define SQ_V_MUL_LO_U32                           0x285
+#define SQ_V_MUL_HI_U32                           0x286
+#define SQ_V_MUL_HI_I32                           0x287
+#define SQ_V_LDEXP_F32                            0x288
+#define SQ_V_READLANE_B32                         0x289
+#define SQ_V_WRITELANE_B32                        0x28a
+#define SQ_V_BCNT_U32_B32                         0x28b
+#define SQ_V_MBCNT_LO_U32_B32                     0x28c
+#define SQ_V_MBCNT_HI_U32_B32                     0x28d
+#define SQ_V_MAC_LEGACY_F32                       0x28e
+#define SQ_V_LSHLREV_B64                          0x28f
+#define SQ_V_LSHRREV_B64                          0x290
+#define SQ_V_ASHRREV_I64                          0x291
+#define SQ_V_TRIG_PREOP_F64                       0x292
+#define SQ_V_BFM_B32                              0x293
+#define SQ_V_CVT_PKNORM_I16_F32                   0x294
+#define SQ_V_CVT_PKNORM_U16_F32                   0x295
+#define SQ_V_CVT_PKRTZ_F16_F32                    0x296
+#define SQ_V_CVT_PK_U16_U32                       0x297
+#define SQ_V_CVT_PK_I16_I32                       0x298
+#define SQ_VCC_ALL                                0x0
+#define SQ_SRC_EXECZ                              0xfc
+#define SQ_FLAT_SCRATCH_LO                        0x66
+#define SQ_FLAT_SCRATCH_HI                        0x67
+#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT            0x1
+#define SQ_SYSMSG_OP_REG_RD                       0x2
+#define SQ_SYSMSG_OP_HOST_TRAP_ACK                0x3
+#define SQ_SYSMSG_OP_TTRACE_PC                    0x4
+#define SQ_HW_REG_MODE                            0x1
+#define SQ_HW_REG_STATUS                          0x2
+#define SQ_HW_REG_TRAPSTS                         0x3
+#define SQ_HW_REG_HW_ID                           0x4
+#define SQ_HW_REG_GPR_ALLOC                       0x5
+#define SQ_HW_REG_LDS_ALLOC                       0x6
+#define SQ_HW_REG_IB_STS                          0x7
+#define SQ_HW_REG_PC_LO                           0x8
+#define SQ_HW_REG_PC_HI                           0x9
+#define SQ_HW_REG_INST_DW0                        0xa
+#define SQ_HW_REG_INST_DW1                        0xb
+#define SQ_HW_REG_IB_DBG0                         0xc
+#define SQ_HW_REG_IB_DBG1                         0xd
+#define SQ_DPP_BOUND_OFF                          0x0
+#define SQ_DPP_BOUND_ZERO                         0x1
+#define SQ_R1                                     0x1
+#define SQ_R2                                     0x2
+#define SQ_R3                                     0x3
+#define SQ_R4                                     0x4
+#define SQ_R5                                     0x5
+#define SQ_R6                                     0x6
+#define SQ_R7                                     0x7
+#define SQ_R8                                     0x8
+#define SQ_R9                                     0x9
+#define SQ_R10                                    0xa
+#define SQ_R11                                    0xb
+#define SQ_R12                                    0xc
+#define SQ_R13                                    0xd
+#define SQ_R14                                    0xe
+#define SQ_R15                                    0xf
+#define SQ_S_ADD_U32                              0x0
+#define SQ_S_SUB_U32                              0x1
+#define SQ_S_ADD_I32                              0x2
+#define SQ_S_SUB_I32                              0x3
+#define SQ_S_ADDC_U32                             0x4
+#define SQ_S_SUBB_U32                             0x5
+#define SQ_S_MIN_I32                              0x6
+#define SQ_S_MIN_U32                              0x7
+#define SQ_S_MAX_I32                              0x8
+#define SQ_S_MAX_U32                              0x9
+#define SQ_S_CSELECT_B32                          0xa
+#define SQ_S_CSELECT_B64                          0xb
+#define SQ_S_AND_B32                              0xc
+#define SQ_S_AND_B64                              0xd
+#define SQ_S_OR_B32                               0xe
+#define SQ_S_OR_B64                               0xf
+#define SQ_S_XOR_B32                              0x10
+#define SQ_S_XOR_B64                              0x11
+#define SQ_S_ANDN2_B32                            0x12
+#define SQ_S_ANDN2_B64                            0x13
+#define SQ_S_ORN2_B32                             0x14
+#define SQ_S_ORN2_B64                             0x15
+#define SQ_S_NAND_B32                             0x16
+#define SQ_S_NAND_B64                             0x17
+#define SQ_S_NOR_B32                              0x18
+#define SQ_S_NOR_B64                              0x19
+#define SQ_S_XNOR_B32                             0x1a
+#define SQ_S_XNOR_B64                             0x1b
+#define SQ_S_LSHL_B32                             0x1c
+#define SQ_S_LSHL_B64                             0x1d
+#define SQ_S_LSHR_B32                             0x1e
+#define SQ_S_LSHR_B64                             0x1f
+#define SQ_S_ASHR_I32                             0x20
+#define SQ_S_ASHR_I64                             0x21
+#define SQ_S_BFM_B32                              0x22
+#define SQ_S_BFM_B64                              0x23
+#define SQ_S_MUL_I32                              0x24
+#define SQ_S_BFE_U32                              0x25
+#define SQ_S_BFE_I32                              0x26
+#define SQ_S_BFE_U64                              0x27
+#define SQ_S_BFE_I64                              0x28
+#define SQ_S_CBRANCH_G_FORK                       0x29
+#define SQ_S_ABSDIFF_I32                          0x2a
+#define SQ_S_RFE_RESTORE_B64                      0x2b
+#define SQ_MSG_INTERRUPT                          0x1
+#define SQ_MSG_GS                                 0x2
+#define SQ_MSG_GS_DONE                            0x3
+#define SQ_MSG_SAVEWAVE                           0x4
+#define SQ_MSG_SYSMSG                             0xf
+typedef enum TEX_BORDER_COLOR_TYPE {
+       TEX_BorderColor_TransparentBlack                 = 0x0,
+       TEX_BorderColor_OpaqueBlack                      = 0x1,
+       TEX_BorderColor_OpaqueWhite                      = 0x2,
+       TEX_BorderColor_Register                         = 0x3,
+} TEX_BORDER_COLOR_TYPE;
+typedef enum TEX_CHROMA_KEY {
+       TEX_ChromaKey_Disabled                           = 0x0,
+       TEX_ChromaKey_Kill                               = 0x1,
+       TEX_ChromaKey_Blend                              = 0x2,
+       TEX_ChromaKey_RESERVED_3                         = 0x3,
+} TEX_CHROMA_KEY;
+typedef enum TEX_CLAMP {
+       TEX_Clamp_Repeat                                 = 0x0,
+       TEX_Clamp_Mirror                                 = 0x1,
+       TEX_Clamp_ClampToLast                            = 0x2,
+       TEX_Clamp_MirrorOnceToLast                       = 0x3,
+       TEX_Clamp_ClampHalfToBorder                      = 0x4,
+       TEX_Clamp_MirrorOnceHalfToBorder                 = 0x5,
+       TEX_Clamp_ClampToBorder                          = 0x6,
+       TEX_Clamp_MirrorOnceToBorder                     = 0x7,
+} TEX_CLAMP;
+typedef enum TEX_COORD_TYPE {
+       TEX_CoordType_Unnormalized                       = 0x0,
+       TEX_CoordType_Normalized                         = 0x1,
+} TEX_COORD_TYPE;
+typedef enum TEX_DEPTH_COMPARE_FUNCTION {
+       TEX_DepthCompareFunction_Never                   = 0x0,
+       TEX_DepthCompareFunction_Less                    = 0x1,
+       TEX_DepthCompareFunction_Equal                   = 0x2,
+       TEX_DepthCompareFunction_LessEqual               = 0x3,
+       TEX_DepthCompareFunction_Greater                 = 0x4,
+       TEX_DepthCompareFunction_NotEqual                = 0x5,
+       TEX_DepthCompareFunction_GreaterEqual            = 0x6,
+       TEX_DepthCompareFunction_Always                  = 0x7,
+} TEX_DEPTH_COMPARE_FUNCTION;
+typedef enum TEX_DIM {
+       TEX_Dim_1D                                       = 0x0,
+       TEX_Dim_2D                                       = 0x1,
+       TEX_Dim_3D                                       = 0x2,
+       TEX_Dim_CubeMap                                  = 0x3,
+       TEX_Dim_1DArray                                  = 0x4,
+       TEX_Dim_2DArray                                  = 0x5,
+       TEX_Dim_2D_MSAA                                  = 0x6,
+       TEX_Dim_2DArray_MSAA                             = 0x7,
+} TEX_DIM;
+typedef enum TEX_FORMAT_COMP {
+       TEX_FormatComp_Unsigned                          = 0x0,
+       TEX_FormatComp_Signed                            = 0x1,
+       TEX_FormatComp_UnsignedBiased                    = 0x2,
+       TEX_FormatComp_RESERVED_3                        = 0x3,
+} TEX_FORMAT_COMP;
+typedef enum TEX_MAX_ANISO_RATIO {
+       TEX_MaxAnisoRatio_1to1                           = 0x0,
+       TEX_MaxAnisoRatio_2to1                           = 0x1,
+       TEX_MaxAnisoRatio_4to1                           = 0x2,
+       TEX_MaxAnisoRatio_8to1                           = 0x3,
+       TEX_MaxAnisoRatio_16to1                          = 0x4,
+       TEX_MaxAnisoRatio_RESERVED_5                     = 0x5,
+       TEX_MaxAnisoRatio_RESERVED_6                     = 0x6,
+       TEX_MaxAnisoRatio_RESERVED_7                     = 0x7,
+} TEX_MAX_ANISO_RATIO;
+typedef enum TEX_MIP_FILTER {
+       TEX_MipFilter_None                               = 0x0,
+       TEX_MipFilter_Point                              = 0x1,
+       TEX_MipFilter_Linear                             = 0x2,
+       TEX_MipFilter_Point_Aniso_Adj                    = 0x3,
+} TEX_MIP_FILTER;
+typedef enum TEX_REQUEST_SIZE {
+       TEX_RequestSize_32B                              = 0x0,
+       TEX_RequestSize_64B                              = 0x1,
+       TEX_RequestSize_128B                             = 0x2,
+       TEX_RequestSize_2X64B                            = 0x3,
+} TEX_REQUEST_SIZE;
+typedef enum TEX_SAMPLER_TYPE {
+       TEX_SamplerType_Invalid                          = 0x0,
+       TEX_SamplerType_Valid                            = 0x1,
+} TEX_SAMPLER_TYPE;
+typedef enum TEX_XY_FILTER {
+       TEX_XYFilter_Point                               = 0x0,
+       TEX_XYFilter_Linear                              = 0x1,
+       TEX_XYFilter_AnisoPoint                          = 0x2,
+       TEX_XYFilter_AnisoLinear                         = 0x3,
+} TEX_XY_FILTER;
+typedef enum TEX_Z_FILTER {
+       TEX_ZFilter_None                                 = 0x0,
+       TEX_ZFilter_Point                                = 0x1,
+       TEX_ZFilter_Linear                               = 0x2,
+       TEX_ZFilter_RESERVED_3                           = 0x3,
+} TEX_Z_FILTER;
+typedef enum VTX_CLAMP {
+       VTX_Clamp_ClampToZero                            = 0x0,
+       VTX_Clamp_ClampToNAN                             = 0x1,
+} VTX_CLAMP;
+typedef enum VTX_FETCH_TYPE {
+       VTX_FetchType_VertexData                         = 0x0,
+       VTX_FetchType_InstanceData                       = 0x1,
+       VTX_FetchType_NoIndexOffset                      = 0x2,
+       VTX_FetchType_RESERVED_3                         = 0x3,
+} VTX_FETCH_TYPE;
+typedef enum VTX_FORMAT_COMP_ALL {
+       VTX_FormatCompAll_Unsigned                       = 0x0,
+       VTX_FormatCompAll_Signed                         = 0x1,
+} VTX_FORMAT_COMP_ALL;
+typedef enum VTX_MEM_REQUEST_SIZE {
+       VTX_MemRequestSize_32B                           = 0x0,
+       VTX_MemRequestSize_64B                           = 0x1,
+} VTX_MEM_REQUEST_SIZE;
+typedef enum TVX_DATA_FORMAT {
+       TVX_FMT_INVALID                                  = 0x0,
+       TVX_FMT_8                                        = 0x1,
+       TVX_FMT_4_4                                      = 0x2,
+       TVX_FMT_3_3_2                                    = 0x3,
+       TVX_FMT_RESERVED_4                               = 0x4,
+       TVX_FMT_16                                       = 0x5,
+       TVX_FMT_16_FLOAT                                 = 0x6,
+       TVX_FMT_8_8                                      = 0x7,
+       TVX_FMT_5_6_5                                    = 0x8,
+       TVX_FMT_6_5_5                                    = 0x9,
+       TVX_FMT_1_5_5_5                                  = 0xa,
+       TVX_FMT_4_4_4_4                                  = 0xb,
+       TVX_FMT_5_5_5_1                                  = 0xc,
+       TVX_FMT_32                                       = 0xd,
+       TVX_FMT_32_FLOAT                                 = 0xe,
+       TVX_FMT_16_16                                    = 0xf,
+       TVX_FMT_16_16_FLOAT                              = 0x10,
+       TVX_FMT_8_24                                     = 0x11,
+       TVX_FMT_8_24_FLOAT                               = 0x12,
+       TVX_FMT_24_8                                     = 0x13,
+       TVX_FMT_24_8_FLOAT                               = 0x14,
+       TVX_FMT_10_11_11                                 = 0x15,
+       TVX_FMT_10_11_11_FLOAT                           = 0x16,
+       TVX_FMT_11_11_10                                 = 0x17,
+       TVX_FMT_11_11_10_FLOAT                           = 0x18,
+       TVX_FMT_2_10_10_10                               = 0x19,
+       TVX_FMT_8_8_8_8                                  = 0x1a,
+       TVX_FMT_10_10_10_2                               = 0x1b,
+       TVX_FMT_X24_8_32_FLOAT                           = 0x1c,
+       TVX_FMT_32_32                                    = 0x1d,
+       TVX_FMT_32_32_FLOAT                              = 0x1e,
+       TVX_FMT_16_16_16_16                              = 0x1f,
+       TVX_FMT_16_16_16_16_FLOAT                        = 0x20,
+       TVX_FMT_RESERVED_33                              = 0x21,
+       TVX_FMT_32_32_32_32                              = 0x22,
+       TVX_FMT_32_32_32_32_FLOAT                        = 0x23,
+       TVX_FMT_RESERVED_36                              = 0x24,
+       TVX_FMT_1                                        = 0x25,
+       TVX_FMT_1_REVERSED                               = 0x26,
+       TVX_FMT_GB_GR                                    = 0x27,
+       TVX_FMT_BG_RG                                    = 0x28,
+       TVX_FMT_32_AS_8                                  = 0x29,
+       TVX_FMT_32_AS_8_8                                = 0x2a,
+       TVX_FMT_5_9_9_9_SHAREDEXP                        = 0x2b,
+       TVX_FMT_8_8_8                                    = 0x2c,
+       TVX_FMT_16_16_16                                 = 0x2d,
+       TVX_FMT_16_16_16_FLOAT                           = 0x2e,
+       TVX_FMT_32_32_32                                 = 0x2f,
+       TVX_FMT_32_32_32_FLOAT                           = 0x30,
+       TVX_FMT_BC1                                      = 0x31,
+       TVX_FMT_BC2                                      = 0x32,
+       TVX_FMT_BC3                                      = 0x33,
+       TVX_FMT_BC4                                      = 0x34,
+       TVX_FMT_BC5                                      = 0x35,
+       TVX_FMT_APC0                                     = 0x36,
+       TVX_FMT_APC1                                     = 0x37,
+       TVX_FMT_APC2                                     = 0x38,
+       TVX_FMT_APC3                                     = 0x39,
+       TVX_FMT_APC4                                     = 0x3a,
+       TVX_FMT_APC5                                     = 0x3b,
+       TVX_FMT_APC6                                     = 0x3c,
+       TVX_FMT_APC7                                     = 0x3d,
+       TVX_FMT_CTX1                                     = 0x3e,
+       TVX_FMT_RESERVED_63                              = 0x3f,
+} TVX_DATA_FORMAT;
+typedef enum TVX_DST_SEL {
+       TVX_DstSel_X                                     = 0x0,
+       TVX_DstSel_Y                                     = 0x1,
+       TVX_DstSel_Z                                     = 0x2,
+       TVX_DstSel_W                                     = 0x3,
+       TVX_DstSel_0f                                    = 0x4,
+       TVX_DstSel_1f                                    = 0x5,
+       TVX_DstSel_RESERVED_6                            = 0x6,
+       TVX_DstSel_Mask                                  = 0x7,
+} TVX_DST_SEL;
+typedef enum TVX_ENDIAN_SWAP {
+       TVX_EndianSwap_None                              = 0x0,
+       TVX_EndianSwap_8in16                             = 0x1,
+       TVX_EndianSwap_8in32                             = 0x2,
+       TVX_EndianSwap_8in64                             = 0x3,
+} TVX_ENDIAN_SWAP;
+typedef enum TVX_INST {
+       TVX_Inst_NormalVertexFetch                       = 0x0,
+       TVX_Inst_SemanticVertexFetch                     = 0x1,
+       TVX_Inst_RESERVED_2                              = 0x2,
+       TVX_Inst_LD                                      = 0x3,
+       TVX_Inst_GetTextureResInfo                       = 0x4,
+       TVX_Inst_GetNumberOfSamples                      = 0x5,
+       TVX_Inst_GetLOD                                  = 0x6,
+       TVX_Inst_GetGradientsH                           = 0x7,
+       TVX_Inst_GetGradientsV                           = 0x8,
+       TVX_Inst_SetTextureOffsets                       = 0x9,
+       TVX_Inst_KeepGradients                           = 0xa,
+       TVX_Inst_SetGradientsH                           = 0xb,
+       TVX_Inst_SetGradientsV                           = 0xc,
+       TVX_Inst_Pass                                    = 0xd,
+       TVX_Inst_GetBufferResInfo                        = 0xe,
+       TVX_Inst_RESERVED_15                             = 0xf,
+       TVX_Inst_Sample                                  = 0x10,
+       TVX_Inst_Sample_L                                = 0x11,
+       TVX_Inst_Sample_LB                               = 0x12,
+       TVX_Inst_Sample_LZ                               = 0x13,
+       TVX_Inst_Sample_G                                = 0x14,
+       TVX_Inst_Gather4                                 = 0x15,
+       TVX_Inst_Sample_G_LB                             = 0x16,
+       TVX_Inst_Gather4_O                               = 0x17,
+       TVX_Inst_Sample_C                                = 0x18,
+       TVX_Inst_Sample_C_L                              = 0x19,
+       TVX_Inst_Sample_C_LB                             = 0x1a,
+       TVX_Inst_Sample_C_LZ                             = 0x1b,
+       TVX_Inst_Sample_C_G                              = 0x1c,
+       TVX_Inst_Gather4_C                               = 0x1d,
+       TVX_Inst_Sample_C_G_LB                           = 0x1e,
+       TVX_Inst_Gather4_C_O                             = 0x1f,
+} TVX_INST;
+typedef enum TVX_NUM_FORMAT_ALL {
+       TVX_NumFormatAll_Norm                            = 0x0,
+       TVX_NumFormatAll_Int                             = 0x1,
+       TVX_NumFormatAll_Scaled                          = 0x2,
+       TVX_NumFormatAll_RESERVED_3                      = 0x3,
+} TVX_NUM_FORMAT_ALL;
+typedef enum TVX_SRC_SEL {
+       TVX_SrcSel_X                                     = 0x0,
+       TVX_SrcSel_Y                                     = 0x1,
+       TVX_SrcSel_Z                                     = 0x2,
+       TVX_SrcSel_W                                     = 0x3,
+       TVX_SrcSel_0f                                    = 0x4,
+       TVX_SrcSel_1f                                    = 0x5,
+} TVX_SRC_SEL;
+typedef enum TVX_SRF_MODE_ALL {
+       TVX_SRFModeAll_ZCMO                              = 0x0,
+       TVX_SRFModeAll_NZ                                = 0x1,
+} TVX_SRF_MODE_ALL;
+typedef enum TVX_TYPE {
+       TVX_Type_InvalidTextureResource                  = 0x0,
+       TVX_Type_InvalidVertexBuffer                     = 0x1,
+       TVX_Type_ValidTextureResource                    = 0x2,
+       TVX_Type_ValidVertexBuffer                       = 0x3,
+} TVX_TYPE;
+typedef enum TC_OP_MASKS {
+       TC_OP_MASK_FLUSH_DENROM                          = 0x8,
+       TC_OP_MASK_64                                    = 0x20,
+       TC_OP_MASK_NO_RTN                                = 0x40,
+} TC_OP_MASKS;
+typedef enum TC_OP {
+       TC_OP_READ                                       = 0x0,
+       TC_OP_ATOMIC_FCMPSWAP_RTN_32                     = 0x1,
+       TC_OP_ATOMIC_FMIN_RTN_32                         = 0x2,
+       TC_OP_ATOMIC_FMAX_RTN_32                         = 0x3,
+       TC_OP_RESERVED_FOP_RTN_32_0                      = 0x4,
+       TC_OP_RESERVED_FOP_RTN_32_1                      = 0x5,
+       TC_OP_RESERVED_FOP_RTN_32_2                      = 0x6,
+       TC_OP_ATOMIC_SWAP_RTN_32                         = 0x7,
+       TC_OP_ATOMIC_CMPSWAP_RTN_32                      = 0x8,
+       TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32        = 0x9,
+       TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32            = 0xa,
+       TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32            = 0xb,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0         = 0xc,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1         = 0xd,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2         = 0xe,
+       TC_OP_ATOMIC_ADD_RTN_32                          = 0xf,
+       TC_OP_ATOMIC_SUB_RTN_32                          = 0x10,
+       TC_OP_ATOMIC_SMIN_RTN_32                         = 0x11,
+       TC_OP_ATOMIC_UMIN_RTN_32                         = 0x12,
+       TC_OP_ATOMIC_SMAX_RTN_32                         = 0x13,
+       TC_OP_ATOMIC_UMAX_RTN_32                         = 0x14,
+       TC_OP_ATOMIC_AND_RTN_32                          = 0x15,
+       TC_OP_ATOMIC_OR_RTN_32                           = 0x16,
+       TC_OP_ATOMIC_XOR_RTN_32                          = 0x17,
+       TC_OP_ATOMIC_INC_RTN_32                          = 0x18,
+       TC_OP_ATOMIC_DEC_RTN_32                          = 0x19,
+       TC_OP_WBINVL1_VOL                                = 0x1a,
+       TC_OP_WBINVL1_SD                                 = 0x1b,
+       TC_OP_RESERVED_NON_FLOAT_RTN_32_0                = 0x1c,
+       TC_OP_RESERVED_NON_FLOAT_RTN_32_1                = 0x1d,
+       TC_OP_RESERVED_NON_FLOAT_RTN_32_2                = 0x1e,
+       TC_OP_RESERVED_NON_FLOAT_RTN_32_3                = 0x1f,
+       TC_OP_WRITE                                      = 0x20,
+       TC_OP_ATOMIC_FCMPSWAP_RTN_64                     = 0x21,
+       TC_OP_ATOMIC_FMIN_RTN_64                         = 0x22,
+       TC_OP_ATOMIC_FMAX_RTN_64                         = 0x23,
+       TC_OP_RESERVED_FOP_RTN_64_0                      = 0x24,
+       TC_OP_RESERVED_FOP_RTN_64_1                      = 0x25,
+       TC_OP_RESERVED_FOP_RTN_64_2                      = 0x26,
+       TC_OP_ATOMIC_SWAP_RTN_64                         = 0x27,
+       TC_OP_ATOMIC_CMPSWAP_RTN_64                      = 0x28,
+       TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64        = 0x29,
+       TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64            = 0x2a,
+       TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64            = 0x2b,
+       TC_OP_WBINVL2_SD                                 = 0x2c,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0         = 0x2d,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1         = 0x2e,
+       TC_OP_ATOMIC_ADD_RTN_64                          = 0x2f,
+       TC_OP_ATOMIC_SUB_RTN_64                          = 0x30,
+       TC_OP_ATOMIC_SMIN_RTN_64                         = 0x31,
+       TC_OP_ATOMIC_UMIN_RTN_64                         = 0x32,
+       TC_OP_ATOMIC_SMAX_RTN_64                         = 0x33,
+       TC_OP_ATOMIC_UMAX_RTN_64                         = 0x34,
+       TC_OP_ATOMIC_AND_RTN_64                          = 0x35,
+       TC_OP_ATOMIC_OR_RTN_64                           = 0x36,
+       TC_OP_ATOMIC_XOR_RTN_64                          = 0x37,
+       TC_OP_ATOMIC_INC_RTN_64                          = 0x38,
+       TC_OP_ATOMIC_DEC_RTN_64                          = 0x39,
+       TC_OP_WBL2_NC                                    = 0x3a,
+       TC_OP_RESERVED_NON_FLOAT_RTN_64_0                = 0x3b,
+       TC_OP_RESERVED_NON_FLOAT_RTN_64_1                = 0x3c,
+       TC_OP_RESERVED_NON_FLOAT_RTN_64_2                = 0x3d,
+       TC_OP_RESERVED_NON_FLOAT_RTN_64_3                = 0x3e,
+       TC_OP_RESERVED_NON_FLOAT_RTN_64_4                = 0x3f,
+       TC_OP_WBINVL1                                    = 0x40,
+       TC_OP_ATOMIC_FCMPSWAP_32                         = 0x41,
+       TC_OP_ATOMIC_FMIN_32                             = 0x42,
+       TC_OP_ATOMIC_FMAX_32                             = 0x43,
+       TC_OP_RESERVED_FOP_32_0                          = 0x44,
+       TC_OP_RESERVED_FOP_32_1                          = 0x45,
+       TC_OP_RESERVED_FOP_32_2                          = 0x46,
+       TC_OP_ATOMIC_SWAP_32                             = 0x47,
+       TC_OP_ATOMIC_CMPSWAP_32                          = 0x48,
+       TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32            = 0x49,
+       TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32                = 0x4a,
+       TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32                = 0x4b,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0             = 0x4c,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1             = 0x4d,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2             = 0x4e,
+       TC_OP_ATOMIC_ADD_32                              = 0x4f,
+       TC_OP_ATOMIC_SUB_32                              = 0x50,
+       TC_OP_ATOMIC_SMIN_32                             = 0x51,
+       TC_OP_ATOMIC_UMIN_32                             = 0x52,
+       TC_OP_ATOMIC_SMAX_32                             = 0x53,
+       TC_OP_ATOMIC_UMAX_32                             = 0x54,
+       TC_OP_ATOMIC_AND_32                              = 0x55,
+       TC_OP_ATOMIC_OR_32                               = 0x56,
+       TC_OP_ATOMIC_XOR_32                              = 0x57,
+       TC_OP_ATOMIC_INC_32                              = 0x58,
+       TC_OP_ATOMIC_DEC_32                              = 0x59,
+       TC_OP_INVL2_NC                                   = 0x5a,
+       TC_OP_RESERVED_NON_FLOAT_32_0                    = 0x5b,
+       TC_OP_RESERVED_NON_FLOAT_32_1                    = 0x5c,
+       TC_OP_RESERVED_NON_FLOAT_32_2                    = 0x5d,
+       TC_OP_RESERVED_NON_FLOAT_32_3                    = 0x5e,
+       TC_OP_RESERVED_NON_FLOAT_32_4                    = 0x5f,
+       TC_OP_WBINVL2                                    = 0x60,
+       TC_OP_ATOMIC_FCMPSWAP_64                         = 0x61,
+       TC_OP_ATOMIC_FMIN_64                             = 0x62,
+       TC_OP_ATOMIC_FMAX_64                             = 0x63,
+       TC_OP_RESERVED_FOP_64_0                          = 0x64,
+       TC_OP_RESERVED_FOP_64_1                          = 0x65,
+       TC_OP_RESERVED_FOP_64_2                          = 0x66,
+       TC_OP_ATOMIC_SWAP_64                             = 0x67,
+       TC_OP_ATOMIC_CMPSWAP_64                          = 0x68,
+       TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64            = 0x69,
+       TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64                = 0x6a,
+       TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64                = 0x6b,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0             = 0x6c,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1             = 0x6d,
+       TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2             = 0x6e,
+       TC_OP_ATOMIC_ADD_64                              = 0x6f,
+       TC_OP_ATOMIC_SUB_64                              = 0x70,
+       TC_OP_ATOMIC_SMIN_64                             = 0x71,
+       TC_OP_ATOMIC_UMIN_64                             = 0x72,
+       TC_OP_ATOMIC_SMAX_64                             = 0x73,
+       TC_OP_ATOMIC_UMAX_64                             = 0x74,
+       TC_OP_ATOMIC_AND_64                              = 0x75,
+       TC_OP_ATOMIC_OR_64                               = 0x76,
+       TC_OP_ATOMIC_XOR_64                              = 0x77,
+       TC_OP_ATOMIC_INC_64                              = 0x78,
+       TC_OP_ATOMIC_DEC_64                              = 0x79,
+       TC_OP_WBINVL2_NC                                 = 0x7a,
+       TC_OP_RESERVED_NON_FLOAT_64_0                    = 0x7b,
+       TC_OP_RESERVED_NON_FLOAT_64_1                    = 0x7c,
+       TC_OP_RESERVED_NON_FLOAT_64_2                    = 0x7d,
+       TC_OP_RESERVED_NON_FLOAT_64_3                    = 0x7e,
+       TC_OP_RESERVED_NON_FLOAT_64_4                    = 0x7f,
+} TC_OP;
+typedef enum TC_CHUB_REQ_CREDITS_ENUM {
+       TC_CHUB_REQ_CREDITS                              = 0x10,
+} TC_CHUB_REQ_CREDITS_ENUM;
+typedef enum CHUB_TC_RET_CREDITS_ENUM {
+       CHUB_TC_RET_CREDITS                              = 0x20,
+} CHUB_TC_RET_CREDITS_ENUM;
+typedef enum TC_NACKS {
+       TC_NACK_NO_FAULT                                 = 0x0,
+       TC_NACK_PAGE_FAULT                               = 0x1,
+       TC_NACK_PROTECTION_FAULT                         = 0x2,
+       TC_NACK_DATA_ERROR                               = 0x3,
+} TC_NACKS;
+typedef enum TCC_PERF_SEL {
+       TCC_PERF_SEL_NONE                                = 0x0,
+       TCC_PERF_SEL_CYCLE                               = 0x1,
+       TCC_PERF_SEL_BUSY                                = 0x2,
+       TCC_PERF_SEL_REQ                                 = 0x3,
+       TCC_PERF_SEL_STREAMING_REQ                       = 0x4,
+       TCC_PERF_SEL_EXE_REQ                             = 0x5,
+       TCC_PERF_SEL_COMPRESSED_REQ                      = 0x6,
+       TCC_PERF_SEL_COMPRESSED_0_REQ                    = 0x7,
+       TCC_PERF_SEL_METADATA_REQ                        = 0x8,
+       TCC_PERF_SEL_NC_VIRTUAL_REQ                      = 0x9,
+       TCC_PERF_SEL_NC_PHYSICAL_REQ                     = 0xa,
+       TCC_PERF_SEL_UC_VIRTUAL_REQ                      = 0xb,
+       TCC_PERF_SEL_UC_PHYSICAL_REQ                     = 0xc,
+       TCC_PERF_SEL_CC_PHYSICAL_REQ                     = 0xd,
+       TCC_PERF_SEL_PROBE                               = 0xe,
+       TCC_PERF_SEL_READ                                = 0xf,
+       TCC_PERF_SEL_WRITE                               = 0x10,
+       TCC_PERF_SEL_ATOMIC                              = 0x11,
+       TCC_PERF_SEL_HIT                                 = 0x12,
+       TCC_PERF_SEL_MISS                                = 0x13,
+       TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT                = 0x14,
+       TCC_PERF_SEL_FULLY_WRITTEN_HIT                   = 0x15,
+       TCC_PERF_SEL_WRITEBACK                           = 0x16,
+       TCC_PERF_SEL_LATENCY_FIFO_FULL                   = 0x17,
+       TCC_PERF_SEL_SRC_FIFO_FULL                       = 0x18,
+       TCC_PERF_SEL_HOLE_FIFO_FULL                      = 0x19,
+       TCC_PERF_SEL_MC_WRREQ                            = 0x1a,
+       TCC_PERF_SEL_MC_WRREQ_UNCACHED                   = 0x1b,
+       TCC_PERF_SEL_MC_WRREQ_STALL                      = 0x1c,
+       TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL               = 0x1d,
+       TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL              = 0x1e,
+       TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL            = 0x1f,
+       TCC_PERF_SEL_MC_WRREQ_LEVEL                      = 0x20,
+       TCC_PERF_SEL_MC_ATOMIC                           = 0x21,
+       TCC_PERF_SEL_MC_ATOMIC_LEVEL                     = 0x22,
+       TCC_PERF_SEL_MC_RDREQ                            = 0x23,
+       TCC_PERF_SEL_MC_RDREQ_UNCACHED                   = 0x24,
+       TCC_PERF_SEL_MC_RDREQ_MDC                        = 0x25,
+       TCC_PERF_SEL_MC_RDREQ_COMPRESSED                 = 0x26,
+       TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL               = 0x27,
+       TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL              = 0x28,
+       TCC_PERF_SEL_MC_RDREQ_LEVEL                      = 0x29,
+       TCC_PERF_SEL_TAG_STALL                           = 0x2a,
+       TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL       = 0x2b,
+       TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x2c,
+       TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d,
+       TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e,
+       TCC_PERF_SEL_TAG_PROBE_STALL                     = 0x2f,
+       TCC_PERF_SEL_TAG_PROBE_FILTER_STALL              = 0x30,
+       TCC_PERF_SEL_READ_RETURN_TIMEOUT                 = 0x31,
+       TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT              = 0x32,
+       TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE             = 0x33,
+       TCC_PERF_SEL_BUBBLE                              = 0x34,
+       TCC_PERF_SEL_RETURN_ACK                          = 0x35,
+       TCC_PERF_SEL_RETURN_DATA                         = 0x36,
+       TCC_PERF_SEL_RETURN_HOLE                         = 0x37,
+       TCC_PERF_SEL_RETURN_ACK_HOLE                     = 0x38,
+       TCC_PERF_SEL_IB_REQ                              = 0x39,
+       TCC_PERF_SEL_IB_STALL                            = 0x3a,
+       TCC_PERF_SEL_IB_TAG_STALL                        = 0x3b,
+       TCC_PERF_SEL_IB_MDC_STALL                        = 0x3c,
+       TCC_PERF_SEL_TCA_LEVEL                           = 0x3d,
+       TCC_PERF_SEL_HOLE_LEVEL                          = 0x3e,
+       TCC_PERF_SEL_MC_RDRET_NACK                       = 0x3f,
+       TCC_PERF_SEL_MC_WRRET_NACK                       = 0x40,
+       TCC_PERF_SEL_NORMAL_WRITEBACK                    = 0x41,
+       TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK             = 0x42,
+       TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK             = 0x43,
+       TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK          = 0x44,
+       TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK          = 0x45,
+       TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK              = 0x46,
+       TCC_PERF_SEL_NORMAL_EVICT                        = 0x47,
+       TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT                 = 0x48,
+       TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT                = 0x49,
+       TCC_PERF_SEL_TC_OP_WBINVL2_EVICT                 = 0x4a,
+       TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT              = 0x4b,
+       TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT              = 0x4c,
+       TCC_PERF_SEL_ALL_TC_OP_INV_EVICT                 = 0x4d,
+       TCC_PERF_SEL_PROBE_EVICT                         = 0x4e,
+       TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE                 = 0x4f,
+       TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE                = 0x50,
+       TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE                 = 0x51,
+       TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE              = 0x52,
+       TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE              = 0x53,
+       TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE           = 0x54,
+       TCC_PERF_SEL_TC_OP_WBL2_NC_START                 = 0x55,
+       TCC_PERF_SEL_TC_OP_INVL2_NC_START                = 0x56,
+       TCC_PERF_SEL_TC_OP_WBINVL2_START                 = 0x57,
+       TCC_PERF_SEL_TC_OP_WBINVL2_NC_START              = 0x58,
+       TCC_PERF_SEL_TC_OP_WBINVL2_SD_START              = 0x59,
+       TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START           = 0x5a,
+       TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH                = 0x5b,
+       TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH               = 0x5c,
+       TCC_PERF_SEL_TC_OP_WBINVL2_FINISH                = 0x5d,
+       TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH             = 0x5e,
+       TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH             = 0x5f,
+       TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH          = 0x60,
+       TCC_PERF_SEL_MDC_REQ                             = 0x61,
+       TCC_PERF_SEL_MDC_LEVEL                           = 0x62,
+       TCC_PERF_SEL_MDC_TAG_HIT                         = 0x63,
+       TCC_PERF_SEL_MDC_SECTOR_HIT                      = 0x64,
+       TCC_PERF_SEL_MDC_SECTOR_MISS                     = 0x65,
+       TCC_PERF_SEL_MDC_TAG_STALL                       = 0x66,
+       TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67,
+       TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68,
+       TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69,
+       TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION     = 0x6a,
+       TCC_PERF_SEL_PROBE_FILTER_DISABLED               = 0x6b,
+       TCC_PERF_SEL_CLIENT0_REQ                         = 0x80,
+       TCC_PERF_SEL_CLIENT1_REQ                         = 0x81,
+       TCC_PERF_SEL_CLIENT2_REQ                         = 0x82,
+       TCC_PERF_SEL_CLIENT3_REQ                         = 0x83,
+       TCC_PERF_SEL_CLIENT4_REQ                         = 0x84,
+       TCC_PERF_SEL_CLIENT5_REQ                         = 0x85,
+       TCC_PERF_SEL_CLIENT6_REQ                         = 0x86,
+       TCC_PERF_SEL_CLIENT7_REQ                         = 0x87,
+       TCC_PERF_SEL_CLIENT8_REQ                         = 0x88,
+       TCC_PERF_SEL_CLIENT9_REQ                         = 0x89,
+       TCC_PERF_SEL_CLIENT10_REQ                        = 0x8a,
+       TCC_PERF_SEL_CLIENT11_REQ                        = 0x8b,
+       TCC_PERF_SEL_CLIENT12_REQ                        = 0x8c,
+       TCC_PERF_SEL_CLIENT13_REQ                        = 0x8d,
+       TCC_PERF_SEL_CLIENT14_REQ                        = 0x8e,
+       TCC_PERF_SEL_CLIENT15_REQ                        = 0x8f,
+       TCC_PERF_SEL_CLIENT16_REQ                        = 0x90,
+       TCC_PERF_SEL_CLIENT17_REQ                        = 0x91,
+       TCC_PERF_SEL_CLIENT18_REQ                        = 0x92,
+       TCC_PERF_SEL_CLIENT19_REQ                        = 0x93,
+       TCC_PERF_SEL_CLIENT20_REQ                        = 0x94,
+       TCC_PERF_SEL_CLIENT21_REQ                        = 0x95,
+       TCC_PERF_SEL_CLIENT22_REQ                        = 0x96,
+       TCC_PERF_SEL_CLIENT23_REQ                        = 0x97,
+       TCC_PERF_SEL_CLIENT24_REQ                        = 0x98,
+       TCC_PERF_SEL_CLIENT25_REQ                        = 0x99,
+       TCC_PERF_SEL_CLIENT26_REQ                        = 0x9a,
+       TCC_PERF_SEL_CLIENT27_REQ                        = 0x9b,
+       TCC_PERF_SEL_CLIENT28_REQ                        = 0x9c,
+       TCC_PERF_SEL_CLIENT29_REQ                        = 0x9d,
+       TCC_PERF_SEL_CLIENT30_REQ                        = 0x9e,
+       TCC_PERF_SEL_CLIENT31_REQ                        = 0x9f,
+       TCC_PERF_SEL_CLIENT32_REQ                        = 0xa0,
+       TCC_PERF_SEL_CLIENT33_REQ                        = 0xa1,
+       TCC_PERF_SEL_CLIENT34_REQ                        = 0xa2,
+       TCC_PERF_SEL_CLIENT35_REQ                        = 0xa3,
+       TCC_PERF_SEL_CLIENT36_REQ                        = 0xa4,
+       TCC_PERF_SEL_CLIENT37_REQ                        = 0xa5,
+       TCC_PERF_SEL_CLIENT38_REQ                        = 0xa6,
+       TCC_PERF_SEL_CLIENT39_REQ                        = 0xa7,
+       TCC_PERF_SEL_CLIENT40_REQ                        = 0xa8,
+       TCC_PERF_SEL_CLIENT41_REQ                        = 0xa9,
+       TCC_PERF_SEL_CLIENT42_REQ                        = 0xaa,
+       TCC_PERF_SEL_CLIENT43_REQ                        = 0xab,
+       TCC_PERF_SEL_CLIENT44_REQ                        = 0xac,
+       TCC_PERF_SEL_CLIENT45_REQ                        = 0xad,
+       TCC_PERF_SEL_CLIENT46_REQ                        = 0xae,
+       TCC_PERF_SEL_CLIENT47_REQ                        = 0xaf,
+       TCC_PERF_SEL_CLIENT48_REQ                        = 0xb0,
+       TCC_PERF_SEL_CLIENT49_REQ                        = 0xb1,
+       TCC_PERF_SEL_CLIENT50_REQ                        = 0xb2,
+       TCC_PERF_SEL_CLIENT51_REQ                        = 0xb3,
+       TCC_PERF_SEL_CLIENT52_REQ                        = 0xb4,
+       TCC_PERF_SEL_CLIENT53_REQ                        = 0xb5,
+       TCC_PERF_SEL_CLIENT54_REQ                        = 0xb6,
+       TCC_PERF_SEL_CLIENT55_REQ                        = 0xb7,
+       TCC_PERF_SEL_CLIENT56_REQ                        = 0xb8,
+       TCC_PERF_SEL_CLIENT57_REQ                        = 0xb9,
+       TCC_PERF_SEL_CLIENT58_REQ                        = 0xba,
+       TCC_PERF_SEL_CLIENT59_REQ                        = 0xbb,
+       TCC_PERF_SEL_CLIENT60_REQ                        = 0xbc,
+       TCC_PERF_SEL_CLIENT61_REQ                        = 0xbd,
+       TCC_PERF_SEL_CLIENT62_REQ                        = 0xbe,
+       TCC_PERF_SEL_CLIENT63_REQ                        = 0xbf,
+       TCC_PERF_SEL_CLIENT64_REQ                        = 0xc0,
+       TCC_PERF_SEL_CLIENT65_REQ                        = 0xc1,
+       TCC_PERF_SEL_CLIENT66_REQ                        = 0xc2,
+       TCC_PERF_SEL_CLIENT67_REQ                        = 0xc3,
+       TCC_PERF_SEL_CLIENT68_REQ                        = 0xc4,
+       TCC_PERF_SEL_CLIENT69_REQ                        = 0xc5,
+       TCC_PERF_SEL_CLIENT70_REQ                        = 0xc6,
+       TCC_PERF_SEL_CLIENT71_REQ                        = 0xc7,
+       TCC_PERF_SEL_CLIENT72_REQ                        = 0xc8,
+       TCC_PERF_SEL_CLIENT73_REQ                        = 0xc9,
+       TCC_PERF_SEL_CLIENT74_REQ                        = 0xca,
+       TCC_PERF_SEL_CLIENT75_REQ                        = 0xcb,
+       TCC_PERF_SEL_CLIENT76_REQ                        = 0xcc,
+       TCC_PERF_SEL_CLIENT77_REQ                        = 0xcd,
+       TCC_PERF_SEL_CLIENT78_REQ                        = 0xce,
+       TCC_PERF_SEL_CLIENT79_REQ                        = 0xcf,
+       TCC_PERF_SEL_CLIENT80_REQ                        = 0xd0,
+       TCC_PERF_SEL_CLIENT81_REQ                        = 0xd1,
+       TCC_PERF_SEL_CLIENT82_REQ                        = 0xd2,
+       TCC_PERF_SEL_CLIENT83_REQ                        = 0xd3,
+       TCC_PERF_SEL_CLIENT84_REQ                        = 0xd4,
+       TCC_PERF_SEL_CLIENT85_REQ                        = 0xd5,
+       TCC_PERF_SEL_CLIENT86_REQ                        = 0xd6,
+       TCC_PERF_SEL_CLIENT87_REQ                        = 0xd7,
+       TCC_PERF_SEL_CLIENT88_REQ                        = 0xd8,
+       TCC_PERF_SEL_CLIENT89_REQ                        = 0xd9,
+       TCC_PERF_SEL_CLIENT90_REQ                        = 0xda,
+       TCC_PERF_SEL_CLIENT91_REQ                        = 0xdb,
+       TCC_PERF_SEL_CLIENT92_REQ                        = 0xdc,
+       TCC_PERF_SEL_CLIENT93_REQ                        = 0xdd,
+       TCC_PERF_SEL_CLIENT94_REQ                        = 0xde,
+       TCC_PERF_SEL_CLIENT95_REQ                        = 0xdf,
+       TCC_PERF_SEL_CLIENT96_REQ                        = 0xe0,
+       TCC_PERF_SEL_CLIENT97_REQ                        = 0xe1,
+       TCC_PERF_SEL_CLIENT98_REQ                        = 0xe2,
+       TCC_PERF_SEL_CLIENT99_REQ                        = 0xe3,
+       TCC_PERF_SEL_CLIENT100_REQ                       = 0xe4,
+       TCC_PERF_SEL_CLIENT101_REQ                       = 0xe5,
+       TCC_PERF_SEL_CLIENT102_REQ                       = 0xe6,
+       TCC_PERF_SEL_CLIENT103_REQ                       = 0xe7,
+       TCC_PERF_SEL_CLIENT104_REQ                       = 0xe8,
+       TCC_PERF_SEL_CLIENT105_REQ                       = 0xe9,
+       TCC_PERF_SEL_CLIENT106_REQ                       = 0xea,
+       TCC_PERF_SEL_CLIENT107_REQ                       = 0xeb,
+       TCC_PERF_SEL_CLIENT108_REQ                       = 0xec,
+       TCC_PERF_SEL_CLIENT109_REQ                       = 0xed,
+       TCC_PERF_SEL_CLIENT110_REQ                       = 0xee,
+       TCC_PERF_SEL_CLIENT111_REQ                       = 0xef,
+       TCC_PERF_SEL_CLIENT112_REQ                       = 0xf0,
+       TCC_PERF_SEL_CLIENT113_REQ                       = 0xf1,
+       TCC_PERF_SEL_CLIENT114_REQ                       = 0xf2,
+       TCC_PERF_SEL_CLIENT115_REQ                       = 0xf3,
+       TCC_PERF_SEL_CLIENT116_REQ                       = 0xf4,
+       TCC_PERF_SEL_CLIENT117_REQ                       = 0xf5,
+       TCC_PERF_SEL_CLIENT118_REQ                       = 0xf6,
+       TCC_PERF_SEL_CLIENT119_REQ                       = 0xf7,
+       TCC_PERF_SEL_CLIENT120_REQ                       = 0xf8,
+       TCC_PERF_SEL_CLIENT121_REQ                       = 0xf9,
+       TCC_PERF_SEL_CLIENT122_REQ                       = 0xfa,
+       TCC_PERF_SEL_CLIENT123_REQ                       = 0xfb,
+       TCC_PERF_SEL_CLIENT124_REQ                       = 0xfc,
+       TCC_PERF_SEL_CLIENT125_REQ                       = 0xfd,
+       TCC_PERF_SEL_CLIENT126_REQ                       = 0xfe,
+       TCC_PERF_SEL_CLIENT127_REQ                       = 0xff,
+} TCC_PERF_SEL;
+typedef enum TCA_PERF_SEL {
+       TCA_PERF_SEL_NONE                                = 0x0,
+       TCA_PERF_SEL_CYCLE                               = 0x1,
+       TCA_PERF_SEL_BUSY                                = 0x2,
+       TCA_PERF_SEL_FORCED_HOLE_TCC0                    = 0x3,
+       TCA_PERF_SEL_FORCED_HOLE_TCC1                    = 0x4,
+       TCA_PERF_SEL_FORCED_HOLE_TCC2                    = 0x5,
+       TCA_PERF_SEL_FORCED_HOLE_TCC3                    = 0x6,
+       TCA_PERF_SEL_FORCED_HOLE_TCC4                    = 0x7,
+       TCA_PERF_SEL_FORCED_HOLE_TCC5                    = 0x8,
+       TCA_PERF_SEL_FORCED_HOLE_TCC6                    = 0x9,
+       TCA_PERF_SEL_FORCED_HOLE_TCC7                    = 0xa,
+       TCA_PERF_SEL_REQ_TCC0                            = 0xb,
+       TCA_PERF_SEL_REQ_TCC1                            = 0xc,
+       TCA_PERF_SEL_REQ_TCC2                            = 0xd,
+       TCA_PERF_SEL_REQ_TCC3                            = 0xe,
+       TCA_PERF_SEL_REQ_TCC4                            = 0xf,
+       TCA_PERF_SEL_REQ_TCC5                            = 0x10,
+       TCA_PERF_SEL_REQ_TCC6                            = 0x11,
+       TCA_PERF_SEL_REQ_TCC7                            = 0x12,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0            = 0x13,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1            = 0x14,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2            = 0x15,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3            = 0x16,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4            = 0x17,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5            = 0x18,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6            = 0x19,
+       TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7            = 0x1a,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC0                 = 0x1b,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC1                 = 0x1c,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC2                 = 0x1d,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC3                 = 0x1e,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC4                 = 0x1f,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC5                 = 0x20,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC6                 = 0x21,
+       TCA_PERF_SEL_CROSSBAR_STALL_TCC7                 = 0x22,
+} TCA_PERF_SEL;
+typedef enum TA_TC_ADDR_MODES {
+       TA_TC_ADDR_MODE_DEFAULT                          = 0x0,
+       TA_TC_ADDR_MODE_COMP0                            = 0x1,
+       TA_TC_ADDR_MODE_COMP1                            = 0x2,
+       TA_TC_ADDR_MODE_COMP2                            = 0x3,
+       TA_TC_ADDR_MODE_COMP3                            = 0x4,
+       TA_TC_ADDR_MODE_UNALIGNED                        = 0x5,
+       TA_TC_ADDR_MODE_BORDER_COLOR                     = 0x6,
+} TA_TC_ADDR_MODES;
+typedef enum TA_PERFCOUNT_SEL {
+       TA_PERF_SEL_NULL                                 = 0x0,
+       TA_PERF_SEL_sh_fifo_busy                         = 0x1,
+       TA_PERF_SEL_sh_fifo_cmd_busy                     = 0x2,
+       TA_PERF_SEL_sh_fifo_addr_busy                    = 0x3,
+       TA_PERF_SEL_sh_fifo_data_busy                    = 0x4,
+       TA_PERF_SEL_sh_fifo_data_sfifo_busy              = 0x5,
+       TA_PERF_SEL_sh_fifo_data_tfifo_busy              = 0x6,
+       TA_PERF_SEL_gradient_busy                        = 0x7,
+       TA_PERF_SEL_gradient_fifo_busy                   = 0x8,
+       TA_PERF_SEL_lod_busy                             = 0x9,
+       TA_PERF_SEL_lod_fifo_busy                        = 0xa,
+       TA_PERF_SEL_addresser_busy                       = 0xb,
+       TA_PERF_SEL_addresser_fifo_busy                  = 0xc,
+       TA_PERF_SEL_aligner_busy                         = 0xd,
+       TA_PERF_SEL_write_path_busy                      = 0xe,
+       TA_PERF_SEL_ta_busy                              = 0xf,
+       TA_PERF_SEL_sq_ta_cmd_cycles                     = 0x10,
+       TA_PERF_SEL_sp_ta_addr_cycles                    = 0x11,
+       TA_PERF_SEL_sp_ta_data_cycles                    = 0x12,
+       TA_PERF_SEL_ta_fa_data_state_cycles              = 0x13,
+       TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles   = 0x14,
+       TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles   = 0x15,
+       TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
+       TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
+       TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
+       TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
+       TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
+       TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
+       TA_PERF_SEL_RESERVED_28                          = 0x1c,
+       TA_PERF_SEL_RESERVED_29                          = 0x1d,
+       TA_PERF_SEL_sh_fifo_addr_cycles                  = 0x1e,
+       TA_PERF_SEL_sh_fifo_data_cycles                  = 0x1f,
+       TA_PERF_SEL_total_wavefronts                     = 0x20,
+       TA_PERF_SEL_gradient_cycles                      = 0x21,
+       TA_PERF_SEL_walker_cycles                        = 0x22,
+       TA_PERF_SEL_aligner_cycles                       = 0x23,
+       TA_PERF_SEL_image_wavefronts                     = 0x24,
+       TA_PERF_SEL_image_read_wavefronts                = 0x25,
+       TA_PERF_SEL_image_write_wavefronts               = 0x26,
+       TA_PERF_SEL_image_atomic_wavefronts              = 0x27,
+       TA_PERF_SEL_image_total_cycles                   = 0x28,
+       TA_PERF_SEL_RESERVED_41                          = 0x29,
+       TA_PERF_SEL_RESERVED_42                          = 0x2a,
+       TA_PERF_SEL_RESERVED_43                          = 0x2b,
+       TA_PERF_SEL_buffer_wavefronts                    = 0x2c,
+       TA_PERF_SEL_buffer_read_wavefronts               = 0x2d,
+       TA_PERF_SEL_buffer_write_wavefronts              = 0x2e,
+       TA_PERF_SEL_buffer_atomic_wavefronts             = 0x2f,
+       TA_PERF_SEL_buffer_coalescable_wavefronts        = 0x30,
+       TA_PERF_SEL_buffer_total_cycles                  = 0x31,
+       TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
+       TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
+       TA_PERF_SEL_buffer_coalesced_read_cycles         = 0x34,
+       TA_PERF_SEL_buffer_coalesced_write_cycles        = 0x35,
+       TA_PERF_SEL_addr_stalled_by_tc_cycles            = 0x36,
+       TA_PERF_SEL_addr_stalled_by_td_cycles            = 0x37,
+       TA_PERF_SEL_data_stalled_by_tc_cycles            = 0x38,
+       TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
+       TA_PERF_SEL_addresser_stalled_cycles             = 0x3a,
+       TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
+       TA_PERF_SEL_aniso_stalled_cycles                 = 0x3c,
+       TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles   = 0x3d,
+       TA_PERF_SEL_deriv_stalled_cycles                 = 0x3e,
+       TA_PERF_SEL_aniso_gt1_cycle_quads                = 0x3f,
+       TA_PERF_SEL_color_1_cycle_pixels                 = 0x40,
+       TA_PERF_SEL_color_2_cycle_pixels                 = 0x41,
+       TA_PERF_SEL_color_3_cycle_pixels                 = 0x42,
+       TA_PERF_SEL_color_4_cycle_pixels                 = 0x43,
+       TA_PERF_SEL_mip_1_cycle_pixels                   = 0x44,
+       TA_PERF_SEL_mip_2_cycle_pixels                   = 0x45,
+       TA_PERF_SEL_vol_1_cycle_pixels                   = 0x46,
+       TA_PERF_SEL_vol_2_cycle_pixels                   = 0x47,
+       TA_PERF_SEL_bilin_point_1_cycle_pixels           = 0x48,
+       TA_PERF_SEL_mipmap_lod_0_samples                 = 0x49,
+       TA_PERF_SEL_mipmap_lod_1_samples                 = 0x4a,
+       TA_PERF_SEL_mipmap_lod_2_samples                 = 0x4b,
+       TA_PERF_SEL_mipmap_lod_3_samples                 = 0x4c,
+       TA_PERF_SEL_mipmap_lod_4_samples                 = 0x4d,
+       TA_PERF_SEL_mipmap_lod_5_samples                 = 0x4e,
+       TA_PERF_SEL_mipmap_lod_6_samples                 = 0x4f,
+       TA_PERF_SEL_mipmap_lod_7_samples                 = 0x50,
+       TA_PERF_SEL_mipmap_lod_8_samples                 = 0x51,
+       TA_PERF_SEL_mipmap_lod_9_samples                 = 0x52,
+       TA_PERF_SEL_mipmap_lod_10_samples                = 0x53,
+       TA_PERF_SEL_mipmap_lod_11_samples                = 0x54,
+       TA_PERF_SEL_mipmap_lod_12_samples                = 0x55,
+       TA_PERF_SEL_mipmap_lod_13_samples                = 0x56,
+       TA_PERF_SEL_mipmap_lod_14_samples                = 0x57,
+       TA_PERF_SEL_mipmap_invalid_samples               = 0x58,
+       TA_PERF_SEL_aniso_1_cycle_quads                  = 0x59,
+       TA_PERF_SEL_aniso_2_cycle_quads                  = 0x5a,
+       TA_PERF_SEL_aniso_4_cycle_quads                  = 0x5b,
+       TA_PERF_SEL_aniso_6_cycle_quads                  = 0x5c,
+       TA_PERF_SEL_aniso_8_cycle_quads                  = 0x5d,
+       TA_PERF_SEL_aniso_10_cycle_quads                 = 0x5e,
+       TA_PERF_SEL_aniso_12_cycle_quads                 = 0x5f,
+       TA_PERF_SEL_aniso_14_cycle_quads                 = 0x60,
+       TA_PERF_SEL_aniso_16_cycle_quads                 = 0x61,
+       TA_PERF_SEL_write_path_input_cycles              = 0x62,
+       TA_PERF_SEL_write_path_output_cycles             = 0x63,
+       TA_PERF_SEL_flat_wavefronts                      = 0x64,
+       TA_PERF_SEL_flat_read_wavefronts                 = 0x65,
+       TA_PERF_SEL_flat_write_wavefronts                = 0x66,
+       TA_PERF_SEL_flat_atomic_wavefronts               = 0x67,
+       TA_PERF_SEL_flat_coalesceable_wavefronts         = 0x68,
+       TA_PERF_SEL_reg_sclk_vld                         = 0x69,
+       TA_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6a,
+       TA_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x6b,
+       TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en       = 0x6c,
+       TA_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x6d,
+       TA_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x6e,
+       TA_PERF_SEL_xnack_on_phase0                      = 0x6f,
+       TA_PERF_SEL_xnack_on_phase1                      = 0x70,
+       TA_PERF_SEL_xnack_on_phase2                      = 0x71,
+       TA_PERF_SEL_xnack_on_phase3                      = 0x72,
+       TA_PERF_SEL_first_xnack_on_phase0                = 0x73,
+       TA_PERF_SEL_first_xnack_on_phase1                = 0x74,
+       TA_PERF_SEL_first_xnack_on_phase2                = 0x75,
+       TA_PERF_SEL_first_xnack_on_phase3                = 0x76,
+} TA_PERFCOUNT_SEL;
+typedef enum TD_PERFCOUNT_SEL {
+       TD_PERF_SEL_none                                 = 0x0,
+       TD_PERF_SEL_td_busy                              = 0x1,
+       TD_PERF_SEL_input_busy                           = 0x2,
+       TD_PERF_SEL_output_busy                          = 0x3,
+       TD_PERF_SEL_lerp_busy                            = 0x4,
+       TD_PERF_SEL_reg_sclk_vld                         = 0x5,
+       TD_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6,
+       TD_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x7,
+       TD_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x8,
+       TD_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x9,
+       TD_PERF_SEL_tc_td_fifo_full                      = 0xa,
+       TD_PERF_SEL_constant_state_full                  = 0xb,
+       TD_PERF_SEL_sample_state_full                    = 0xc,
+       TD_PERF_SEL_output_fifo_full                     = 0xd,
+       TD_PERF_SEL_RESERVED_14                          = 0xe,
+       TD_PERF_SEL_tc_stall                             = 0xf,
+       TD_PERF_SEL_pc_stall                             = 0x10,
+       TD_PERF_SEL_gds_stall                            = 0x11,
+       TD_PERF_SEL_RESERVED_18                          = 0x12,
+       TD_PERF_SEL_RESERVED_19                          = 0x13,
+       TD_PERF_SEL_gather4_wavefront                    = 0x14,
+       TD_PERF_SEL_sample_c_wavefront                   = 0x15,
+       TD_PERF_SEL_load_wavefront                       = 0x16,
+       TD_PERF_SEL_atomic_wavefront                     = 0x17,
+       TD_PERF_SEL_store_wavefront                      = 0x18,
+       TD_PERF_SEL_ldfptr_wavefront                     = 0x19,
+       TD_PERF_SEL_RESERVED_26                          = 0x1a,
+       TD_PERF_SEL_RESERVED_27                          = 0x1b,
+       TD_PERF_SEL_d16_en_wavefront                     = 0x1c,
+       TD_PERF_SEL_bicubic_filter_wavefront             = 0x1d,
+       TD_PERF_SEL_bypass_filter_wavefront              = 0x1e,
+       TD_PERF_SEL_min_max_filter_wavefront             = 0x1f,
+       TD_PERF_SEL_coalescable_wavefront                = 0x20,
+       TD_PERF_SEL_coalesced_phase                      = 0x21,
+       TD_PERF_SEL_four_phase_wavefront                 = 0x22,
+       TD_PERF_SEL_eight_phase_wavefront                = 0x23,
+       TD_PERF_SEL_sixteen_phase_wavefront              = 0x24,
+       TD_PERF_SEL_four_phase_forward_wavefront         = 0x25,
+       TD_PERF_SEL_write_ack_wavefront                  = 0x26,
+       TD_PERF_SEL_RESERVED_39                          = 0x27,
+       TD_PERF_SEL_user_defined_border                  = 0x28,
+       TD_PERF_SEL_white_border                         = 0x29,
+       TD_PERF_SEL_opaque_black_border                  = 0x2a,
+       TD_PERF_SEL_RESERVED_43                          = 0x2b,
+       TD_PERF_SEL_RESERVED_44                          = 0x2c,
+       TD_PERF_SEL_nack                                 = 0x2d,
+       TD_PERF_SEL_td_sp_traffic                        = 0x2e,
+       TD_PERF_SEL_consume_gds_traffic                  = 0x2f,
+       TD_PERF_SEL_addresscmd_poison                    = 0x30,
+       TD_PERF_SEL_data_poison                          = 0x31,
+       TD_PERF_SEL_start_cycle_0                        = 0x32,
+       TD_PERF_SEL_start_cycle_1                        = 0x33,
+       TD_PERF_SEL_start_cycle_2                        = 0x34,
+       TD_PERF_SEL_start_cycle_3                        = 0x35,
+       TD_PERF_SEL_null_cycle_output                    = 0x36,
+} TD_PERFCOUNT_SEL;
+typedef enum TCP_PERFCOUNT_SELECT {
+       TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES           = 0x0,
+       TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES           = 0x1,
+       TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES            = 0x2,
+       TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES            = 0x3,
+       TCP_PERF_SEL_TD_TCP_STALL_CYCLES                 = 0x4,
+       TCP_PERF_SEL_TCR_TCP_STALL_CYCLES                = 0x5,
+       TCP_PERF_SEL_LOD_STALL_CYCLES                    = 0x6,
+       TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES       = 0x7,
+       TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES      = 0x8,
+       TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES     = 0x9,
+       TCP_PERF_SEL_ALLOC_STALL_CYCLES                  = 0xa,
+       TCP_PERF_SEL_LFIFO_STALL_CYCLES                  = 0xb,
+       TCP_PERF_SEL_RFIFO_STALL_CYCLES                  = 0xc,
+       TCP_PERF_SEL_TCR_RDRET_STALL                     = 0xd,
+       TCP_PERF_SEL_WRITE_CONFLICT_STALL                = 0xe,
+       TCP_PERF_SEL_HOLE_READ_STALL                     = 0xf,
+       TCP_PERF_SEL_READCONFLICT_STALL_CYCLES           = 0x10,
+       TCP_PERF_SEL_PENDING_STALL_CYCLES                = 0x11,
+       TCP_PERF_SEL_READFIFO_STALL_CYCLES               = 0x12,
+       TCP_PERF_SEL_TCP_LATENCY                         = 0x13,
+       TCP_PERF_SEL_TCC_READ_REQ_LATENCY                = 0x14,
+       TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY               = 0x15,
+       TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY          = 0x16,
+       TCP_PERF_SEL_TCC_READ_REQ                        = 0x17,
+       TCP_PERF_SEL_TCC_WRITE_REQ                       = 0x18,
+       TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ             = 0x19,
+       TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ          = 0x1a,
+       TCP_PERF_SEL_TOTAL_LOCAL_READ                    = 0x1b,
+       TCP_PERF_SEL_TOTAL_GLOBAL_READ                   = 0x1c,
+       TCP_PERF_SEL_TOTAL_LOCAL_WRITE                   = 0x1d,
+       TCP_PERF_SEL_TOTAL_GLOBAL_WRITE                  = 0x1e,
+       TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET               = 0x1f,
+       TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET            = 0x20,
+       TCP_PERF_SEL_TOTAL_WBINVL1                       = 0x21,
+       TCP_PERF_SEL_IMG_READ_FMT_1                      = 0x22,
+       TCP_PERF_SEL_IMG_READ_FMT_8                      = 0x23,
+       TCP_PERF_SEL_IMG_READ_FMT_16                     = 0x24,
+       TCP_PERF_SEL_IMG_READ_FMT_32                     = 0x25,
+       TCP_PERF_SEL_IMG_READ_FMT_32_AS_8                = 0x26,
+       TCP_PERF_SEL_IMG_READ_FMT_32_AS_16               = 0x27,
+       TCP_PERF_SEL_IMG_READ_FMT_32_AS_128              = 0x28,
+       TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE             = 0x29,
+       TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE             = 0x2a,
+       TCP_PERF_SEL_IMG_READ_FMT_96                     = 0x2b,
+       TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE            = 0x2c,
+       TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE            = 0x2d,
+       TCP_PERF_SEL_IMG_READ_FMT_BC1                    = 0x2e,
+       TCP_PERF_SEL_IMG_READ_FMT_BC2                    = 0x2f,
+       TCP_PERF_SEL_IMG_READ_FMT_BC3                    = 0x30,
+       TCP_PERF_SEL_IMG_READ_FMT_BC4                    = 0x31,
+       TCP_PERF_SEL_IMG_READ_FMT_BC5                    = 0x32,
+       TCP_PERF_SEL_IMG_READ_FMT_BC6                    = 0x33,
+       TCP_PERF_SEL_IMG_READ_FMT_BC7                    = 0x34,
+       TCP_PERF_SEL_IMG_READ_FMT_I8                     = 0x35,
+       TCP_PERF_SEL_IMG_READ_FMT_I16                    = 0x36,
+       TCP_PERF_SEL_IMG_READ_FMT_I32                    = 0x37,
+       TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8               = 0x38,
+       TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16              = 0x39,
+       TCP_PERF_SEL_IMG_READ_FMT_D8                     = 0x3a,
+       TCP_PERF_SEL_IMG_READ_FMT_D16                    = 0x3b,
+       TCP_PERF_SEL_IMG_READ_FMT_D32                    = 0x3c,
+       TCP_PERF_SEL_IMG_WRITE_FMT_8                     = 0x3d,
+       TCP_PERF_SEL_IMG_WRITE_FMT_16                    = 0x3e,
+       TCP_PERF_SEL_IMG_WRITE_FMT_32                    = 0x3f,
+       TCP_PERF_SEL_IMG_WRITE_FMT_64                    = 0x40,
+       TCP_PERF_SEL_IMG_WRITE_FMT_128                   = 0x41,
+       TCP_PERF_SEL_IMG_WRITE_FMT_D8                    = 0x42,
+       TCP_PERF_SEL_IMG_WRITE_FMT_D16                   = 0x43,
+       TCP_PERF_SEL_IMG_WRITE_FMT_D32                   = 0x44,
+       TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32          = 0x45,
+       TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32       = 0x46,
+       TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64          = 0x47,
+       TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64       = 0x48,
+       TCP_PERF_SEL_BUF_READ_FMT_8                      = 0x49,
+       TCP_PERF_SEL_BUF_READ_FMT_16                     = 0x4a,
+       TCP_PERF_SEL_BUF_READ_FMT_32                     = 0x4b,
+       TCP_PERF_SEL_BUF_WRITE_FMT_8                     = 0x4c,
+       TCP_PERF_SEL_BUF_WRITE_FMT_16                    = 0x4d,
+       TCP_PERF_SEL_BUF_WRITE_FMT_32                    = 0x4e,
+       TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32          = 0x4f,
+       TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32       = 0x50,
+       TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64          = 0x51,
+       TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64       = 0x52,
+       TCP_PERF_SEL_ARR_LINEAR_GENERAL                  = 0x53,
+       TCP_PERF_SEL_ARR_LINEAR_ALIGNED                  = 0x54,
+       TCP_PERF_SEL_ARR_1D_THIN1                        = 0x55,
+       TCP_PERF_SEL_ARR_1D_THICK                        = 0x56,
+       TCP_PERF_SEL_ARR_2D_THIN1                        = 0x57,
+       TCP_PERF_SEL_ARR_2D_THICK                        = 0x58,
+       TCP_PERF_SEL_ARR_2D_XTHICK                       = 0x59,
+       TCP_PERF_SEL_ARR_3D_THIN1                        = 0x5a,
+       TCP_PERF_SEL_ARR_3D_THICK                        = 0x5b,
+       TCP_PERF_SEL_ARR_3D_XTHICK                       = 0x5c,
+       TCP_PERF_SEL_DIM_1D                              = 0x5d,
+       TCP_PERF_SEL_DIM_2D                              = 0x5e,
+       TCP_PERF_SEL_DIM_3D                              = 0x5f,
+       TCP_PERF_SEL_DIM_1D_ARRAY                        = 0x60,
+       TCP_PERF_SEL_DIM_2D_ARRAY                        = 0x61,
+       TCP_PERF_SEL_DIM_2D_MSAA                         = 0x62,
+       TCP_PERF_SEL_DIM_2D_ARRAY_MSAA                   = 0x63,
+       TCP_PERF_SEL_DIM_CUBE_ARRAY                      = 0x64,
+       TCP_PERF_SEL_CP_TCP_INVALIDATE                   = 0x65,
+       TCP_PERF_SEL_TA_TCP_STATE_READ                   = 0x66,
+       TCP_PERF_SEL_TAGRAM0_REQ                         = 0x67,
+       TCP_PERF_SEL_TAGRAM1_REQ                         = 0x68,
+       TCP_PERF_SEL_TAGRAM2_REQ                         = 0x69,
+       TCP_PERF_SEL_TAGRAM3_REQ                         = 0x6a,
+       TCP_PERF_SEL_GATE_EN1                            = 0x6b,
+       TCP_PERF_SEL_GATE_EN2                            = 0x6c,
+       TCP_PERF_SEL_CORE_REG_SCLK_VLD                   = 0x6d,
+       TCP_PERF_SEL_TCC_REQ                             = 0x6e,
+       TCP_PERF_SEL_TCC_NON_READ_REQ                    = 0x6f,
+       TCP_PERF_SEL_TCC_BYPASS_READ_REQ                 = 0x70,
+       TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ             = 0x71,
+       TCP_PERF_SEL_TCC_VOLATILE_READ_REQ               = 0x72,
+       TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ        = 0x73,
+       TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ    = 0x74,
+       TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ                = 0x75,
+       TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ            = 0x76,
+       TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ       = 0x77,
+       TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ              = 0x78,
+       TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ   = 0x79,
+       TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ               = 0x7a,
+       TCP_PERF_SEL_TCC_ATOMIC_REQ                      = 0x7b,
+       TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ             = 0x7c,
+       TCP_PERF_SEL_TCC_DATA_BUS_BUSY                   = 0x7d,
+       TCP_PERF_SEL_TOTAL_ACCESSES                      = 0x7e,
+       TCP_PERF_SEL_TOTAL_READ                          = 0x7f,
+       TCP_PERF_SEL_TOTAL_HIT_LRU_READ                  = 0x80,
+       TCP_PERF_SEL_TOTAL_HIT_EVICT_READ                = 0x81,
+       TCP_PERF_SEL_TOTAL_MISS_LRU_READ                 = 0x82,
+       TCP_PERF_SEL_TOTAL_MISS_EVICT_READ               = 0x83,
+       TCP_PERF_SEL_TOTAL_NON_READ                      = 0x84,
+       TCP_PERF_SEL_TOTAL_WRITE                         = 0x85,
+       TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE                = 0x86,
+       TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE              = 0x87,
+       TCP_PERF_SEL_TOTAL_WBINVL1_VOL                   = 0x88,
+       TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES         = 0x89,
+       TCP_PERF_SEL_DISPLAY_MICROTILING                 = 0x8a,
+       TCP_PERF_SEL_THIN_MICROTILING                    = 0x8b,
+       TCP_PERF_SEL_DEPTH_MICROTILING                   = 0x8c,
+       TCP_PERF_SEL_ARR_PRT_THIN1                       = 0x8d,
+       TCP_PERF_SEL_ARR_PRT_2D_THIN1                    = 0x8e,
+       TCP_PERF_SEL_ARR_PRT_3D_THIN1                    = 0x8f,
+       TCP_PERF_SEL_ARR_PRT_THICK                       = 0x90,
+       TCP_PERF_SEL_ARR_PRT_2D_THICK                    = 0x91,
+       TCP_PERF_SEL_ARR_PRT_3D_THICK                    = 0x92,
+       TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL               = 0x93,
+       TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL               = 0x94,
+       TCP_PERF_SEL_UNALIGNED                           = 0x95,
+       TCP_PERF_SEL_ROTATED_MICROTILING                 = 0x96,
+       TCP_PERF_SEL_THICK_MICROTILING                   = 0x97,
+       TCP_PERF_SEL_ATC                                 = 0x98,
+       TCP_PERF_SEL_POWER_STALL                         = 0x99,
+       TCP_PERF_SEL_RESERVED_154                        = 0x9a,
+       TCP_PERF_SEL_TCC_LRU_REQ                         = 0x9b,
+       TCP_PERF_SEL_TCC_STREAM_REQ                      = 0x9c,
+       TCP_PERF_SEL_TCC_NC_READ_REQ                     = 0x9d,
+       TCP_PERF_SEL_TCC_NC_WRITE_REQ                    = 0x9e,
+       TCP_PERF_SEL_TCC_NC_ATOMIC_REQ                   = 0x9f,
+       TCP_PERF_SEL_TCC_UC_READ_REQ                     = 0xa0,
+       TCP_PERF_SEL_TCC_UC_WRITE_REQ                    = 0xa1,
+       TCP_PERF_SEL_TCC_UC_ATOMIC_REQ                   = 0xa2,
+       TCP_PERF_SEL_TCC_CC_READ_REQ                     = 0xa3,
+       TCP_PERF_SEL_TCC_CC_WRITE_REQ                    = 0xa4,
+       TCP_PERF_SEL_TCC_CC_ATOMIC_REQ                   = 0xa5,
+       TCP_PERF_SEL_TCC_DCC_REQ                         = 0xa6,
+       TCP_PERF_SEL_TCC_PHYSICAL_REQ                    = 0xa7,
+       TCP_PERF_SEL_UNORDERED_MTYPE_STALL               = 0xa8,
+       TCP_PERF_SEL_VOLATILE                            = 0xa9,
+       TCP_PERF_SEL_TC_TA_XNACK_STALL                   = 0xaa,
+       TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL           = 0xab,
+       TCP_PERF_SEL_SHOOTDOWN                           = 0xac,
+       TCP_PERF_SEL_GATCL1_TRANSLATION_MISS             = 0xad,
+       TCP_PERF_SEL_GATCL1_PERMISSION_MISS              = 0xae,
+       TCP_PERF_SEL_GATCL1_REQUEST                      = 0xaf,
+       TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX           = 0xb0,
+       TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT           = 0xb1,
+       TCP_PERF_SEL_GATCL1_LFIFO_FULL                   = 0xb2,
+       TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES          = 0xb3,
+       TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4,
+       TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT               = 0xb5,
+       TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL          = 0xb6,
+} TCP_PERFCOUNT_SELECT;
+typedef enum TCP_CACHE_POLICIES {
+       TCP_CACHE_POLICY_MISS_LRU                        = 0x0,
+       TCP_CACHE_POLICY_MISS_EVICT                      = 0x1,
+       TCP_CACHE_POLICY_HIT_LRU                         = 0x2,
+       TCP_CACHE_POLICY_HIT_EVICT                       = 0x3,
+} TCP_CACHE_POLICIES;
+typedef enum TCP_CACHE_STORE_POLICIES {
+       TCP_CACHE_STORE_POLICY_WT_LRU                    = 0x0,
+       TCP_CACHE_STORE_POLICY_WT_EVICT                  = 0x1,
+} TCP_CACHE_STORE_POLICIES;
+typedef enum TCP_WATCH_MODES {
+       TCP_WATCH_MODE_READ                              = 0x0,
+       TCP_WATCH_MODE_NONREAD                           = 0x1,
+       TCP_WATCH_MODE_ATOMIC                            = 0x2,
+       TCP_WATCH_MODE_ALL                               = 0x3,
+} TCP_WATCH_MODES;
+typedef enum TCP_DSM_DATA_SEL {
+       TCP_DSM_DISABLE                                  = 0x0,
+       TCP_DSM_SEL0                                     = 0x1,
+       TCP_DSM_SEL1                                     = 0x2,
+       TCP_DSM_SEL_BOTH                                 = 0x3,
+} TCP_DSM_DATA_SEL;
+typedef enum TCP_DSM_SINGLE_WRITE {
+       TCP_DSM_SINGLE_WRITE_EN                          = 0x1,
+} TCP_DSM_SINGLE_WRITE;
+typedef enum VGT_OUT_PRIM_TYPE {
+       VGT_OUT_POINT                                    = 0x0,
+       VGT_OUT_LINE                                     = 0x1,
+       VGT_OUT_TRI                                      = 0x2,
+       VGT_OUT_RECT_V0                                  = 0x3,
+       VGT_OUT_RECT_V1                                  = 0x4,
+       VGT_OUT_RECT_V2                                  = 0x5,
+       VGT_OUT_RECT_V3                                  = 0x6,
+       VGT_OUT_RESERVED                                 = 0x7,
+       VGT_TE_QUAD                                      = 0x8,
+       VGT_TE_PRIM_INDEX_LINE                           = 0x9,
+       VGT_TE_PRIM_INDEX_TRI                            = 0xa,
+       VGT_TE_PRIM_INDEX_QUAD                           = 0xb,
+       VGT_OUT_LINE_ADJ                                 = 0xc,
+       VGT_OUT_TRI_ADJ                                  = 0xd,
+       VGT_OUT_PATCH                                    = 0xe,
+} VGT_OUT_PRIM_TYPE;
+typedef enum VGT_DI_PRIM_TYPE {
+       DI_PT_NONE                                       = 0x0,
+       DI_PT_POINTLIST                                  = 0x1,
+       DI_PT_LINELIST                                   = 0x2,
+       DI_PT_LINESTRIP                                  = 0x3,
+       DI_PT_TRILIST                                    = 0x4,
+       DI_PT_TRIFAN                                     = 0x5,
+       DI_PT_TRISTRIP                                   = 0x6,
+       DI_PT_UNUSED_0                                   = 0x7,
+       DI_PT_UNUSED_1                                   = 0x8,
+       DI_PT_PATCH                                      = 0x9,
+       DI_PT_LINELIST_ADJ                               = 0xa,
+       DI_PT_LINESTRIP_ADJ                              = 0xb,
+       DI_PT_TRILIST_ADJ                                = 0xc,
+       DI_PT_TRISTRIP_ADJ                               = 0xd,
+       DI_PT_UNUSED_3                                   = 0xe,
+       DI_PT_UNUSED_4                                   = 0xf,
+       DI_PT_TRI_WITH_WFLAGS                            = 0x10,
+       DI_PT_RECTLIST                                   = 0x11,
+       DI_PT_LINELOOP                                   = 0x12,
+       DI_PT_QUADLIST                                   = 0x13,
+       DI_PT_QUADSTRIP                                  = 0x14,
+       DI_PT_POLYGON                                    = 0x15,
+       DI_PT_2D_COPY_RECT_LIST_V0                       = 0x16,
+       DI_PT_2D_COPY_RECT_LIST_V1                       = 0x17,
+       DI_PT_2D_COPY_RECT_LIST_V2                       = 0x18,
+       DI_PT_2D_COPY_RECT_LIST_V3                       = 0x19,
+       DI_PT_2D_FILL_RECT_LIST                          = 0x1a,
+       DI_PT_2D_LINE_STRIP                              = 0x1b,
+       DI_PT_2D_TRI_STRIP                               = 0x1c,
+} VGT_DI_PRIM_TYPE;
+typedef enum VGT_DI_SOURCE_SELECT {
+       DI_SRC_SEL_DMA                                   = 0x0,
+       DI_SRC_SEL_IMMEDIATE                             = 0x1,
+       DI_SRC_SEL_AUTO_INDEX                            = 0x2,
+       DI_SRC_SEL_RESERVED                              = 0x3,
+} VGT_DI_SOURCE_SELECT;
+typedef enum VGT_DI_MAJOR_MODE_SELECT {
+       DI_MAJOR_MODE_0                                  = 0x0,
+       DI_MAJOR_MODE_1                                  = 0x1,
+} VGT_DI_MAJOR_MODE_SELECT;
+typedef enum VGT_DI_INDEX_SIZE {
+       DI_INDEX_SIZE_16_BIT                             = 0x0,
+       DI_INDEX_SIZE_32_BIT                             = 0x1,
+       DI_INDEX_SIZE_8_BIT                              = 0x2,
+} VGT_DI_INDEX_SIZE;
+typedef enum VGT_EVENT_TYPE {
+       Reserved_0x00                                    = 0x0,
+       SAMPLE_STREAMOUTSTATS1                           = 0x1,
+       SAMPLE_STREAMOUTSTATS2                           = 0x2,
+       SAMPLE_STREAMOUTSTATS3                           = 0x3,
+       CACHE_FLUSH_TS                                   = 0x4,
+       CONTEXT_DONE                                     = 0x5,
+       CACHE_FLUSH                                      = 0x6,
+       CS_PARTIAL_FLUSH                                 = 0x7,
+       VGT_STREAMOUT_SYNC                               = 0x8,
+       Reserved_0x09                                    = 0x9,
+       VGT_STREAMOUT_RESET                              = 0xa,
+       END_OF_PIPE_INCR_DE                              = 0xb,
+       END_OF_PIPE_IB_END                               = 0xc,
+       RST_PIX_CNT                                      = 0xd,
+       Reserved_0x0E                                    = 0xe,
+       VS_PARTIAL_FLUSH                                 = 0xf,
+       PS_PARTIAL_FLUSH                                 = 0x10,
+       FLUSH_HS_OUTPUT                                  = 0x11,
+       FLUSH_LS_OUTPUT                                  = 0x12,
+       Reserved_0x13                                    = 0x13,
+       CACHE_FLUSH_AND_INV_TS_EVENT                     = 0x14,
+       ZPASS_DONE                                       = 0x15,
+       CACHE_FLUSH_AND_INV_EVENT                        = 0x16,
+       PERFCOUNTER_START                                = 0x17,
+       PERFCOUNTER_STOP                                 = 0x18,
+       PIPELINESTAT_START                               = 0x19,
+       PIPELINESTAT_STOP                                = 0x1a,
+       PERFCOUNTER_SAMPLE                               = 0x1b,
+       FLUSH_ES_OUTPUT                                  = 0x1c,
+       FLUSH_GS_OUTPUT                                  = 0x1d,
+       SAMPLE_PIPELINESTAT                              = 0x1e,
+       SO_VGTSTREAMOUT_FLUSH                            = 0x1f,
+       SAMPLE_STREAMOUTSTATS                            = 0x20,
+       RESET_VTX_CNT                                    = 0x21,
+       BLOCK_CONTEXT_DONE                               = 0x22,
+       CS_CONTEXT_DONE                                  = 0x23,
+       VGT_FLUSH                                        = 0x24,
+       TGID_ROLLOVER                                    = 0x25,
+       SQ_NON_EVENT                                     = 0x26,
+       SC_SEND_DB_VPZ                                   = 0x27,
+       BOTTOM_OF_PIPE_TS                                = 0x28,
+       FLUSH_SX_TS                                      = 0x29,
+       DB_CACHE_FLUSH_AND_INV                           = 0x2a,
+       FLUSH_AND_INV_DB_DATA_TS                         = 0x2b,
+       FLUSH_AND_INV_DB_META                            = 0x2c,
+       FLUSH_AND_INV_CB_DATA_TS                         = 0x2d,
+       FLUSH_AND_INV_CB_META                            = 0x2e,
+       CS_DONE                                          = 0x2f,
+       PS_DONE                                          = 0x30,
+       FLUSH_AND_INV_CB_PIXEL_DATA                      = 0x31,
+       SX_CB_RAT_ACK_REQUEST                            = 0x32,
+       THREAD_TRACE_START                               = 0x33,
+       THREAD_TRACE_STOP                                = 0x34,
+       THREAD_TRACE_MARKER                              = 0x35,
+       THREAD_TRACE_FLUSH                               = 0x36,
+       THREAD_TRACE_FINISH                              = 0x37,
+       PIXEL_PIPE_STAT_CONTROL                          = 0x38,
+       PIXEL_PIPE_STAT_DUMP                             = 0x39,
+       PIXEL_PIPE_STAT_RESET                            = 0x3a,
+       CONTEXT_SUSPEND                                  = 0x3b,
+       OFFCHIP_HS_DEALLOC                               = 0x3c,
+} VGT_EVENT_TYPE;
+typedef enum VGT_DMA_SWAP_MODE {
+       VGT_DMA_SWAP_NONE                                = 0x0,
+       VGT_DMA_SWAP_16_BIT                              = 0x1,
+       VGT_DMA_SWAP_32_BIT                              = 0x2,
+       VGT_DMA_SWAP_WORD                                = 0x3,
+} VGT_DMA_SWAP_MODE;
+typedef enum VGT_INDEX_TYPE_MODE {
+       VGT_INDEX_16                                     = 0x0,
+       VGT_INDEX_32                                     = 0x1,
+       VGT_INDEX_8                                      = 0x2,
+} VGT_INDEX_TYPE_MODE;
+typedef enum VGT_DMA_BUF_TYPE {
+       VGT_DMA_BUF_MEM                                  = 0x0,
+       VGT_DMA_BUF_RING                                 = 0x1,
+       VGT_DMA_BUF_SETUP                                = 0x2,
+       VGT_DMA_PTR_UPDATE                               = 0x3,
+} VGT_DMA_BUF_TYPE;
+typedef enum VGT_OUTPATH_SELECT {
+       VGT_OUTPATH_VTX_REUSE                            = 0x0,
+       VGT_OUTPATH_TESS_EN                              = 0x1,
+       VGT_OUTPATH_PASSTHRU                             = 0x2,
+       VGT_OUTPATH_GS_BLOCK                             = 0x3,
+       VGT_OUTPATH_HS_BLOCK                             = 0x4,
+} VGT_OUTPATH_SELECT;
+typedef enum VGT_GRP_PRIM_TYPE {
+       VGT_GRP_3D_POINT                                 = 0x0,
+       VGT_GRP_3D_LINE                                  = 0x1,
+       VGT_GRP_3D_TRI                                   = 0x2,
+       VGT_GRP_3D_RECT                                  = 0x3,
+       VGT_GRP_3D_QUAD                                  = 0x4,
+       VGT_GRP_2D_COPY_RECT_V0                          = 0x5,
+       VGT_GRP_2D_COPY_RECT_V1                          = 0x6,
+       VGT_GRP_2D_COPY_RECT_V2                          = 0x7,
+       VGT_GRP_2D_COPY_RECT_V3                          = 0x8,
+       VGT_GRP_2D_FILL_RECT                             = 0x9,
+       VGT_GRP_2D_LINE                                  = 0xa,
+       VGT_GRP_2D_TRI                                   = 0xb,
+       VGT_GRP_PRIM_INDEX_LINE                          = 0xc,
+       VGT_GRP_PRIM_INDEX_TRI                           = 0xd,
+       VGT_GRP_PRIM_INDEX_QUAD                          = 0xe,
+       VGT_GRP_3D_LINE_ADJ                              = 0xf,
+       VGT_GRP_3D_TRI_ADJ                               = 0x10,
+       VGT_GRP_3D_PATCH                                 = 0x11,
+} VGT_GRP_PRIM_TYPE;
+typedef enum VGT_GRP_PRIM_ORDER {
+       VGT_GRP_LIST                                     = 0x0,
+       VGT_GRP_STRIP                                    = 0x1,
+       VGT_GRP_FAN                                      = 0x2,
+       VGT_GRP_LOOP                                     = 0x3,
+       VGT_GRP_POLYGON                                  = 0x4,
+} VGT_GRP_PRIM_ORDER;
+typedef enum VGT_GROUP_CONV_SEL {
+       VGT_GRP_INDEX_16                                 = 0x0,
+       VGT_GRP_INDEX_32                                 = 0x1,
+       VGT_GRP_UINT_16                                  = 0x2,
+       VGT_GRP_UINT_32                                  = 0x3,
+       VGT_GRP_SINT_16                                  = 0x4,
+       VGT_GRP_SINT_32                                  = 0x5,
+       VGT_GRP_FLOAT_32                                 = 0x6,
+       VGT_GRP_AUTO_PRIM                                = 0x7,
+       VGT_GRP_FIX_1_23_TO_FLOAT                        = 0x8,
+} VGT_GROUP_CONV_SEL;
+typedef enum VGT_GS_MODE_TYPE {
+       GS_OFF                                           = 0x0,
+       GS_SCENARIO_A                                    = 0x1,
+       GS_SCENARIO_B                                    = 0x2,
+       GS_SCENARIO_G                                    = 0x3,
+       GS_SCENARIO_C                                    = 0x4,
+       SPRITE_EN                                        = 0x5,
+} VGT_GS_MODE_TYPE;
+typedef enum VGT_GS_CUT_MODE {
+       GS_CUT_1024                                      = 0x0,
+       GS_CUT_512                                       = 0x1,
+       GS_CUT_256                                       = 0x2,
+       GS_CUT_128                                       = 0x3,
+} VGT_GS_CUT_MODE;
+typedef enum VGT_GS_OUTPRIM_TYPE {
+       POINTLIST                                        = 0x0,
+       LINESTRIP                                        = 0x1,
+       TRISTRIP                                         = 0x2,
+} VGT_GS_OUTPRIM_TYPE;
+typedef enum VGT_CACHE_INVALID_MODE {
+       VC_ONLY                                          = 0x0,
+       TC_ONLY                                          = 0x1,
+       VC_AND_TC                                        = 0x2,
+} VGT_CACHE_INVALID_MODE;
+typedef enum VGT_TESS_TYPE {
+       TESS_ISOLINE                                     = 0x0,
+       TESS_TRIANGLE                                    = 0x1,
+       TESS_QUAD                                        = 0x2,
+} VGT_TESS_TYPE;
+typedef enum VGT_TESS_PARTITION {
+       PART_INTEGER                                     = 0x0,
+       PART_POW2                                        = 0x1,
+       PART_FRAC_ODD                                    = 0x2,
+       PART_FRAC_EVEN                                   = 0x3,
+} VGT_TESS_PARTITION;
+typedef enum VGT_TESS_TOPOLOGY {
+       OUTPUT_POINT                                     = 0x0,
+       OUTPUT_LINE                                      = 0x1,
+       OUTPUT_TRIANGLE_CW                               = 0x2,
+       OUTPUT_TRIANGLE_CCW                              = 0x3,
+} VGT_TESS_TOPOLOGY;
+typedef enum VGT_RDREQ_POLICY {
+       VGT_POLICY_LRU                                   = 0x0,
+       VGT_POLICY_STREAM                                = 0x1,
+} VGT_RDREQ_POLICY;
+typedef enum VGT_DIST_MODE {
+       NO_DIST                                          = 0x0,
+       PATCHES                                          = 0x1,
+       DONUTS                                           = 0x2,
+} VGT_DIST_MODE;
+typedef enum VGT_STAGES_LS_EN {
+       LS_STAGE_OFF                                     = 0x0,
+       LS_STAGE_ON                                      = 0x1,
+       CS_STAGE_ON                                      = 0x2,
+       RESERVED_LS                                      = 0x3,
+} VGT_STAGES_LS_EN;
+typedef enum VGT_STAGES_HS_EN {
+       HS_STAGE_OFF                                     = 0x0,
+       HS_STAGE_ON                                      = 0x1,
+} VGT_STAGES_HS_EN;
+typedef enum VGT_STAGES_ES_EN {
+       ES_STAGE_OFF                                     = 0x0,
+       ES_STAGE_DS                                      = 0x1,
+       ES_STAGE_REAL                                    = 0x2,
+       RESERVED_ES                                      = 0x3,
+} VGT_STAGES_ES_EN;
+typedef enum VGT_STAGES_GS_EN {
+       GS_STAGE_OFF                                     = 0x0,
+       GS_STAGE_ON                                      = 0x1,
+} VGT_STAGES_GS_EN;
+typedef enum VGT_STAGES_VS_EN {
+       VS_STAGE_REAL                                    = 0x0,
+       VS_STAGE_DS                                      = 0x1,
+       VS_STAGE_COPY_SHADER                             = 0x2,
+       RESERVED_VS                                      = 0x3,
+} VGT_STAGES_VS_EN;
+typedef enum VGT_PERFCOUNT_SELECT {
+       vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE    = 0x0,
+       vgt_perf_VGT_SPI_ESVERT_VALID                    = 0x1,
+       vgt_perf_VGT_SPI_ESVERT_EOV                      = 0x2,
+       vgt_perf_VGT_SPI_ESVERT_STALLED                  = 0x3,
+       vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY             = 0x4,
+       vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE             = 0x5,
+       vgt_perf_VGT_SPI_ESVERT_STATIC                   = 0x6,
+       vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT               = 0x7,
+       vgt_perf_VGT_SPI_ESTHREAD_SEND                   = 0x8,
+       vgt_perf_VGT_SPI_GSPRIM_VALID                    = 0x9,
+       vgt_perf_VGT_SPI_GSPRIM_EOV                      = 0xa,
+       vgt_perf_VGT_SPI_GSPRIM_CONT                     = 0xb,
+       vgt_perf_VGT_SPI_GSPRIM_STALLED                  = 0xc,
+       vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY             = 0xd,
+       vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE             = 0xe,
+       vgt_perf_VGT_SPI_GSPRIM_STATIC                   = 0xf,
+       vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE    = 0x10,
+       vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT               = 0x11,
+       vgt_perf_VGT_SPI_GSTHREAD_SEND                   = 0x12,
+       vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE    = 0x13,
+       vgt_perf_VGT_SPI_VSVERT_SEND                     = 0x14,
+       vgt_perf_VGT_SPI_VSVERT_EOV                      = 0x15,
+       vgt_perf_VGT_SPI_VSVERT_STALLED                  = 0x16,
+       vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY             = 0x17,
+       vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE             = 0x18,
+       vgt_perf_VGT_SPI_VSVERT_STATIC                   = 0x19,
+       vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT               = 0x1a,
+       vgt_perf_VGT_SPI_VSTHREAD_SEND                   = 0x1b,
+       vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE              = 0x1c,
+       vgt_perf_VGT_PA_CLIPV_SEND                       = 0x1d,
+       vgt_perf_VGT_PA_CLIPV_FIRSTVERT                  = 0x1e,
+       vgt_perf_VGT_PA_CLIPV_STALLED                    = 0x1f,
+       vgt_perf_VGT_PA_CLIPV_STARVED_BUSY               = 0x20,
+       vgt_perf_VGT_PA_CLIPV_STARVED_IDLE               = 0x21,
+       vgt_perf_VGT_PA_CLIPV_STATIC                     = 0x22,
+       vgt_perf_VGT_PA_CLIPP_SEND                       = 0x23,
+       vgt_perf_VGT_PA_CLIPP_EOP                        = 0x24,
+       vgt_perf_VGT_PA_CLIPP_IS_EVENT                   = 0x25,
+       vgt_perf_VGT_PA_CLIPP_NULL_PRIM                  = 0x26,
+       vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT               = 0x27,
+       vgt_perf_VGT_PA_CLIPP_STALLED                    = 0x28,
+       vgt_perf_VGT_PA_CLIPP_STARVED_BUSY               = 0x29,
+       vgt_perf_VGT_PA_CLIPP_STARVED_IDLE               = 0x2a,
+       vgt_perf_VGT_PA_CLIPP_STATIC                     = 0x2b,
+       vgt_perf_VGT_PA_CLIPS_SEND                       = 0x2c,
+       vgt_perf_VGT_PA_CLIPS_STALLED                    = 0x2d,
+       vgt_perf_VGT_PA_CLIPS_STARVED_BUSY               = 0x2e,
+       vgt_perf_VGT_PA_CLIPS_STARVED_IDLE               = 0x2f,
+       vgt_perf_VGT_PA_CLIPS_STATIC                     = 0x30,
+       vgt_perf_vsvert_ds_send                          = 0x31,
+       vgt_perf_vsvert_api_send                         = 0x32,
+       vgt_perf_hs_tif_stall                            = 0x33,
+       vgt_perf_hs_input_stall                          = 0x34,
+       vgt_perf_hs_interface_stall                      = 0x35,
+       vgt_perf_hs_tfm_stall                            = 0x36,
+       vgt_perf_te11_starved                            = 0x37,
+       vgt_perf_gs_event_stall                          = 0x38,
+       vgt_perf_vgt_pa_clipp_send_not_event             = 0x39,
+       vgt_perf_vgt_pa_clipp_valid_prim                 = 0x3a,
+       vgt_perf_reused_es_indices                       = 0x3b,
+       vgt_perf_vs_cache_hits                           = 0x3c,
+       vgt_perf_gs_cache_hits                           = 0x3d,
+       vgt_perf_ds_cache_hits                           = 0x3e,
+       vgt_perf_total_cache_hits                        = 0x3f,
+       vgt_perf_vgt_busy                                = 0x40,
+       vgt_perf_vgt_gs_busy                             = 0x41,
+       vgt_perf_esvert_stalled_es_tbl                   = 0x42,
+       vgt_perf_esvert_stalled_gs_tbl                   = 0x43,
+       vgt_perf_esvert_stalled_gs_event                 = 0x44,
+       vgt_perf_esvert_stalled_gsprim                   = 0x45,
+       vgt_perf_gsprim_stalled_es_tbl                   = 0x46,
+       vgt_perf_gsprim_stalled_gs_tbl                   = 0x47,
+       vgt_perf_gsprim_stalled_gs_event                 = 0x48,
+       vgt_perf_gsprim_stalled_esvert                   = 0x49,
+       vgt_perf_esthread_stalled_es_rb_full             = 0x4a,
+       vgt_perf_esthread_stalled_spi_bp                 = 0x4b,
+       vgt_perf_counters_avail_stalled                  = 0x4c,
+       vgt_perf_gs_rb_space_avail_stalled               = 0x4d,
+       vgt_perf_gs_issue_rtr_stalled                    = 0x4e,
+       vgt_perf_gsthread_stalled                        = 0x4f,
+       vgt_perf_strmout_stalled                         = 0x50,
+       vgt_perf_wait_for_es_done_stalled                = 0x51,
+       vgt_perf_cm_stalled_by_gog                       = 0x52,
+       vgt_perf_cm_reading_stalled                      = 0x53,
+       vgt_perf_cm_stalled_by_gsfetch_done              = 0x54,
+       vgt_perf_gog_vs_tbl_stalled                      = 0x55,
+       vgt_perf_gog_out_indx_stalled                    = 0x56,
+       vgt_perf_gog_out_prim_stalled                    = 0x57,
+       vgt_perf_waveid_stalled                          = 0x58,
+       vgt_perf_gog_busy                                = 0x59,
+       vgt_perf_reused_vs_indices                       = 0x5a,
+       vgt_perf_sclk_reg_vld_event                      = 0x5b,
+       vgt_perf_vs_conflicting_indices                  = 0x5c,
+       vgt_perf_sclk_core_vld_event                     = 0x5d,
+       vgt_perf_hswave_stalled                          = 0x5e,
+       vgt_perf_sclk_gs_vld_event                       = 0x5f,
+       vgt_perf_VGT_SPI_LSVERT_VALID                    = 0x60,
+       vgt_perf_VGT_SPI_LSVERT_EOV                      = 0x61,
+       vgt_perf_VGT_SPI_LSVERT_STALLED                  = 0x62,
+       vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY             = 0x63,
+       vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE             = 0x64,
+       vgt_perf_VGT_SPI_LSVERT_STATIC                   = 0x65,
+       vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE      = 0x66,
+       vgt_perf_VGT_SPI_LSWAVE_IS_EVENT                 = 0x67,
+       vgt_perf_VGT_SPI_LSWAVE_SEND                     = 0x68,
+       vgt_perf_VGT_SPI_HSVERT_VALID                    = 0x69,
+       vgt_perf_VGT_SPI_HSVERT_EOV                      = 0x6a,
+       vgt_perf_VGT_SPI_HSVERT_STALLED                  = 0x6b,
+       vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY             = 0x6c,
+       vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE             = 0x6d,
+       vgt_perf_VGT_SPI_HSVERT_STATIC                   = 0x6e,
+       vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE      = 0x6f,
+       vgt_perf_VGT_SPI_HSWAVE_IS_EVENT                 = 0x70,
+       vgt_perf_VGT_SPI_HSWAVE_SEND                     = 0x71,
+       vgt_perf_ds_prims                                = 0x72,
+       vgt_perf_ls_thread_groups                        = 0x73,
+       vgt_perf_hs_thread_groups                        = 0x74,
+       vgt_perf_es_thread_groups                        = 0x75,
+       vgt_perf_vs_thread_groups                        = 0x76,
+       vgt_perf_ls_done_latency                         = 0x77,
+       vgt_perf_hs_done_latency                         = 0x78,
+       vgt_perf_es_done_latency                         = 0x79,
+       vgt_perf_gs_done_latency                         = 0x7a,
+       vgt_perf_vgt_hs_busy                             = 0x7b,
+       vgt_perf_vgt_te11_busy                           = 0x7c,
+       vgt_perf_ls_flush                                = 0x7d,
+       vgt_perf_hs_flush                                = 0x7e,
+       vgt_perf_es_flush                                = 0x7f,
+       vgt_perf_vgt_pa_clipp_eopg                       = 0x80,
+       vgt_perf_ls_done                                 = 0x81,
+       vgt_perf_hs_done                                 = 0x82,
+       vgt_perf_es_done                                 = 0x83,
+       vgt_perf_gs_done                                 = 0x84,
+       vgt_perf_vsfetch_done                            = 0x85,
+       vgt_perf_gs_done_received                        = 0x86,
+       vgt_perf_es_ring_high_water_mark                 = 0x87,
+       vgt_perf_gs_ring_high_water_mark                 = 0x88,
+       vgt_perf_vs_table_high_water_mark                = 0x89,
+       vgt_perf_hs_tgs_active_high_water_mark           = 0x8a,
+       vgt_perf_pa_clipp_dealloc                        = 0x8b,
+       vgt_perf_cut_mem_flush_stalled                   = 0x8c,
+       vgt_perf_vsvert_work_received                    = 0x8d,
+       vgt_perf_vgt_pa_clipp_starved_after_work         = 0x8e,
+       vgt_perf_te11_con_starved_after_work             = 0x8f,
+       vgt_perf_hs_waiting_on_ls_done_stall             = 0x90,
+       vgt_spi_vsvert_valid                             = 0x91,
+} VGT_PERFCOUNT_SELECT;
+typedef enum IA_PERFCOUNT_SELECT {
+       ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE            = 0x0,
+       ia_perf_dma_data_fifo_full                       = 0x1,
+       ia_perf_RESERVED1                                = 0x2,
+       ia_perf_RESERVED2                                = 0x3,
+       ia_perf_RESERVED3                                = 0x4,
+       ia_perf_RESERVED4                                = 0x5,
+       ia_perf_RESERVED5                                = 0x6,
+       ia_perf_MC_LAT_BIN_0                             = 0x7,
+       ia_perf_MC_LAT_BIN_1                             = 0x8,
+       ia_perf_MC_LAT_BIN_2                             = 0x9,
+       ia_perf_MC_LAT_BIN_3                             = 0xa,
+       ia_perf_MC_LAT_BIN_4                             = 0xb,
+       ia_perf_MC_LAT_BIN_5                             = 0xc,
+       ia_perf_MC_LAT_BIN_6                             = 0xd,
+       ia_perf_MC_LAT_BIN_7                             = 0xe,
+       ia_perf_ia_busy                                  = 0xf,
+       ia_perf_ia_sclk_reg_vld_event                    = 0x10,
+       ia_perf_RESERVED6                                = 0x11,
+       ia_perf_ia_sclk_core_vld_event                   = 0x12,
+       ia_perf_RESERVED7                                = 0x13,
+       ia_perf_ia_dma_return                            = 0x14,
+       ia_perf_ia_stalled                               = 0x15,
+       ia_perf_shift_starved_pipe0_event                = 0x16,
+       ia_perf_shift_starved_pipe1_event                = 0x17,
+} IA_PERFCOUNT_SELECT;
+typedef enum WD_PERFCOUNT_SELECT {
+       wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE           = 0x0,
+       wd_perf_RBIU_DR_FIFO_STARVED                     = 0x1,
+       wd_perf_RBIU_DR_FIFO_STALLED                     = 0x2,
+       wd_perf_RBIU_DI_FIFO_STARVED                     = 0x3,
+       wd_perf_RBIU_DI_FIFO_STALLED                     = 0x4,
+       wd_perf_wd_busy                                  = 0x5,
+       wd_perf_wd_sclk_reg_vld_event                    = 0x6,
+       wd_perf_wd_sclk_input_vld_event                  = 0x7,
+       wd_perf_wd_sclk_core_vld_event                   = 0x8,
+       wd_perf_wd_stalled                               = 0x9,
+       wd_perf_inside_tf_bin_0                          = 0xa,
+       wd_perf_inside_tf_bin_1                          = 0xb,
+       wd_perf_inside_tf_bin_2                          = 0xc,
+       wd_perf_inside_tf_bin_3                          = 0xd,
+       wd_perf_inside_tf_bin_4                          = 0xe,
+       wd_perf_inside_tf_bin_5                          = 0xf,
+       wd_perf_inside_tf_bin_6                          = 0x10,
+       wd_perf_inside_tf_bin_7                          = 0x11,
+       wd_perf_inside_tf_bin_8                          = 0x12,
+       wd_perf_tfreq_lat_bin_0                          = 0x13,
+       wd_perf_tfreq_lat_bin_1                          = 0x14,
+       wd_perf_tfreq_lat_bin_2                          = 0x15,
+       wd_perf_tfreq_lat_bin_3                          = 0x16,
+       wd_perf_tfreq_lat_bin_4                          = 0x17,
+       wd_perf_tfreq_lat_bin_5                          = 0x18,
+       wd_perf_tfreq_lat_bin_6                          = 0x19,
+       wd_perf_tfreq_lat_bin_7                          = 0x1a,
+       wd_starved_on_hs_done                            = 0x1b,
+       wd_perf_se0_hs_done_latency                      = 0x1c,
+       wd_perf_se1_hs_done_latency                      = 0x1d,
+       wd_perf_se2_hs_done_latency                      = 0x1e,
+       wd_perf_se3_hs_done_latency                      = 0x1f,
+       wd_perf_hs_done_se0                              = 0x20,
+       wd_perf_hs_done_se1                              = 0x21,
+       wd_perf_hs_done_se2                              = 0x22,
+       wd_perf_hs_done_se3                              = 0x23,
+       wd_perf_null_patches                             = 0x24,
+} WD_PERFCOUNT_SELECT;
+typedef enum WD_IA_DRAW_TYPE {
+       WD_IA_DRAW_TYPE_DI_MM0                           = 0x0,
+       WD_IA_DRAW_TYPE_DI_MM1                           = 0x1,
+       WD_IA_DRAW_TYPE_EVENT_INIT                       = 0x2,
+       WD_IA_DRAW_TYPE_EVENT_ADDR                       = 0x3,
+       WD_IA_DRAW_TYPE_MIN_INDX                         = 0x4,
+       WD_IA_DRAW_TYPE_MAX_INDX                         = 0x5,
+       WD_IA_DRAW_TYPE_INDX_OFF                         = 0x6,
+       WD_IA_DRAW_TYPE_IMM_DATA                         = 0x7,
+} WD_IA_DRAW_TYPE;
+typedef enum WD_IA_DRAW_SOURCE {
+       WD_IA_DRAW_SOURCE_DMA                            = 0x0,
+       WD_IA_DRAW_SOURCE_IMMD                           = 0x1,
+       WD_IA_DRAW_SOURCE_AUTO                           = 0x2,
+       WD_IA_DRAW_SOURCE_OPAQ                           = 0x3,
+} WD_IA_DRAW_SOURCE;
+#define GSTHREADID_SIZE                           0x2
+typedef enum SurfaceEndian {
+       ENDIAN_NONE                                      = 0x0,
+       ENDIAN_8IN16                                     = 0x1,
+       ENDIAN_8IN32                                     = 0x2,
+       ENDIAN_8IN64                                     = 0x3,
+} SurfaceEndian;
+typedef enum ArrayMode {
+       ARRAY_LINEAR_GENERAL                             = 0x0,
+       ARRAY_LINEAR_ALIGNED                             = 0x1,
+       ARRAY_1D_TILED_THIN1                             = 0x2,
+       ARRAY_1D_TILED_THICK                             = 0x3,
+       ARRAY_2D_TILED_THIN1                             = 0x4,
+       ARRAY_PRT_TILED_THIN1                            = 0x5,
+       ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
+       ARRAY_2D_TILED_THICK                             = 0x7,
+       ARRAY_2D_TILED_XTHICK                            = 0x8,
+       ARRAY_PRT_TILED_THICK                            = 0x9,
+       ARRAY_PRT_2D_TILED_THICK                         = 0xa,
+       ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
+       ARRAY_3D_TILED_THIN1                             = 0xc,
+       ARRAY_3D_TILED_THICK                             = 0xd,
+       ARRAY_3D_TILED_XTHICK                            = 0xe,
+       ARRAY_PRT_3D_TILED_THICK                         = 0xf,
+} ArrayMode;
+typedef enum PipeTiling {
+       CONFIG_1_PIPE                                    = 0x0,
+       CONFIG_2_PIPE                                    = 0x1,
+       CONFIG_4_PIPE                                    = 0x2,
+       CONFIG_8_PIPE                                    = 0x3,
+} PipeTiling;
+typedef enum BankTiling {
+       CONFIG_4_BANK                                    = 0x0,
+       CONFIG_8_BANK                                    = 0x1,
+} BankTiling;
+typedef enum GroupInterleave {
+       CONFIG_256B_GROUP                                = 0x0,
+       CONFIG_512B_GROUP                                = 0x1,
+} GroupInterleave;
+typedef enum RowTiling {
+       CONFIG_1KB_ROW                                   = 0x0,
+       CONFIG_2KB_ROW                                   = 0x1,
+       CONFIG_4KB_ROW                                   = 0x2,
+       CONFIG_8KB_ROW                                   = 0x3,
+       CONFIG_1KB_ROW_OPT                               = 0x4,
+       CONFIG_2KB_ROW_OPT                               = 0x5,
+       CONFIG_4KB_ROW_OPT                               = 0x6,
+       CONFIG_8KB_ROW_OPT                               = 0x7,
+} RowTiling;
+typedef enum BankSwapBytes {
+       CONFIG_128B_SWAPS                                = 0x0,
+       CONFIG_256B_SWAPS                                = 0x1,
+       CONFIG_512B_SWAPS                                = 0x2,
+       CONFIG_1KB_SWAPS                                 = 0x3,
+} BankSwapBytes;
+typedef enum SampleSplitBytes {
+       CONFIG_1KB_SPLIT                                 = 0x0,
+       CONFIG_2KB_SPLIT                                 = 0x1,
+       CONFIG_4KB_SPLIT                                 = 0x2,
+       CONFIG_8KB_SPLIT                                 = 0x3,
+} SampleSplitBytes;
+typedef enum NumPipes {
+       ADDR_CONFIG_1_PIPE                               = 0x0,
+       ADDR_CONFIG_2_PIPE                               = 0x1,
+       ADDR_CONFIG_4_PIPE                               = 0x2,
+       ADDR_CONFIG_8_PIPE                               = 0x3,
+} NumPipes;
+typedef enum PipeInterleaveSize {
+       ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
+       ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
+} PipeInterleaveSize;
+typedef enum BankInterleaveSize {
+       ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
+       ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
+       ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
+       ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
+} BankInterleaveSize;
+typedef enum NumShaderEngines {
+       ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
+       ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
+} NumShaderEngines;
+typedef enum ShaderEngineTileSize {
+       ADDR_CONFIG_SE_TILE_16                           = 0x0,
+       ADDR_CONFIG_SE_TILE_32                           = 0x1,
+} ShaderEngineTileSize;
+typedef enum NumGPUs {
+       ADDR_CONFIG_1_GPU                                = 0x0,
+       ADDR_CONFIG_2_GPU                                = 0x1,
+       ADDR_CONFIG_4_GPU                                = 0x2,
+} NumGPUs;
+typedef enum MultiGPUTileSize {
+       ADDR_CONFIG_GPU_TILE_16                          = 0x0,
+       ADDR_CONFIG_GPU_TILE_32                          = 0x1,
+       ADDR_CONFIG_GPU_TILE_64                          = 0x2,
+       ADDR_CONFIG_GPU_TILE_128                         = 0x3,
+} MultiGPUTileSize;
+typedef enum RowSize {
+       ADDR_CONFIG_1KB_ROW                              = 0x0,
+       ADDR_CONFIG_2KB_ROW                              = 0x1,
+       ADDR_CONFIG_4KB_ROW                              = 0x2,
+} RowSize;
+typedef enum NumLowerPipes {
+       ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
+       ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
+} NumLowerPipes;
+typedef enum DebugBlockId {
+       DBG_CLIENT_BLKID_RESERVED                        = 0x0,
+       DBG_CLIENT_BLKID_dbg                             = 0x1,
+       DBG_CLIENT_BLKID_scf2                            = 0x2,
+       DBG_CLIENT_BLKID_mcd5                            = 0x3,
+       DBG_CLIENT_BLKID_vmc                             = 0x4,
+       DBG_CLIENT_BLKID_sx30                            = 0x5,
+       DBG_CLIENT_BLKID_mcd2                            = 0x6,
+       DBG_CLIENT_BLKID_bci1                            = 0x7,
+       DBG_CLIENT_BLKID_xdma_dbg_client_wrapper         = 0x8,
+       DBG_CLIENT_BLKID_mcc0                            = 0x9,
+       DBG_CLIENT_BLKID_uvdf_0                          = 0xa,
+       DBG_CLIENT_BLKID_uvdf_1                          = 0xb,
+       DBG_CLIENT_BLKID_uvdf_2                          = 0xc,
+       DBG_CLIENT_BLKID_uvdi_0                          = 0xd,
+       DBG_CLIENT_BLKID_bci0                            = 0xe,
+       DBG_CLIENT_BLKID_vcec0_0                         = 0xf,
+       DBG_CLIENT_BLKID_cb100                           = 0x10,
+       DBG_CLIENT_BLKID_cb001                           = 0x11,
+       DBG_CLIENT_BLKID_mcd4                            = 0x12,
+       DBG_CLIENT_BLKID_tmonw00                         = 0x13,
+       DBG_CLIENT_BLKID_cb101                           = 0x14,
+       DBG_CLIENT_BLKID_sx10                            = 0x15,
+       DBG_CLIENT_BLKID_cb301                           = 0x16,
+       DBG_CLIENT_BLKID_tmonw01                         = 0x17,
+       DBG_CLIENT_BLKID_vcea0_0                         = 0x18,
+       DBG_CLIENT_BLKID_vcea0_1                         = 0x19,
+       DBG_CLIENT_BLKID_vcea0_2                         = 0x1a,
+       DBG_CLIENT_BLKID_vcea0_3                         = 0x1b,
+       DBG_CLIENT_BLKID_scf1                            = 0x1c,
+       DBG_CLIENT_BLKID_sx20                            = 0x1d,
+       DBG_CLIENT_BLKID_spim1                           = 0x1e,
+       DBG_CLIENT_BLKID_pa10                            = 0x1f,
+       DBG_CLIENT_BLKID_pa00                            = 0x20,
+       DBG_CLIENT_BLKID_gmcon                           = 0x21,
+       DBG_CLIENT_BLKID_mcb                             = 0x22,
+       DBG_CLIENT_BLKID_vgt0                            = 0x23,
+       DBG_CLIENT_BLKID_pc0                             = 0x24,
+       DBG_CLIENT_BLKID_bci2                            = 0x25,
+       DBG_CLIENT_BLKID_uvdb_0                          = 0x26,
+       DBG_CLIENT_BLKID_spim3                           = 0x27,
+       DBG_CLIENT_BLKID_cpc_0                           = 0x28,
+       DBG_CLIENT_BLKID_cpc_1                           = 0x29,
+       DBG_CLIENT_BLKID_uvdm_0                          = 0x2a,
+       DBG_CLIENT_BLKID_uvdm_1                          = 0x2b,
+       DBG_CLIENT_BLKID_uvdm_2                          = 0x2c,
+       DBG_CLIENT_BLKID_uvdm_3                          = 0x2d,
+       DBG_CLIENT_BLKID_cb000                           = 0x2e,
+       DBG_CLIENT_BLKID_spim0                           = 0x2f,
+       DBG_CLIENT_BLKID_mcc2                            = 0x30,
+       DBG_CLIENT_BLKID_ds0                             = 0x31,
+       DBG_CLIENT_BLKID_srbm                            = 0x32,
+       DBG_CLIENT_BLKID_ih                              = 0x33,
+       DBG_CLIENT_BLKID_sem                             = 0x34,
+       DBG_CLIENT_BLKID_sdma_0                          = 0x35,
+       DBG_CLIENT_BLKID_sdma_1                          = 0x36,
+       DBG_CLIENT_BLKID_hdp                             = 0x37,
+       DBG_CLIENT_BLKID_acp_0                           = 0x38,
+       DBG_CLIENT_BLKID_acp_1                           = 0x39,
+       DBG_CLIENT_BLKID_cb200                           = 0x3a,
+       DBG_CLIENT_BLKID_scf3                            = 0x3b,
+       DBG_CLIENT_BLKID_vceb1_0                         = 0x3c,
+       DBG_CLIENT_BLKID_vcea1_0                         = 0x3d,
+       DBG_CLIENT_BLKID_vcea1_1                         = 0x3e,
+       DBG_CLIENT_BLKID_vcea1_2                         = 0x3f,
+       DBG_CLIENT_BLKID_vcea1_3                         = 0x40,
+       DBG_CLIENT_BLKID_bci3                            = 0x41,
+       DBG_CLIENT_BLKID_mcd0                            = 0x42,
+       DBG_CLIENT_BLKID_pa11                            = 0x43,
+       DBG_CLIENT_BLKID_pa01                            = 0x44,
+       DBG_CLIENT_BLKID_cb201                           = 0x45,
+       DBG_CLIENT_BLKID_spim2                           = 0x46,
+       DBG_CLIENT_BLKID_vgt2                            = 0x47,
+       DBG_CLIENT_BLKID_pc2                             = 0x48,
+       DBG_CLIENT_BLKID_smu_0                           = 0x49,
+       DBG_CLIENT_BLKID_smu_1                           = 0x4a,
+       DBG_CLIENT_BLKID_smu_2                           = 0x4b,
+       DBG_CLIENT_BLKID_cb1                             = 0x4c,
+       DBG_CLIENT_BLKID_ia0                             = 0x4d,
+       DBG_CLIENT_BLKID_wd                              = 0x4e,
+       DBG_CLIENT_BLKID_ia1                             = 0x4f,
+       DBG_CLIENT_BLKID_vcec1_0                         = 0x50,
+       DBG_CLIENT_BLKID_scf0                            = 0x51,
+       DBG_CLIENT_BLKID_vgt1                            = 0x52,
+       DBG_CLIENT_BLKID_pc1                             = 0x53,
+       DBG_CLIENT_BLKID_cb0                             = 0x54,
+       DBG_CLIENT_BLKID_gdc_one_0                       = 0x55,
+       DBG_CLIENT_BLKID_gdc_one_1                       = 0x56,
+       DBG_CLIENT_BLKID_gdc_one_2                       = 0x57,
+       DBG_CLIENT_BLKID_gdc_one_3                       = 0x58,
+       DBG_CLIENT_BLKID_gdc_one_4                       = 0x59,
+       DBG_CLIENT_BLKID_gdc_one_5                       = 0x5a,
+       DBG_CLIENT_BLKID_gdc_one_6                       = 0x5b,
+       DBG_CLIENT_BLKID_gdc_one_7                       = 0x5c,
+       DBG_CLIENT_BLKID_gdc_one_8                       = 0x5d,
+       DBG_CLIENT_BLKID_gdc_one_9                       = 0x5e,
+       DBG_CLIENT_BLKID_gdc_one_10                      = 0x5f,
+       DBG_CLIENT_BLKID_gdc_one_11                      = 0x60,
+       DBG_CLIENT_BLKID_gdc_one_12                      = 0x61,
+       DBG_CLIENT_BLKID_gdc_one_13                      = 0x62,
+       DBG_CLIENT_BLKID_gdc_one_14                      = 0x63,
+       DBG_CLIENT_BLKID_gdc_one_15                      = 0x64,
+       DBG_CLIENT_BLKID_gdc_one_16                      = 0x65,
+       DBG_CLIENT_BLKID_gdc_one_17                      = 0x66,
+       DBG_CLIENT_BLKID_gdc_one_18                      = 0x67,
+       DBG_CLIENT_BLKID_gdc_one_19                      = 0x68,
+       DBG_CLIENT_BLKID_gdc_one_20                      = 0x69,
+       DBG_CLIENT_BLKID_gdc_one_21                      = 0x6a,
+       DBG_CLIENT_BLKID_gdc_one_22                      = 0x6b,
+       DBG_CLIENT_BLKID_gdc_one_23                      = 0x6c,
+       DBG_CLIENT_BLKID_gdc_one_24                      = 0x6d,
+       DBG_CLIENT_BLKID_gdc_one_25                      = 0x6e,
+       DBG_CLIENT_BLKID_gdc_one_26                      = 0x6f,
+       DBG_CLIENT_BLKID_gdc_one_27                      = 0x70,
+       DBG_CLIENT_BLKID_gdc_one_28                      = 0x71,
+       DBG_CLIENT_BLKID_gdc_one_29                      = 0x72,
+       DBG_CLIENT_BLKID_gdc_one_30                      = 0x73,
+       DBG_CLIENT_BLKID_gdc_one_31                      = 0x74,
+       DBG_CLIENT_BLKID_gdc_one_32                      = 0x75,
+       DBG_CLIENT_BLKID_gdc_one_33                      = 0x76,
+       DBG_CLIENT_BLKID_gdc_one_34                      = 0x77,
+       DBG_CLIENT_BLKID_gdc_one_35                      = 0x78,
+       DBG_CLIENT_BLKID_vceb0_0                         = 0x79,
+       DBG_CLIENT_BLKID_vgt3                            = 0x7a,
+       DBG_CLIENT_BLKID_pc3                             = 0x7b,
+       DBG_CLIENT_BLKID_mcd3                            = 0x7c,
+       DBG_CLIENT_BLKID_uvdu_0                          = 0x7d,
+       DBG_CLIENT_BLKID_uvdu_1                          = 0x7e,
+       DBG_CLIENT_BLKID_uvdu_2                          = 0x7f,
+       DBG_CLIENT_BLKID_uvdu_3                          = 0x80,
+       DBG_CLIENT_BLKID_uvdu_4                          = 0x81,
+       DBG_CLIENT_BLKID_uvdu_5                          = 0x82,
+       DBG_CLIENT_BLKID_uvdu_6                          = 0x83,
+       DBG_CLIENT_BLKID_cb300                           = 0x84,
+       DBG_CLIENT_BLKID_mcd1                            = 0x85,
+       DBG_CLIENT_BLKID_sx00                            = 0x86,
+       DBG_CLIENT_BLKID_uvdc_0                          = 0x87,
+       DBG_CLIENT_BLKID_uvdc_1                          = 0x88,
+       DBG_CLIENT_BLKID_mcc3                            = 0x89,
+       DBG_CLIENT_BLKID_cpg_0                           = 0x8a,
+       DBG_CLIENT_BLKID_cpg_1                           = 0x8b,
+       DBG_CLIENT_BLKID_gck                             = 0x8c,
+       DBG_CLIENT_BLKID_mcc1                            = 0x8d,
+       DBG_CLIENT_BLKID_cpf_0                           = 0x8e,
+       DBG_CLIENT_BLKID_cpf_1                           = 0x8f,
+       DBG_CLIENT_BLKID_rlc                             = 0x90,
+       DBG_CLIENT_BLKID_grbm                            = 0x91,
+       DBG_CLIENT_BLKID_sammsp                          = 0x92,
+       DBG_CLIENT_BLKID_dci_pg                          = 0x93,
+       DBG_CLIENT_BLKID_dci_0                           = 0x94,
+       DBG_CLIENT_BLKID_dccg0_0                         = 0x95,
+       DBG_CLIENT_BLKID_dccg0_1                         = 0x96,
+       DBG_CLIENT_BLKID_dcfe01_0                        = 0x97,
+       DBG_CLIENT_BLKID_dcfe02_0                        = 0x98,
+       DBG_CLIENT_BLKID_dcfe03_0                        = 0x99,
+       DBG_CLIENT_BLKID_dcfe04_0                        = 0x9a,
+       DBG_CLIENT_BLKID_dcfe05_0                        = 0x9b,
+       DBG_CLIENT_BLKID_dcfe06_0                        = 0x9c,
+       DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x9d,
+} DebugBlockId;
+typedef enum DebugBlockId_OLD {
+       DBG_BLOCK_ID_RESERVED                            = 0x0,
+       DBG_BLOCK_ID_DBG                                 = 0x1,
+       DBG_BLOCK_ID_VMC                                 = 0x2,
+       DBG_BLOCK_ID_PDMA                                = 0x3,
+       DBG_BLOCK_ID_CG                                  = 0x4,
+       DBG_BLOCK_ID_SRBM                                = 0x5,
+       DBG_BLOCK_ID_GRBM                                = 0x6,
+       DBG_BLOCK_ID_RLC                                 = 0x7,
+       DBG_BLOCK_ID_CSC                                 = 0x8,
+       DBG_BLOCK_ID_SEM                                 = 0x9,
+       DBG_BLOCK_ID_IH                                  = 0xa,
+       DBG_BLOCK_ID_SC                                  = 0xb,
+       DBG_BLOCK_ID_SQ                                  = 0xc,
+       DBG_BLOCK_ID_AVP                                 = 0xd,
+       DBG_BLOCK_ID_GMCON                               = 0xe,
+       DBG_BLOCK_ID_SMU                                 = 0xf,
+       DBG_BLOCK_ID_DMA0                                = 0x10,
+       DBG_BLOCK_ID_DMA1                                = 0x11,
+       DBG_BLOCK_ID_SPIM                                = 0x12,
+       DBG_BLOCK_ID_GDS                                 = 0x13,
+       DBG_BLOCK_ID_SPIS                                = 0x14,
+       DBG_BLOCK_ID_UNUSED0                             = 0x15,
+       DBG_BLOCK_ID_PA0                                 = 0x16,
+       DBG_BLOCK_ID_PA1                                 = 0x17,
+       DBG_BLOCK_ID_CP0                                 = 0x18,
+       DBG_BLOCK_ID_CP1                                 = 0x19,
+       DBG_BLOCK_ID_CP2                                 = 0x1a,
+       DBG_BLOCK_ID_UNUSED1                             = 0x1b,
+       DBG_BLOCK_ID_UVDU                                = 0x1c,
+       DBG_BLOCK_ID_UVDM                                = 0x1d,
+       DBG_BLOCK_ID_VCE                                 = 0x1e,
+       DBG_BLOCK_ID_UNUSED2                             = 0x1f,
+       DBG_BLOCK_ID_VGT0                                = 0x20,
+       DBG_BLOCK_ID_VGT1                                = 0x21,
+       DBG_BLOCK_ID_IA                                  = 0x22,
+       DBG_BLOCK_ID_UNUSED3                             = 0x23,
+       DBG_BLOCK_ID_SCT0                                = 0x24,
+       DBG_BLOCK_ID_SCT1                                = 0x25,
+       DBG_BLOCK_ID_SPM0                                = 0x26,
+       DBG_BLOCK_ID_SPM1                                = 0x27,
+       DBG_BLOCK_ID_TCAA                                = 0x28,
+       DBG_BLOCK_ID_TCAB                                = 0x29,
+       DBG_BLOCK_ID_TCCA                                = 0x2a,
+       DBG_BLOCK_ID_TCCB                                = 0x2b,
+       DBG_BLOCK_ID_MCC0                                = 0x2c,
+       DBG_BLOCK_ID_MCC1                                = 0x2d,
+       DBG_BLOCK_ID_MCC2                                = 0x2e,
+       DBG_BLOCK_ID_MCC3                                = 0x2f,
+       DBG_BLOCK_ID_SX0                                 = 0x30,
+       DBG_BLOCK_ID_SX1                                 = 0x31,
+       DBG_BLOCK_ID_SX2                                 = 0x32,
+       DBG_BLOCK_ID_SX3                                 = 0x33,
+       DBG_BLOCK_ID_UNUSED4                             = 0x34,
+       DBG_BLOCK_ID_UNUSED5                             = 0x35,
+       DBG_BLOCK_ID_UNUSED6                             = 0x36,
+       DBG_BLOCK_ID_UNUSED7                             = 0x37,
+       DBG_BLOCK_ID_PC0                                 = 0x38,
+       DBG_BLOCK_ID_PC1                                 = 0x39,
+       DBG_BLOCK_ID_UNUSED8                             = 0x3a,
+       DBG_BLOCK_ID_UNUSED9                             = 0x3b,
+       DBG_BLOCK_ID_UNUSED10                            = 0x3c,
+       DBG_BLOCK_ID_UNUSED11                            = 0x3d,
+       DBG_BLOCK_ID_MCB                                 = 0x3e,
+       DBG_BLOCK_ID_UNUSED12                            = 0x3f,
+       DBG_BLOCK_ID_SCB0                                = 0x40,
+       DBG_BLOCK_ID_SCB1                                = 0x41,
+       DBG_BLOCK_ID_UNUSED13                            = 0x42,
+       DBG_BLOCK_ID_UNUSED14                            = 0x43,
+       DBG_BLOCK_ID_SCF0                                = 0x44,
+       DBG_BLOCK_ID_SCF1                                = 0x45,
+       DBG_BLOCK_ID_UNUSED15                            = 0x46,
+       DBG_BLOCK_ID_UNUSED16                            = 0x47,
+       DBG_BLOCK_ID_BCI0                                = 0x48,
+       DBG_BLOCK_ID_BCI1                                = 0x49,
+       DBG_BLOCK_ID_BCI2                                = 0x4a,
+       DBG_BLOCK_ID_BCI3                                = 0x4b,
+       DBG_BLOCK_ID_UNUSED17                            = 0x4c,
+       DBG_BLOCK_ID_UNUSED18                            = 0x4d,
+       DBG_BLOCK_ID_UNUSED19                            = 0x4e,
+       DBG_BLOCK_ID_UNUSED20                            = 0x4f,
+       DBG_BLOCK_ID_CB00                                = 0x50,
+       DBG_BLOCK_ID_CB01                                = 0x51,
+       DBG_BLOCK_ID_CB02                                = 0x52,
+       DBG_BLOCK_ID_CB03                                = 0x53,
+       DBG_BLOCK_ID_CB04                                = 0x54,
+       DBG_BLOCK_ID_UNUSED21                            = 0x55,
+       DBG_BLOCK_ID_UNUSED22                            = 0x56,
+       DBG_BLOCK_ID_UNUSED23                            = 0x57,
+       DBG_BLOCK_ID_CB10                                = 0x58,
+       DBG_BLOCK_ID_CB11                                = 0x59,
+       DBG_BLOCK_ID_CB12                                = 0x5a,
+       DBG_BLOCK_ID_CB13                                = 0x5b,
+       DBG_BLOCK_ID_CB14                                = 0x5c,
+       DBG_BLOCK_ID_UNUSED24                            = 0x5d,
+       DBG_BLOCK_ID_UNUSED25                            = 0x5e,
+       DBG_BLOCK_ID_UNUSED26                            = 0x5f,
+       DBG_BLOCK_ID_TCP0                                = 0x60,
+       DBG_BLOCK_ID_TCP1                                = 0x61,
+       DBG_BLOCK_ID_TCP2                                = 0x62,
+       DBG_BLOCK_ID_TCP3                                = 0x63,
+       DBG_BLOCK_ID_TCP4                                = 0x64,
+       DBG_BLOCK_ID_TCP5                                = 0x65,
+       DBG_BLOCK_ID_TCP6                                = 0x66,
+       DBG_BLOCK_ID_TCP7                                = 0x67,
+       DBG_BLOCK_ID_TCP8                                = 0x68,
+       DBG_BLOCK_ID_TCP9                                = 0x69,
+       DBG_BLOCK_ID_TCP10                               = 0x6a,
+       DBG_BLOCK_ID_TCP11                               = 0x6b,
+       DBG_BLOCK_ID_TCP12                               = 0x6c,
+       DBG_BLOCK_ID_TCP13                               = 0x6d,
+       DBG_BLOCK_ID_TCP14                               = 0x6e,
+       DBG_BLOCK_ID_TCP15                               = 0x6f,
+       DBG_BLOCK_ID_TCP16                               = 0x70,
+       DBG_BLOCK_ID_TCP17                               = 0x71,
+       DBG_BLOCK_ID_TCP18                               = 0x72,
+       DBG_BLOCK_ID_TCP19                               = 0x73,
+       DBG_BLOCK_ID_TCP20                               = 0x74,
+       DBG_BLOCK_ID_TCP21                               = 0x75,
+       DBG_BLOCK_ID_TCP22                               = 0x76,
+       DBG_BLOCK_ID_TCP23                               = 0x77,
+       DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
+       DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
+       DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
+       DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
+       DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
+       DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
+       DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
+       DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
+       DBG_BLOCK_ID_DB00                                = 0x80,
+       DBG_BLOCK_ID_DB01                                = 0x81,
+       DBG_BLOCK_ID_DB02                                = 0x82,
+       DBG_BLOCK_ID_DB03                                = 0x83,
+       DBG_BLOCK_ID_DB04                                = 0x84,
+       DBG_BLOCK_ID_UNUSED27                            = 0x85,
+       DBG_BLOCK_ID_UNUSED28                            = 0x86,
+       DBG_BLOCK_ID_UNUSED29                            = 0x87,
+       DBG_BLOCK_ID_DB10                                = 0x88,
+       DBG_BLOCK_ID_DB11                                = 0x89,
+       DBG_BLOCK_ID_DB12                                = 0x8a,
+       DBG_BLOCK_ID_DB13                                = 0x8b,
+       DBG_BLOCK_ID_DB14                                = 0x8c,
+       DBG_BLOCK_ID_UNUSED30                            = 0x8d,
+       DBG_BLOCK_ID_UNUSED31                            = 0x8e,
+       DBG_BLOCK_ID_UNUSED32                            = 0x8f,
+       DBG_BLOCK_ID_TCC0                                = 0x90,
+       DBG_BLOCK_ID_TCC1                                = 0x91,
+       DBG_BLOCK_ID_TCC2                                = 0x92,
+       DBG_BLOCK_ID_TCC3                                = 0x93,
+       DBG_BLOCK_ID_TCC4                                = 0x94,
+       DBG_BLOCK_ID_TCC5                                = 0x95,
+       DBG_BLOCK_ID_TCC6                                = 0x96,
+       DBG_BLOCK_ID_TCC7                                = 0x97,
+       DBG_BLOCK_ID_SPS00                               = 0x98,
+       DBG_BLOCK_ID_SPS01                               = 0x99,
+       DBG_BLOCK_ID_SPS02                               = 0x9a,
+       DBG_BLOCK_ID_SPS10                               = 0x9b,
+       DBG_BLOCK_ID_SPS11                               = 0x9c,
+       DBG_BLOCK_ID_SPS12                               = 0x9d,
+       DBG_BLOCK_ID_UNUSED33                            = 0x9e,
+       DBG_BLOCK_ID_UNUSED34                            = 0x9f,
+       DBG_BLOCK_ID_TA00                                = 0xa0,
+       DBG_BLOCK_ID_TA01                                = 0xa1,
+       DBG_BLOCK_ID_TA02                                = 0xa2,
+       DBG_BLOCK_ID_TA03                                = 0xa3,
+       DBG_BLOCK_ID_TA04                                = 0xa4,
+       DBG_BLOCK_ID_TA05                                = 0xa5,
+       DBG_BLOCK_ID_TA06                                = 0xa6,
+       DBG_BLOCK_ID_TA07                                = 0xa7,
+       DBG_BLOCK_ID_TA08                                = 0xa8,
+       DBG_BLOCK_ID_TA09                                = 0xa9,
+       DBG_BLOCK_ID_TA0A                                = 0xaa,
+       DBG_BLOCK_ID_TA0B                                = 0xab,
+       DBG_BLOCK_ID_UNUSED35                            = 0xac,
+       DBG_BLOCK_ID_UNUSED36                            = 0xad,
+       DBG_BLOCK_ID_UNUSED37                            = 0xae,
+       DBG_BLOCK_ID_UNUSED38                            = 0xaf,
+       DBG_BLOCK_ID_TA10                                = 0xb0,
+       DBG_BLOCK_ID_TA11                                = 0xb1,
+       DBG_BLOCK_ID_TA12                                = 0xb2,
+       DBG_BLOCK_ID_TA13                                = 0xb3,
+       DBG_BLOCK_ID_TA14                                = 0xb4,
+       DBG_BLOCK_ID_TA15                                = 0xb5,
+       DBG_BLOCK_ID_TA16                                = 0xb6,
+       DBG_BLOCK_ID_TA17                                = 0xb7,
+       DBG_BLOCK_ID_TA18                                = 0xb8,
+       DBG_BLOCK_ID_TA19                                = 0xb9,
+       DBG_BLOCK_ID_TA1A                                = 0xba,
+       DBG_BLOCK_ID_TA1B                                = 0xbb,
+       DBG_BLOCK_ID_UNUSED39                            = 0xbc,
+       DBG_BLOCK_ID_UNUSED40                            = 0xbd,
+       DBG_BLOCK_ID_UNUSED41                            = 0xbe,
+       DBG_BLOCK_ID_UNUSED42                            = 0xbf,
+       DBG_BLOCK_ID_TD00                                = 0xc0,
+       DBG_BLOCK_ID_TD01                                = 0xc1,
+       DBG_BLOCK_ID_TD02                                = 0xc2,
+       DBG_BLOCK_ID_TD03                                = 0xc3,
+       DBG_BLOCK_ID_TD04                                = 0xc4,
+       DBG_BLOCK_ID_TD05                                = 0xc5,
+       DBG_BLOCK_ID_TD06                                = 0xc6,
+       DBG_BLOCK_ID_TD07                                = 0xc7,
+       DBG_BLOCK_ID_TD08                                = 0xc8,
+       DBG_BLOCK_ID_TD09                                = 0xc9,
+       DBG_BLOCK_ID_TD0A                                = 0xca,
+       DBG_BLOCK_ID_TD0B                                = 0xcb,
+       DBG_BLOCK_ID_UNUSED43                            = 0xcc,
+       DBG_BLOCK_ID_UNUSED44                            = 0xcd,
+       DBG_BLOCK_ID_UNUSED45                            = 0xce,
+       DBG_BLOCK_ID_UNUSED46                            = 0xcf,
+       DBG_BLOCK_ID_TD10                                = 0xd0,
+       DBG_BLOCK_ID_TD11                                = 0xd1,
+       DBG_BLOCK_ID_TD12                                = 0xd2,
+       DBG_BLOCK_ID_TD13                                = 0xd3,
+       DBG_BLOCK_ID_TD14                                = 0xd4,
+       DBG_BLOCK_ID_TD15                                = 0xd5,
+       DBG_BLOCK_ID_TD16                                = 0xd6,
+       DBG_BLOCK_ID_TD17                                = 0xd7,
+       DBG_BLOCK_ID_TD18                                = 0xd8,
+       DBG_BLOCK_ID_TD19                                = 0xd9,
+       DBG_BLOCK_ID_TD1A                                = 0xda,
+       DBG_BLOCK_ID_TD1B                                = 0xdb,
+       DBG_BLOCK_ID_UNUSED47                            = 0xdc,
+       DBG_BLOCK_ID_UNUSED48                            = 0xdd,
+       DBG_BLOCK_ID_UNUSED49                            = 0xde,
+       DBG_BLOCK_ID_UNUSED50                            = 0xdf,
+       DBG_BLOCK_ID_MCD0                                = 0xe0,
+       DBG_BLOCK_ID_MCD1                                = 0xe1,
+       DBG_BLOCK_ID_MCD2                                = 0xe2,
+       DBG_BLOCK_ID_MCD3                                = 0xe3,
+       DBG_BLOCK_ID_MCD4                                = 0xe4,
+       DBG_BLOCK_ID_MCD5                                = 0xe5,
+       DBG_BLOCK_ID_UNUSED51                            = 0xe6,
+       DBG_BLOCK_ID_UNUSED52                            = 0xe7,
+} DebugBlockId_OLD;
+typedef enum DebugBlockId_BY2 {
+       DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
+       DBG_BLOCK_ID_VMC_BY2                             = 0x1,
+       DBG_BLOCK_ID_CG_BY2                              = 0x2,
+       DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
+       DBG_BLOCK_ID_CSC_BY2                             = 0x4,
+       DBG_BLOCK_ID_IH_BY2                              = 0x5,
+       DBG_BLOCK_ID_SQ_BY2                              = 0x6,
+       DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
+       DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
+       DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
+       DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
+       DBG_BLOCK_ID_PA0_BY2                             = 0xb,
+       DBG_BLOCK_ID_CP0_BY2                             = 0xc,
+       DBG_BLOCK_ID_CP2_BY2                             = 0xd,
+       DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
+       DBG_BLOCK_ID_VCE_BY2                             = 0xf,
+       DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
+       DBG_BLOCK_ID_IA_BY2                              = 0x11,
+       DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
+       DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
+       DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
+       DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
+       DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
+       DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
+       DBG_BLOCK_ID_SX0_BY2                             = 0x18,
+       DBG_BLOCK_ID_SX2_BY2                             = 0x19,
+       DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
+       DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
+       DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
+       DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
+       DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
+       DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
+       DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
+       DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
+       DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
+       DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
+       DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
+       DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
+       DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
+       DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
+       DBG_BLOCK_ID_CB00_BY2                            = 0x28,
+       DBG_BLOCK_ID_CB02_BY2                            = 0x29,
+       DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
+       DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
+       DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
+       DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
+       DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
+       DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
+       DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
+       DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
+       DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
+       DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
+       DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
+       DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
+       DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
+       DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
+       DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
+       DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
+       DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
+       DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
+       DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
+       DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
+       DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
+       DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
+       DBG_BLOCK_ID_DB00_BY2                            = 0x40,
+       DBG_BLOCK_ID_DB02_BY2                            = 0x41,
+       DBG_BLOCK_ID_DB04_BY2                            = 0x42,
+       DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
+       DBG_BLOCK_ID_DB10_BY2                            = 0x44,
+       DBG_BLOCK_ID_DB12_BY2                            = 0x45,
+       DBG_BLOCK_ID_DB14_BY2                            = 0x46,
+       DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
+       DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
+       DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
+       DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
+       DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
+       DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
+       DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
+       DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
+       DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
+       DBG_BLOCK_ID_TA00_BY2                            = 0x50,
+       DBG_BLOCK_ID_TA02_BY2                            = 0x51,
+       DBG_BLOCK_ID_TA04_BY2                            = 0x52,
+       DBG_BLOCK_ID_TA06_BY2                            = 0x53,
+       DBG_BLOCK_ID_TA08_BY2                            = 0x54,
+       DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
+       DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
+       DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
+       DBG_BLOCK_ID_TA10_BY2                            = 0x58,
+       DBG_BLOCK_ID_TA12_BY2                            = 0x59,
+       DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
+       DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
+       DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
+       DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
+       DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
+       DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
+       DBG_BLOCK_ID_TD00_BY2                            = 0x60,
+       DBG_BLOCK_ID_TD02_BY2                            = 0x61,
+       DBG_BLOCK_ID_TD04_BY2                            = 0x62,
+       DBG_BLOCK_ID_TD06_BY2                            = 0x63,
+       DBG_BLOCK_ID_TD08_BY2                            = 0x64,
+       DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
+       DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
+       DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
+       DBG_BLOCK_ID_TD10_BY2                            = 0x68,
+       DBG_BLOCK_ID_TD12_BY2                            = 0x69,
+       DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
+       DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
+       DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
+       DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
+       DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
+       DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
+       DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
+       DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
+       DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
+       DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
+} DebugBlockId_BY2;
+typedef enum DebugBlockId_BY4 {
+       DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
+       DBG_BLOCK_ID_CG_BY4                              = 0x1,
+       DBG_BLOCK_ID_CSC_BY4                             = 0x2,
+       DBG_BLOCK_ID_SQ_BY4                              = 0x3,
+       DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
+       DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
+       DBG_BLOCK_ID_CP0_BY4                             = 0x6,
+       DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
+       DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
+       DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
+       DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
+       DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
+       DBG_BLOCK_ID_SX0_BY4                             = 0xc,
+       DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
+       DBG_BLOCK_ID_PC0_BY4                             = 0xe,
+       DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
+       DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
+       DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
+       DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
+       DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
+       DBG_BLOCK_ID_CB00_BY4                            = 0x14,
+       DBG_BLOCK_ID_CB04_BY4                            = 0x15,
+       DBG_BLOCK_ID_CB10_BY4                            = 0x16,
+       DBG_BLOCK_ID_CB14_BY4                            = 0x17,
+       DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
+       DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
+       DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
+       DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
+       DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
+       DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
+       DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
+       DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
+       DBG_BLOCK_ID_DB_BY4                              = 0x20,
+       DBG_BLOCK_ID_DB04_BY4                            = 0x21,
+       DBG_BLOCK_ID_DB10_BY4                            = 0x22,
+       DBG_BLOCK_ID_DB14_BY4                            = 0x23,
+       DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
+       DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
+       DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
+       DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
+       DBG_BLOCK_ID_TA00_BY4                            = 0x28,
+       DBG_BLOCK_ID_TA04_BY4                            = 0x29,
+       DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
+       DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
+       DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
+       DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
+       DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
+       DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
+       DBG_BLOCK_ID_TD00_BY4                            = 0x30,
+       DBG_BLOCK_ID_TD04_BY4                            = 0x31,
+       DBG_BLOCK_ID_TD08_BY4                            = 0x32,
+       DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
+       DBG_BLOCK_ID_TD10_BY4                            = 0x34,
+       DBG_BLOCK_ID_TD14_BY4                            = 0x35,
+       DBG_BLOCK_ID_TD18_BY4                            = 0x36,
+       DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
+       DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
+       DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
+} DebugBlockId_BY4;
+typedef enum DebugBlockId_BY8 {
+       DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
+       DBG_BLOCK_ID_CSC_BY8                             = 0x1,
+       DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
+       DBG_BLOCK_ID_CP0_BY8                             = 0x3,
+       DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
+       DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
+       DBG_BLOCK_ID_SX0_BY8                             = 0x6,
+       DBG_BLOCK_ID_PC0_BY8                             = 0x7,
+       DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
+       DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
+       DBG_BLOCK_ID_CB00_BY8                            = 0xa,
+       DBG_BLOCK_ID_CB10_BY8                            = 0xb,
+       DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
+       DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
+       DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
+       DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
+       DBG_BLOCK_ID_DB00_BY8                            = 0x10,
+       DBG_BLOCK_ID_DB10_BY8                            = 0x11,
+       DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
+       DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
+       DBG_BLOCK_ID_TA00_BY8                            = 0x14,
+       DBG_BLOCK_ID_TA08_BY8                            = 0x15,
+       DBG_BLOCK_ID_TA10_BY8                            = 0x16,
+       DBG_BLOCK_ID_TA18_BY8                            = 0x17,
+       DBG_BLOCK_ID_TD00_BY8                            = 0x18,
+       DBG_BLOCK_ID_TD08_BY8                            = 0x19,
+       DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
+       DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
+       DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
+} DebugBlockId_BY8;
+typedef enum DebugBlockId_BY16 {
+       DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
+       DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
+       DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
+       DBG_BLOCK_ID_SX0_BY16                            = 0x3,
+       DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
+       DBG_BLOCK_ID_CB00_BY16                           = 0x5,
+       DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
+       DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
+       DBG_BLOCK_ID_DB00_BY16                           = 0x8,
+       DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
+       DBG_BLOCK_ID_TA00_BY16                           = 0xa,
+       DBG_BLOCK_ID_TA10_BY16                           = 0xb,
+       DBG_BLOCK_ID_TD00_BY16                           = 0xc,
+       DBG_BLOCK_ID_TD10_BY16                           = 0xd,
+       DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
+} DebugBlockId_BY16;
+typedef enum ColorTransform {
+       DCC_CT_AUTO                                      = 0x0,
+       DCC_CT_NONE                                      = 0x1,
+       ABGR_TO_A_BG_G_RB                                = 0x2,
+       BGRA_TO_BG_G_RB_A                                = 0x3,
+} ColorTransform;
+typedef enum CompareRef {
+       REF_NEVER                                        = 0x0,
+       REF_LESS                                         = 0x1,
+       REF_EQUAL                                        = 0x2,
+       REF_LEQUAL                                       = 0x3,
+       REF_GREATER                                      = 0x4,
+       REF_NOTEQUAL                                     = 0x5,
+       REF_GEQUAL                                       = 0x6,
+       REF_ALWAYS                                       = 0x7,
+} CompareRef;
+typedef enum ReadSize {
+       READ_256_BITS                                    = 0x0,
+       READ_512_BITS                                    = 0x1,
+} ReadSize;
+typedef enum DepthFormat {
+       DEPTH_INVALID                                    = 0x0,
+       DEPTH_16                                         = 0x1,
+       DEPTH_X8_24                                      = 0x2,
+       DEPTH_8_24                                       = 0x3,
+       DEPTH_X8_24_FLOAT                                = 0x4,
+       DEPTH_8_24_FLOAT                                 = 0x5,
+       DEPTH_32_FLOAT                                   = 0x6,
+       DEPTH_X24_8_32_FLOAT                             = 0x7,
+} DepthFormat;
+typedef enum ZFormat {
+       Z_INVALID                                        = 0x0,
+       Z_16                                             = 0x1,
+       Z_24                                             = 0x2,
+       Z_32_FLOAT                                       = 0x3,
+} ZFormat;
+typedef enum StencilFormat {
+       STENCIL_INVALID                                  = 0x0,
+       STENCIL_8                                        = 0x1,
+} StencilFormat;
+typedef enum CmaskMode {
+       CMASK_CLEAR_NONE                                 = 0x0,
+       CMASK_CLEAR_ONE                                  = 0x1,
+       CMASK_CLEAR_ALL                                  = 0x2,
+       CMASK_ANY_EXPANDED                               = 0x3,
+       CMASK_ALPHA0_FRAG1                               = 0x4,
+       CMASK_ALPHA0_FRAG2                               = 0x5,
+       CMASK_ALPHA0_FRAG4                               = 0x6,
+       CMASK_ALPHA0_FRAGS                               = 0x7,
+       CMASK_ALPHA1_FRAG1                               = 0x8,
+       CMASK_ALPHA1_FRAG2                               = 0x9,
+       CMASK_ALPHA1_FRAG4                               = 0xa,
+       CMASK_ALPHA1_FRAGS                               = 0xb,
+       CMASK_ALPHAX_FRAG1                               = 0xc,
+       CMASK_ALPHAX_FRAG2                               = 0xd,
+       CMASK_ALPHAX_FRAG4                               = 0xe,
+       CMASK_ALPHAX_FRAGS                               = 0xf,
+} CmaskMode;
+typedef enum QuadExportFormat {
+       EXPORT_UNUSED                                    = 0x0,
+       EXPORT_32_R                                      = 0x1,
+       EXPORT_32_GR                                     = 0x2,
+       EXPORT_32_AR                                     = 0x3,
+       EXPORT_FP16_ABGR                                 = 0x4,
+       EXPORT_UNSIGNED16_ABGR                           = 0x5,
+       EXPORT_SIGNED16_ABGR                             = 0x6,
+       EXPORT_32_ABGR                                   = 0x7,
+} QuadExportFormat;
+typedef enum QuadExportFormatOld {
+       EXPORT_4P_32BPC_ABGR                             = 0x0,
+       EXPORT_4P_16BPC_ABGR                             = 0x1,
+       EXPORT_4P_32BPC_GR                               = 0x2,
+       EXPORT_4P_32BPC_AR                               = 0x3,
+       EXPORT_2P_32BPC_ABGR                             = 0x4,
+       EXPORT_8P_32BPC_R                                = 0x5,
+} QuadExportFormatOld;
+typedef enum ColorFormat {
+       COLOR_INVALID                                    = 0x0,
+       COLOR_8                                          = 0x1,
+       COLOR_16                                         = 0x2,
+       COLOR_8_8                                        = 0x3,
+       COLOR_32                                         = 0x4,
+       COLOR_16_16                                      = 0x5,
+       COLOR_10_11_11                                   = 0x6,
+       COLOR_11_11_10                                   = 0x7,
+       COLOR_10_10_10_2                                 = 0x8,
+       COLOR_2_10_10_10                                 = 0x9,
+       COLOR_8_8_8_8                                    = 0xa,
+       COLOR_32_32                                      = 0xb,
+       COLOR_16_16_16_16                                = 0xc,
+       COLOR_RESERVED_13                                = 0xd,
+       COLOR_32_32_32_32                                = 0xe,
+       COLOR_RESERVED_15                                = 0xf,
+       COLOR_5_6_5                                      = 0x10,
+       COLOR_1_5_5_5                                    = 0x11,
+       COLOR_5_5_5_1                                    = 0x12,
+       COLOR_4_4_4_4                                    = 0x13,
+       COLOR_8_24                                       = 0x14,
+       COLOR_24_8                                       = 0x15,
+       COLOR_X24_8_32_FLOAT                             = 0x16,
+       COLOR_RESERVED_23                                = 0x17,
+} ColorFormat;
+typedef enum SurfaceFormat {
+       FMT_INVALID                                      = 0x0,
+       FMT_8                                            = 0x1,
+       FMT_16                                           = 0x2,
+       FMT_8_8                                          = 0x3,
+       FMT_32                                           = 0x4,
+       FMT_16_16                                        = 0x5,
+       FMT_10_11_11                                     = 0x6,
+       FMT_11_11_10                                     = 0x7,
+       FMT_10_10_10_2                                   = 0x8,
+       FMT_2_10_10_10                                   = 0x9,
+       FMT_8_8_8_8                                      = 0xa,
+       FMT_32_32                                        = 0xb,
+       FMT_16_16_16_16                                  = 0xc,
+       FMT_32_32_32                                     = 0xd,
+       FMT_32_32_32_32                                  = 0xe,
+       FMT_RESERVED_4                                   = 0xf,
+       FMT_5_6_5                                        = 0x10,
+       FMT_1_5_5_5                                      = 0x11,
+       FMT_5_5_5_1                                      = 0x12,
+       FMT_4_4_4_4                                      = 0x13,
+       FMT_8_24                                         = 0x14,
+       FMT_24_8                                         = 0x15,
+       FMT_X24_8_32_FLOAT                               = 0x16,
+       FMT_RESERVED_33                                  = 0x17,
+       FMT_11_11_10_FLOAT                               = 0x18,
+       FMT_16_FLOAT                                     = 0x19,
+       FMT_32_FLOAT                                     = 0x1a,
+       FMT_16_16_FLOAT                                  = 0x1b,
+       FMT_8_24_FLOAT                                   = 0x1c,
+       FMT_24_8_FLOAT                                   = 0x1d,
+       FMT_32_32_FLOAT                                  = 0x1e,
+       FMT_10_11_11_FLOAT                               = 0x1f,
+       FMT_16_16_16_16_FLOAT                            = 0x20,
+       FMT_3_3_2                                        = 0x21,
+       FMT_6_5_5                                        = 0x22,
+       FMT_32_32_32_32_FLOAT                            = 0x23,
+       FMT_RESERVED_36                                  = 0x24,
+       FMT_1                                            = 0x25,
+       FMT_1_REVERSED                                   = 0x26,
+       FMT_GB_GR                                        = 0x27,
+       FMT_BG_RG                                        = 0x28,
+       FMT_32_AS_8                                      = 0x29,
+       FMT_32_AS_8_8                                    = 0x2a,
+       FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
+       FMT_8_8_8                                        = 0x2c,
+       FMT_16_16_16                                     = 0x2d,
+       FMT_16_16_16_FLOAT                               = 0x2e,
+       FMT_4_4                                          = 0x2f,
+       FMT_32_32_32_FLOAT                               = 0x30,
+       FMT_BC1                                          = 0x31,
+       FMT_BC2                                          = 0x32,
+       FMT_BC3                                          = 0x33,
+       FMT_BC4                                          = 0x34,
+       FMT_BC5                                          = 0x35,
+       FMT_BC6                                          = 0x36,
+       FMT_BC7                                          = 0x37,
+       FMT_32_AS_32_32_32_32                            = 0x38,
+       FMT_APC3                                         = 0x39,
+       FMT_APC4                                         = 0x3a,
+       FMT_APC5                                         = 0x3b,
+       FMT_APC6                                         = 0x3c,
+       FMT_APC7                                         = 0x3d,
+       FMT_CTX1                                         = 0x3e,
+       FMT_RESERVED_63                                  = 0x3f,
+} SurfaceFormat;
+typedef enum BUF_DATA_FORMAT {
+       BUF_DATA_FORMAT_INVALID                          = 0x0,
+       BUF_DATA_FORMAT_8                                = 0x1,
+       BUF_DATA_FORMAT_16                               = 0x2,
+       BUF_DATA_FORMAT_8_8                              = 0x3,
+       BUF_DATA_FORMAT_32                               = 0x4,
+       BUF_DATA_FORMAT_16_16                            = 0x5,
+       BUF_DATA_FORMAT_10_11_11                         = 0x6,
+       BUF_DATA_FORMAT_11_11_10                         = 0x7,
+       BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
+       BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
+       BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
+       BUF_DATA_FORMAT_32_32                            = 0xb,
+       BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
+       BUF_DATA_FORMAT_32_32_32                         = 0xd,
+       BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
+       BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
+} BUF_DATA_FORMAT;
+typedef enum IMG_DATA_FORMAT {
+       IMG_DATA_FORMAT_INVALID                          = 0x0,
+       IMG_DATA_FORMAT_8                                = 0x1,
+       IMG_DATA_FORMAT_16                               = 0x2,
+       IMG_DATA_FORMAT_8_8                              = 0x3,
+       IMG_DATA_FORMAT_32                               = 0x4,
+       IMG_DATA_FORMAT_16_16                            = 0x5,
+       IMG_DATA_FORMAT_10_11_11                         = 0x6,
+       IMG_DATA_FORMAT_11_11_10                         = 0x7,
+       IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
+       IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
+       IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
+       IMG_DATA_FORMAT_32_32                            = 0xb,
+       IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
+       IMG_DATA_FORMAT_32_32_32                         = 0xd,
+       IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
+       IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
+       IMG_DATA_FORMAT_5_6_5                            = 0x10,
+       IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
+       IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
+       IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
+       IMG_DATA_FORMAT_8_24                             = 0x14,
+       IMG_DATA_FORMAT_24_8                             = 0x15,
+       IMG_DATA_FORMAT_X24_8_32                         = 0x16,
+       IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
+       IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
+       IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
+       IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
+       IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
+       IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
+       IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
+       IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
+       IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
+       IMG_DATA_FORMAT_GB_GR                            = 0x20,
+       IMG_DATA_FORMAT_BG_RG                            = 0x21,
+       IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
+       IMG_DATA_FORMAT_BC1                              = 0x23,
+       IMG_DATA_FORMAT_BC2                              = 0x24,
+       IMG_DATA_FORMAT_BC3                              = 0x25,
+       IMG_DATA_FORMAT_BC4                              = 0x26,
+       IMG_DATA_FORMAT_BC5                              = 0x27,
+       IMG_DATA_FORMAT_BC6                              = 0x28,
+       IMG_DATA_FORMAT_BC7                              = 0x29,
+       IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
+       IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
+       IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
+       IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
+       IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
+       IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
+       IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
+       IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
+       IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
+       IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
+       IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
+       IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
+       IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
+       IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
+       IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
+       IMG_DATA_FORMAT_4_4                              = 0x39,
+       IMG_DATA_FORMAT_6_5_5                            = 0x3a,
+       IMG_DATA_FORMAT_1                                = 0x3b,
+       IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
+       IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
+       IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
+       IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
+} IMG_DATA_FORMAT;
+typedef enum BUF_NUM_FORMAT {
+       BUF_NUM_FORMAT_UNORM                             = 0x0,
+       BUF_NUM_FORMAT_SNORM                             = 0x1,
+       BUF_NUM_FORMAT_USCALED                           = 0x2,
+       BUF_NUM_FORMAT_SSCALED                           = 0x3,
+       BUF_NUM_FORMAT_UINT                              = 0x4,
+       BUF_NUM_FORMAT_SINT                              = 0x5,
+       BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
+       BUF_NUM_FORMAT_FLOAT                             = 0x7,
+} BUF_NUM_FORMAT;
+typedef enum IMG_NUM_FORMAT {
+       IMG_NUM_FORMAT_UNORM                             = 0x0,
+       IMG_NUM_FORMAT_SNORM                             = 0x1,
+       IMG_NUM_FORMAT_USCALED                           = 0x2,
+       IMG_NUM_FORMAT_SSCALED                           = 0x3,
+       IMG_NUM_FORMAT_UINT                              = 0x4,
+       IMG_NUM_FORMAT_SINT                              = 0x5,
+       IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
+       IMG_NUM_FORMAT_FLOAT                             = 0x7,
+       IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
+       IMG_NUM_FORMAT_SRGB                              = 0x9,
+       IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
+       IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
+       IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
+       IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
+       IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
+       IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
+} IMG_NUM_FORMAT;
+typedef enum TileType {
+       ARRAY_COLOR_TILE                                 = 0x0,
+       ARRAY_DEPTH_TILE                                 = 0x1,
+} TileType;
+typedef enum NonDispTilingOrder {
+       ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
+       ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
+} NonDispTilingOrder;
+typedef enum MicroTileMode {
+       ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
+       ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
+       ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
+       ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
+       ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
+} MicroTileMode;
+typedef enum TileSplit {
+       ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
+       ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
+       ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
+       ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
+       ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
+       ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
+       ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
+} TileSplit;
+typedef enum SampleSplit {
+       ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
+       ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
+       ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
+       ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
+} SampleSplit;
+typedef enum PipeConfig {
+       ADDR_SURF_P2                                     = 0x0,
+       ADDR_SURF_P2_RESERVED0                           = 0x1,
+       ADDR_SURF_P2_RESERVED1                           = 0x2,
+       ADDR_SURF_P2_RESERVED2                           = 0x3,
+       ADDR_SURF_P4_8x16                                = 0x4,
+       ADDR_SURF_P4_16x16                               = 0x5,
+       ADDR_SURF_P4_16x32                               = 0x6,
+       ADDR_SURF_P4_32x32                               = 0x7,
+       ADDR_SURF_P8_16x16_8x16                          = 0x8,
+       ADDR_SURF_P8_16x32_8x16                          = 0x9,
+       ADDR_SURF_P8_32x32_8x16                          = 0xa,
+       ADDR_SURF_P8_16x32_16x16                         = 0xb,
+       ADDR_SURF_P8_32x32_16x16                         = 0xc,
+       ADDR_SURF_P8_32x32_16x32                         = 0xd,
+       ADDR_SURF_P8_32x64_32x32                         = 0xe,
+       ADDR_SURF_P8_RESERVED0                           = 0xf,
+       ADDR_SURF_P16_32x32_8x16                         = 0x10,
+       ADDR_SURF_P16_32x32_16x16                        = 0x11,
+} PipeConfig;
+typedef enum NumBanks {
+       ADDR_SURF_2_BANK                                 = 0x0,
+       ADDR_SURF_4_BANK                                 = 0x1,
+       ADDR_SURF_8_BANK                                 = 0x2,
+       ADDR_SURF_16_BANK                                = 0x3,
+} NumBanks;
+typedef enum BankWidth {
+       ADDR_SURF_BANK_WIDTH_1                           = 0x0,
+       ADDR_SURF_BANK_WIDTH_2                           = 0x1,
+       ADDR_SURF_BANK_WIDTH_4                           = 0x2,
+       ADDR_SURF_BANK_WIDTH_8                           = 0x3,
+} BankWidth;
+typedef enum BankHeight {
+       ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
+       ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
+       ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
+       ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
+} BankHeight;
+typedef enum BankWidthHeight {
+       ADDR_SURF_BANK_WH_1                              = 0x0,
+       ADDR_SURF_BANK_WH_2                              = 0x1,
+       ADDR_SURF_BANK_WH_4                              = 0x2,
+       ADDR_SURF_BANK_WH_8                              = 0x3,
+} BankWidthHeight;
+typedef enum MacroTileAspect {
+       ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
+       ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
+       ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
+       ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
+} MacroTileAspect;
+typedef enum GATCL1RequestType {
+       GATCL1_TYPE_NORMAL                               = 0x0,
+       GATCL1_TYPE_SHOOTDOWN                            = 0x1,
+       GATCL1_TYPE_BYPASS                               = 0x2,
+} GATCL1RequestType;
+typedef enum TCC_CACHE_POLICIES {
+       TCC_CACHE_POLICY_LRU                             = 0x0,
+       TCC_CACHE_POLICY_STREAM                          = 0x1,
+} TCC_CACHE_POLICIES;
+typedef enum MTYPE {
+       MTYPE_NC_NV                                      = 0x0,
+       MTYPE_NC                                         = 0x1,
+       MTYPE_CC                                         = 0x2,
+       MTYPE_UC                                         = 0x3,
+} MTYPE;
+typedef enum PERFMON_COUNTER_MODE {
+       PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
+       PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
+       PERFMON_COUNTER_MODE_MAX                         = 0x2,
+       PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
+       PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
+       PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
+       PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
+       PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
+       PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
+       PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
+       PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
+} PERFMON_COUNTER_MODE;
+typedef enum PERFMON_SPM_MODE {
+       PERFMON_SPM_MODE_OFF                             = 0x0,
+       PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
+       PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
+       PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
+       PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
+       PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
+       PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
+       PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
+       PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
+       PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
+       PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
+} PERFMON_SPM_MODE;
+typedef enum SurfaceTiling {
+       ARRAY_LINEAR                                     = 0x0,
+       ARRAY_TILED                                      = 0x1,
+} SurfaceTiling;
+typedef enum SurfaceArray {
+       ARRAY_1D                                         = 0x0,
+       ARRAY_2D                                         = 0x1,
+       ARRAY_3D                                         = 0x2,
+       ARRAY_3D_SLICE                                   = 0x3,
+} SurfaceArray;
+typedef enum ColorArray {
+       ARRAY_2D_ALT_COLOR                               = 0x0,
+       ARRAY_2D_COLOR                                   = 0x1,
+       ARRAY_3D_SLICE_COLOR                             = 0x3,
+} ColorArray;
+typedef enum DepthArray {
+       ARRAY_2D_ALT_DEPTH                               = 0x0,
+       ARRAY_2D_DEPTH                                   = 0x1,
+} DepthArray;
+typedef enum ENUM_NUM_SIMD_PER_CU {
+       NUM_SIMD_PER_CU                                  = 0x4,
+} ENUM_NUM_SIMD_PER_CU;
+typedef enum MEM_PWR_FORCE_CTRL {
+       NO_FORCE_REQUEST                                 = 0x0,
+       FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
+       FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
+       FORCE_SHUT_DOWN_REQUEST                          = 0x3,
+} MEM_PWR_FORCE_CTRL;
+typedef enum MEM_PWR_FORCE_CTRL2 {
+       NO_FORCE_REQ                                     = 0x0,
+       FORCE_LIGHT_SLEEP_REQ                            = 0x1,
+} MEM_PWR_FORCE_CTRL2;
+typedef enum MEM_PWR_DIS_CTRL {
+       ENABLE_MEM_PWR_CTRL                              = 0x0,
+       DISABLE_MEM_PWR_CTRL                             = 0x1,
+} MEM_PWR_DIS_CTRL;
+typedef enum MEM_PWR_SEL_CTRL {
+       DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
+       DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
+       DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
+} MEM_PWR_SEL_CTRL;
+typedef enum MEM_PWR_SEL_CTRL2 {
+       DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
+       DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
+} MEM_PWR_SEL_CTRL2;
+
+#endif /* GFX_8_0_ENUM_H */

diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
new file mode 100644 (file)
index 0000000..7d72245
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
@@ -0,0 +1,20776 @@
+/*
+ * GFX_8_0 Register documentation
+ *
+ * Copyright (C) 2014  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GFX_8_0_SH_MASK_H
+#define GFX_8_0_SH_MASK_H
+
+#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
+#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
+#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
+#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
+#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
+#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
+#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
+#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
+#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
+#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
+#define CB_COLOR_CONTROL__MODE_MASK 0x70
+#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
+#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
+#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
+#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
+#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
+#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
+#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
+#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
+#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
+#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
+#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
+#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
+#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
+#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
+#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
+#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
+#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
+#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
+#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
+#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
+#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
+#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
+#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
+#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
+#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
+#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
+#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
+#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
+#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
+#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
+#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
+#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
+#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
+#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
+#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
+#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
+#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
+#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
+#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
+#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
+#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
+#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
+#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
+#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
+#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
+#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
+#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
+#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
+#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
+#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
+#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
+#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
+#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
+#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
+#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
+#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
+#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
+#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
+#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
+#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
+#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
+#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
+#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
+#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
+#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
+#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
+#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
+#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
+#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
+#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
+#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
+#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
+#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
+#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
+#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
+#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
+#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
+#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
+#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
+#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
+#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
+#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
+#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
+#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
+#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
+#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
+#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
+#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
+#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
+#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
+#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
+#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
+#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
+#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
+#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
+#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
+#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
+#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
+#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
+#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
+#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
+#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
+#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
+#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
+#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
+#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
+#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
+#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
+#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
+#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
+#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
+#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
+#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
+#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
+#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
+#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
+#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
+#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
+#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
+#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
+#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
+#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
+#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
+#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
+#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
+#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
+#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
+#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
+#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
+#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
+#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
+#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
+#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
+#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
+#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
+#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
+#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
+#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
+#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
+#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
+#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
+#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
+#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
+#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
+#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
+#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
+#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
+#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
+#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
+#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
+#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
+#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
+#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
+#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
+#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
+#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
+#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
+#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
+#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
+#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
+#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
+#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
+#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
+#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
+#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
+#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
+#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
+#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
+#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
+#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
+#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
+#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
+#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
+#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
+#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
+#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
+#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
+#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
+#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
+#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
+#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
+#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
+#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
+#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
+#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
+#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
+#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
+#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
+#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
+#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
+#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
+#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
+#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
+#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
+#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
+#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
+#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
+#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
+#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
+#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
+#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
+#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
+#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
+#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
+#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
+#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
+#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
+#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
+#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
+#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
+#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
+#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
+#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
+#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
+#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
+#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
+#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
+#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
+#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
+#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
+#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
+#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
+#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
+#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
+#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
+#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
+#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
+#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
+#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
+#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
+#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
+#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
+#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
+#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
+#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
+#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
+#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
+#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
+#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
+#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
+#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
+#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
+#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
+#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
+#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
+#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
+#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
+#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
+#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
+#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
+#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
+#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
+#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
+#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
+#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
+#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
+#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
+#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
+#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
+#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
+#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
+#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
+#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
+#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
+#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
+#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
+#define CP_DFY_CNTL__POLICY_MASK 0x1
+#define CP_DFY_CNTL__POLICY__SHIFT 0x0
+#define CP_DFY_CNTL__MTYPE_MASK 0xc
+#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
+#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
+#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
+#define CP_DFY_CNTL__MODE_MASK 0x60000000
+#define CP_DFY_CNTL__MODE__SHIFT 0x1d
+#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
+#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
+#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
+#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
+#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
+#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
+#define CP_DFY_STAT__BUSY_MASK 0x80000000
+#define CP_DFY_STAT__BUSY__SHIFT 0x1f
+#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
+#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
+#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
+#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_0__DATA__SHIFT 0x0
+#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_1__DATA__SHIFT 0x0
+#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_2__DATA__SHIFT 0x0
+#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_3__DATA__SHIFT 0x0
+#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_4__DATA__SHIFT 0x0
+#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_5__DATA__SHIFT 0x0
+#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_6__DATA__SHIFT 0x0
+#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_7__DATA__SHIFT 0x0
+#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_8__DATA__SHIFT 0x0
+#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_9__DATA__SHIFT 0x0
+#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_10__DATA__SHIFT 0x0
+#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_11__DATA__SHIFT 0x0
+#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_12__DATA__SHIFT 0x0
+#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_13__DATA__SHIFT 0x0
+#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_14__DATA__SHIFT 0x0
+#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
+#define CP_DFY_DATA_15__DATA__SHIFT 0x0
+#define CP_DFY_CMD__OFFSET_MASK 0x1ff
+#define CP_DFY_CMD__OFFSET__SHIFT 0x0
+#define CP_DFY_CMD__SIZE_MASK 0xffff0000
+#define CP_DFY_CMD__SIZE__SHIFT 0x10
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
+#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
+#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
+#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
+#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
+#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
+#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
+#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB0_CNTL__MTYPE_MASK 0x18000
+#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
+#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
+#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB_CNTL__MTYPE_MASK 0x18000
+#define CP_RB_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
+#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
+#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB1_CNTL__MTYPE_MASK 0x18000
+#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
+#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
+#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
+#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
+#define CP_RB2_CNTL__MTYPE_MASK 0x18000
+#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
+#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
+#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
+#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
+#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
+#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
+#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
+#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
+#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
+#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
+#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
+#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
+#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
+#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
+#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
+#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
+#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
+#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
+#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
+#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
+#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
+#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
+#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
+#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
+#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
+#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
+#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
+#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
+#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
+#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
+#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
+#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
+#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
+#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
+#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
+#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
+#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
+#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
+#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
+#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
+#define CP_RB_VMID__RB0_VMID_MASK 0xf
+#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
+#define CP_RB_VMID__RB1_VMID_MASK 0xf00
+#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
+#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
+#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
+#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
+#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
+#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
+#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
+#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
+#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
+#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
+#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
+#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
+#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
+#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
+#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
+#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
+#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
+#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
+#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
+#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
+#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
+#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
+#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
+#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
+#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
+#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
+#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
+#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
+#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
+#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
+#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
+#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
+#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
+#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
+#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
+#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
+#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
+#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
+#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
+#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
+#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
+#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
+#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
+#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
+#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
+#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
+#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
+#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
+#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
+#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
+#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
+#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
+#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
+#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
+#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
+#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
+#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
+#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
+#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
+#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
+#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
+#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
+#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
+#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
+#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
+#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
+#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
+#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
+#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
+#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
+#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
+#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
+#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
+#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
+#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
+#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
+#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
+#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
+#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
+#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
+#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
+#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
+#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
+#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
+#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
+#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
+#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
+#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
+#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
+#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
+#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
+#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
+#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
+#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
+#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
+#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
+#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
+#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
+#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
+#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
+#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
+#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
+#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
+#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
+#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
+#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
+#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
+#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
+#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
+#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
+#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
+#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
+#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
+#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
+#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
+#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
+#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
+#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
+#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
+#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
+#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
+#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
+#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
+#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
+#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
+#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
+#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
+#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
+#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
+#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
+#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
+#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
+#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
+#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
+#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
+#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
+#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
+#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
+#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
+#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
+#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
+#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
+#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
+#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
+#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
+#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
+#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
+#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
+#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
+#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
+#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
+#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
+#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
+#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
+#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
+#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
+#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
+#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
+#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
+#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
+#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
+#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
+#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
+#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
+#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
+#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
+#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
+#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
+#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
+#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
+#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
+#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
+#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
+#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
+#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
+#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
+#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
+#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
+#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
+#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
+#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
+#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
+#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
+#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
+#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
+#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
+#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
+#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
+#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
+#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
+#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
+#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
+#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
+#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
+#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
+#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
+#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
+#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
+#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
+#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
+#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
+#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
+#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
+#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
+#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
+#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
+#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
+#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
+#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
+#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
+#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
+#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
+#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
+#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
+#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
+#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
+#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
+#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
+#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
+#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
+#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
+#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
+#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
+#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
+#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
+#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
+#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
+#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
+#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
+#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
+#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
+#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
+#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
+#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
+#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
+#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
+#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
+#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
+#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
+#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
+#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
+#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
+#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
+#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
+#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
+#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
+#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
+#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
+#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
+#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
+#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
+#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
+#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
+#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
+#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
+#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
+#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
+#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
+#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
+#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
+#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
+#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
+#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
+#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
+#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
+#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
+#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
+#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
+#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
+#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
+#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
+#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
+#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
+#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
+#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
+#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
+#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
+#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
+#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
+#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
+#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
+#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
+#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
+#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
+#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
+#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
+#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
+#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
+#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
+#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
+#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
+#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
+#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
+#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
+#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
+#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
+#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
+#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
+#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
+#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
+#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
+#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
+#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
+#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
+#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
+#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
+#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
+#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
+#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
+#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
+#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
+#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
+#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
+#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
+#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
+#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
+#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
+#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
+#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
+#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
+#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
+#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
+#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
+#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
+#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
+#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
+#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
+#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
+#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
+#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
+#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
+#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
+#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
+#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
+#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
+#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
+#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
+#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
+#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
+#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
+#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
+#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
+#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
+#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
+#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
+#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
+#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
+#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
+#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
+#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
+#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
+#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
+#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
+#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
+#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
+#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
+#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
+#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
+#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
+#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
+#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
+#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
+#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
+#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
+#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
+#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
+#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
+#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
+#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
+#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
+#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
+#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
+#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
+#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
+#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
+#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
+#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
+#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
+#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
+#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
+#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
+#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
+#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
+#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
+#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
+#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
+#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
+#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
+#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
+#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
+#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
+#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
+#define CP_APPEND_DATA__DATA_MASK 0xffffffff
+#define CP_APPEND_DATA__DATA__SHIFT 0x0
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
+#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
+#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
+#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
+#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
+#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
+#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
+#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
+#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
+#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
+#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
+#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
+#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
+#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
+#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
+#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
+#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
+#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
+#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
+#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
+#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
+#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
+#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
+#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
+#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
+#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
+#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
+#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
+#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
+#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
+#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
+#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
+#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
+#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
+#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
+#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
+#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
+#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
+#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
+#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
+#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
+#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
+#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
+#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
+#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
+#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
+#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
+#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
+#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
+#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
+#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
+#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
+#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
+#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
+#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
+#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
+#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
+#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
+#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
+#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
+#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
+#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
+#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
+#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
+#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
+#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
+#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
+#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
+#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
+#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
+#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
+#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
+#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
+#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
+#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
+#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
+#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
+#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
+#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
+#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
+#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
+#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
+#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
+#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
+#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
+#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
+#define CP_COHER_STATUS__MEID_MASK 0x3000000
+#define CP_COHER_STATUS__MEID__SHIFT 0x18
+#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
+#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
+#define CP_COHER_STATUS__STATUS_MASK 0x80000000
+#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
+#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
+#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
+#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
+#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
+#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
+#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
+#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
+#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
+#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
+#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
+#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
+#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
+#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
+#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
+#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
+#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
+#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
+#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
+#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
+#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
+#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
+#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
+#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
+#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
+#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
+#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
+#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
+#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
+#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
+#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
+#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
+#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
+#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
+#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
+#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
+#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
+#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
+#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
+#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
+#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
+#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
+#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
+#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
+#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
+#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
+#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
+#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
+#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
+#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
+#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
+#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
+#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
+#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
+#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
+#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
+#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
+#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
+#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
+#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
+#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
+#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
+#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
+#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
+#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
+#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
+#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
+#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
+#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
+#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
+#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
+#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
+#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
+#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
+#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
+#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
+#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
+#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
+#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
+#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
+#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
+#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
+#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
+#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
+#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
+#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
+#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
+#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
+#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
+#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
+#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
+#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
+#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
+#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
+#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
+#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
+#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
+#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
+#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
+#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
+#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
+#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
+#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
+#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
+#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
+#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
+#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
+#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
+#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
+#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
+#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
+#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
+#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
+#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
+#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
+#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
+#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
+#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
+#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
+#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
+#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
+#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
+#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
+#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
+#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
+#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
+#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
+#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
+#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
+#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
+#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
+#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
+#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
+#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
+#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
+#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
+#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
+#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
+#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
+#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
+#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
+#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
+#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
+#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
+#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
+#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
+#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
+#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
+#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
+#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
+#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
+#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
+#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
+#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
+#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
+#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
+#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
+#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
+#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
+#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
+#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
+#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
+#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
+#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
+#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
+#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
+#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
+#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
+#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
+#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
+#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
+#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
+#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
+#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
+#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
+#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
+#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
+#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
+#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
+#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
+#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
+#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
+#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
+#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
+#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
+#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
+#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
+#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
+#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
+#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
+#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
+#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
+#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
+#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
+#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
+#define CP_STAT__DC_BUSY_MASK 0x2000
+#define CP_STAT__DC_BUSY__SHIFT 0xd
+#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
+#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
+#define CP_STAT__PFP_BUSY_MASK 0x8000
+#define CP_STAT__PFP_BUSY__SHIFT 0xf
+#define CP_STAT__MEQ_BUSY_MASK 0x10000
+#define CP_STAT__MEQ_BUSY__SHIFT 0x10
+#define CP_STAT__ME_BUSY_MASK 0x20000
+#define CP_STAT__ME_BUSY__SHIFT 0x11
+#define CP_STAT__QUERY_BUSY_MASK 0x40000
+#define CP_STAT__QUERY_BUSY__SHIFT 0x12
+#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
+#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
+#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
+#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
+#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
+#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
+#define CP_STAT__DMA_BUSY_MASK 0x400000
+#define CP_STAT__DMA_BUSY__SHIFT 0x16
+#define CP_STAT__RCIU_BUSY_MASK 0x800000
+#define CP_STAT__RCIU_BUSY__SHIFT 0x17
+#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
+#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
+#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
+#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
+#define CP_STAT__CE_BUSY_MASK 0x4000000
+#define CP_STAT__CE_BUSY__SHIFT 0x1a
+#define CP_STAT__TCIU_BUSY_MASK 0x8000000
+#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
+#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
+#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
+#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
+#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
+#define CP_STAT__CP_BUSY_MASK 0x80000000
+#define CP_STAT__CP_BUSY__SHIFT 0x1f
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
+#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
+#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
+#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
+#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
+#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
+#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
+#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
+#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
+#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
+#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
+#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
+#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
+#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
+#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
+#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
+#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
+#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
+#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
+#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
+#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
+#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
+#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
+#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
+#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
+#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
+#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
+#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
+#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
+#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
+#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
+#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
+#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
+#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
+#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
+#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
+#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
+#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
+#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
+#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
+#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
+#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
+#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
+#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
+#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
+#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
+#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
+#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
+#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
+#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
+#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
+#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
+#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
+#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
+#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
+#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
+#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
+#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
+#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
+#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
+#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
+#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
+#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
+#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
+#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
+#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
+#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
+#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
+#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
+#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
+#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
+#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
+#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
+#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
+#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
+#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
+#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
+#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
+#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
+#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
+#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
+#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
+#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
+#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
+#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
+#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
+#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
+#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
+#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
+#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
+#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
+#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
+#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
+#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
+#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
+#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
+#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
+#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
+#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
+#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
+#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
+#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
+#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
+#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
+#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
+#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
+#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
+#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
+#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
+#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
+#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
+#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
+#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
+#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
+#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
+#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
+#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
+#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
+#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
+#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
+#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
+#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
+#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
+#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
+#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
+#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
+#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
+#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
+#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
+#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
+#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
+#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
+#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
+#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
+#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
+#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
+#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
+#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
+#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
+#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
+#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
+#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
+#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
+#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
+#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
+#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
+#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
+#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
+#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
+#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
+#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
+#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
+#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
+#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
+#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
+#define CP_RINGID__RINGID_MASK 0x3
+#define CP_RINGID__RINGID__SHIFT 0x0
+#define CP_PIPEID__PIPE_ID_MASK 0x3
+#define CP_PIPEID__PIPE_ID__SHIFT 0x0
+#define CP_VMID__VMID_MASK 0xf
+#define CP_VMID__VMID__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
+#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
+#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
+#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
+#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
+#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
+#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
+#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
+#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
+#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
+#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
+#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
+#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
+#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
+#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
+#define CP_HQD_VMID__VMID_MASK 0xf
+#define CP_HQD_VMID__VMID__SHIFT 0x0
+#define CP_HQD_VMID__IB_VMID_MASK 0xf00
+#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
+#define CP_HQD_VMID__VQID_MASK 0x3ff0000
+#define CP_HQD_VMID__VQID__SHIFT 0x10
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
+#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
+#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
+#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
+#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
+#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
+#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
+#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
+#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
+#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
+#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
+#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
+#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
+#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
+#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
+#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
+#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
+#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
+#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
+#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
+#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
+#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
+#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
+#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
+#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
+#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
+#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
+#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
+#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
+#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
+#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
+#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
+#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
+#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
+#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
+#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
+#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
+#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
+#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
+#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
+#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
+#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
+#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
+#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
+#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
+#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
+#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
+#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
+#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
+#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
+#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
+#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
+#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
+#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
+#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
+#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
+#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
+#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
+#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
+#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
+#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
+#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
+#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
+#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
+#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
+#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
+#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
+#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
+#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
+#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
+#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
+#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
+#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
+#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
+#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
+#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
+#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
+#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
+#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
+#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
+#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
+#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
+#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
+#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
+#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
+#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
+#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
+#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
+#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
+#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
+#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
+#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
+#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
+#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
+#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
+#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
+#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
+#define CP_MQD_CONTROL__VMID_MASK 0xf
+#define CP_MQD_CONTROL__VMID__SHIFT 0x0
+#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
+#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
+#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
+#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
+#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
+#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
+#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
+#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
+#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
+#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
+#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
+#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
+#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
+#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
+#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
+#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
+#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
+#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
+#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
+#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
+#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
+#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
+#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
+#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
+#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
+#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
+#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
+#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
+#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
+#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
+#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
+#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
+#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
+#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
+#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
+#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
+#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
+#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
+#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
+#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
+#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
+#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
+#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
+#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
+#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
+#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
+#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
+#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
+#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
+#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
+#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
+#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
+#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
+#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
+#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
+#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
+#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
+#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
+#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
+#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
+#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
+#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
+#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
+#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
+#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
+#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
+#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
+#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
+#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
+#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
+#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
+#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
+#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
+#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
+#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
+#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
+#define DB_Z_INFO__FORMAT_MASK 0x3
+#define DB_Z_INFO__FORMAT__SHIFT 0x0
+#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
+#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
+#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
+#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
+#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
+#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
+#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
+#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
+#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
+#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
+#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
+#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
+#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
+#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
+#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
+#define DB_STENCIL_INFO__FORMAT_MASK 0x1
+#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
+#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
+#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
+#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
+#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
+#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
+#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
+#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
+#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
+#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
+#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
+#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
+#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
+#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
+#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
+#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
+#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
+#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
+#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
+#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
+#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
+#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
+#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
+#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
+#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
+#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
+#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
+#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
+#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
+#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
+#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
+#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
+#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
+#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
+#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
+#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
+#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
+#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
+#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
+#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
+#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
+#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
+#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
+#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
+#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
+#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
+#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
+#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
+#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
+#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
+#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
+#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
+#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
+#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
+#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
+#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
+#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
+#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
+#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
+#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
+#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
+#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
+#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
+#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
+#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
+#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
+#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
+#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
+#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
+#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
+#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
+#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
+#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
+#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
+#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
+#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
+#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
+#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
+#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
+#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
+#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
+#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
+#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
+#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
+#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
+#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
+#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
+#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
+#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
+#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
+#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
+#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
+#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
+#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
+#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
+#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
+#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
+#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
+#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
+#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
+#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
+#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
+#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
+#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
+#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
+#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
+#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
+#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
+#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
+#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
+#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
+#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
+#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
+#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
+#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
+#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
+#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
+#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
+#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
+#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
+#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
+#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
+#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
+#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
+#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
+#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
+#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
+#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
+#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
+#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
+#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
+#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
+#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
+#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
+#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
+#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
+#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
+#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
+#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
+#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
+#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
+#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
+#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
+#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
+#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
+#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
+#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
+#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
+#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
+#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
+#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
+#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
+#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
+#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
+#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
+#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
+#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
+#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
+#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
+#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
+#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
+#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
+#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
+#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
+#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
+#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
+#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
+#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
+#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
+#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
+#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
+#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
+#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
+#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
+#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
+#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
+#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
+#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
+#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
+#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
+#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
+#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
+#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
+#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
+#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
+#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
+#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
+#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
+#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
+#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
+#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
+#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
+#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
+#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
+#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
+#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
+#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
+#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
+#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
+#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
+#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
+#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
+#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
+#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
+#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
+#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
+#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
+#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
+#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
+#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
+#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
+#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
+#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
+#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
+#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
+#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
+#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
+#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
+#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
+#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
+#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
+#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
+#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
+#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
+#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
+#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
+#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
+#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
+#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
+#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
+#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
+#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
+#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
+#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
+#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
+#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
+#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
+#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
+#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
+#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
+#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
+#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
+#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
+#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
+#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
+#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
+#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
+#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
+#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
+#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
+#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
+#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
+#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
+#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
+#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
+#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
+#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
+#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
+#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
+#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
+#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
+#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
+#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
+#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
+#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
+#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
+#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
+#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
+#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
+#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
+#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
+#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
+#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
+#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
+#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
+#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
+#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
+#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
+#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
+#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
+#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
+#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
+#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
+#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
+#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
+#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
+#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
+#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
+#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
+#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
+#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
+#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
+#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
+#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
+#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
+#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
+#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
+#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
+#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
+#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
+#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
+#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
+#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
+#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
+#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
+#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
+#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
+#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
+#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
+#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
+#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
+#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
+#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
+#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
+#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
+#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
+#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
+#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
+#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
+#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
+#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
+#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
+#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
+#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
+#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
+#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
+#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
+#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
+#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
+#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
+#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
+#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
+#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
+#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
+#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
+#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
+#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
+#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
+#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
+#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
+#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
+#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
+#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
+#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
+#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
+#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
+#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
+#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
+#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
+#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
+#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
+#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
+#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
+#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
+#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
+#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
+#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
+#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
+#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
+#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
+#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
+#define GB_GPU_ID__GPU_ID_MASK 0xf
+#define GB_GPU_ID__GPU_ID__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
+#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
+#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
+#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
+#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
+#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
+#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
+#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
+#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
+#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
+#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
+#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
+#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
+#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
+#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
+#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
+#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
+#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
+#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
+#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
+#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
+#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
+#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
+#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
+#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
+#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
+#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
+#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
+#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
+#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
+#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
+#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
+#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
+#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
+#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
+#define GB_EDC_MODE__DED_MODE_MASK 0x300000
+#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
+#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
+#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
+#define GB_EDC_MODE__BYPASS_MASK 0x80000000
+#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
+#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
+#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
+#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
+#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
+#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
+#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
+#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
+#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
+#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
+#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
+#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
+#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
+#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
+#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
+#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
+#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
+#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
+#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
+#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
+#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
+#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
+#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
+#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
+#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
+#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
+#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
+#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
+#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
+#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
+#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
+#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
+#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
+#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
+#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
+#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
+#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
+#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
+#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
+#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
+#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
+#define GRBM_STATUS__TA_BUSY_MASK 0x4000
+#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
+#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
+#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
+#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
+#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
+#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
+#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
+#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
+#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
+#define GRBM_STATUS__IA_BUSY_MASK 0x80000
+#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
+#define GRBM_STATUS__SX_BUSY_MASK 0x100000
+#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
+#define GRBM_STATUS__WD_BUSY_MASK 0x200000
+#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
+#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
+#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
+#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
+#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
+#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
+#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
+#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
+#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
+#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
+#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
+#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
+#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
+#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
+#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
+#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
+#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
+#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
+#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
+#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
+#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
+#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
+#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
+#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
+#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
+#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
+#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
+#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
+#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
+#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
+#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
+#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
+#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
+#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
+#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
+#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
+#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
+#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
+#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
+#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
+#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
+#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
+#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
+#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
+#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
+#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
+#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
+#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
+#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
+#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
+#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
+#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
+#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
+#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
+#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
+#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
+#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
+#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
+#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
+#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
+#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
+#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
+#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
+#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
+#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
+#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
+#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
+#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
+#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
+#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
+#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
+#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
+#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
+#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
+#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
+#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
+#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
+#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
+#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
+#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
+#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
+#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
+#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
+#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
+#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
+#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
+#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
+#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
+#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
+#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
+#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
+#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
+#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
+#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
+#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
+#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
+#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
+#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
+#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
+#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
+#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
+#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
+#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
+#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
+#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
+#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
+#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
+#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
+#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
+#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
+#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
+#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
+#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
+#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
+#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
+#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
+#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
+#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
+#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
+#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
+#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
+#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
+#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
+#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
+#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
+#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
+#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
+#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
+#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
+#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
+#define GRBM_TRAP_OP__RW_MASK 0x1
+#define GRBM_TRAP_OP__RW__SHIFT 0x0
+#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
+#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
+#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
+#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
+#define GRBM_TRAP_WD__DATA__SHIFT 0x0
+#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
+#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
+#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
+#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
+#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
+#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
+#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
+#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
+#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
+#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
+#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
+#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
+#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
+#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
+#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
+#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
+#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
+#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
+#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
+#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
+#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
+#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
+#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
+#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
+#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
+#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
+#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
+#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
+#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
+#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
+#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
+#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
+#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
+#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
+#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
+#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
+#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
+#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
+#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
+#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
+#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
+#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
+#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
+#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
+#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
+#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
+#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
+#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
+#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
+#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
+#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
+#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
+#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
+#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
+#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
+#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
+#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
+#define GRBM_NOWHERE__DATA_MASK 0xffffffff
+#define GRBM_NOWHERE__DATA__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
+#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
+#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
+#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
+#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
+#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
+#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
+#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
+#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
+#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
+#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
+#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
+#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
+#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
+#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
+#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
+#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
+#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
+#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
+#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
+#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
+#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
+#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
+#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
+#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
+#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
+#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
+#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
+#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
+#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
+#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
+#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
+#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
+#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
+#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
+#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
+#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
+#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
+#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
+#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
+#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
+#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
+#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
+#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
+#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
+#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
+#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
+#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
+#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
+#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
+#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
+#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
+#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
+#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
+#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
+#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
+#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
+#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
+#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
+#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
+#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
+#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
+#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
+#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
+#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
+#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
+#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
+#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
+#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
+#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
+#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
+#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
+#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
+#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
+#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
+#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
+#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
+#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
+#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
+#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
+#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
+#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
+#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
+#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
+#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
+#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
+#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
+#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
+#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
+#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
+#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
+#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
+#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
+#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
+#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
+#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
+#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
+#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
+#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
+#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
+#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
+#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
+#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
+#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
+#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
+#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
+#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
+#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
+#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
+#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
+#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
+#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
+#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
+#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
+#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
+#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
+#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
+#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
+#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
+#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
+#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
+#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
+#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
+#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
+#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
+#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
+#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
+#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
+#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
+#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
+#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
+#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
+#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
+#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
+#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
+#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
+#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
+#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
+#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
+#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
+#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
+#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
+#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
+#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
+#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
+#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
+#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
+#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
+#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
+#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
+#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
+#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
+#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
+#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
+#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
+#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
+#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
+#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
+#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
+#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
+#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
+#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
+#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
+#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
+#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
+#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
+#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
+#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
+#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
+#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
+#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
+#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
+#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
+#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
+#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
+#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
+#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
+#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
+#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
+#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
+#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
+#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
+#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
+#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
+#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
+#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
+#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
+#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
+#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
+#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
+#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
+#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
+#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
+#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
+#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
+#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
+#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
+#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
+#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
+#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
+#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
+#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
+#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
+#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
+#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
+#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
+#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
+#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
+#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
+#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
+#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
+#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
+#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
+#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
+#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
+#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
+#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
+#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
+#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
+#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
+#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
+#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
+#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
+#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
+#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
+#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
+#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
+#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
+#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
+#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
+#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
+#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
+#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
+#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
+#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
+#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
+#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
+#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
+#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
+#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
+#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
+#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
+#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
+#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
+#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
+#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
+#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
+#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
+#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
+#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
+#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
+#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
+#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
+#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
+#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
+#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
+#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
+#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
+#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
+#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
+#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
+#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
+#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
+#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
+#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
+#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
+#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
+#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
+#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
+#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
+#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
+#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
+#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
+#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
+#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
+#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
+#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
+#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
+#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
+#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
+#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
+#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
+#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
+#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
+#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
+#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
+#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
+#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
+#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
+#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
+#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
+#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
+#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
+#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
+#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
+#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
+#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
+#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
+#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
+#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
+#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
+#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
+#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
+#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
+#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
+#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
+#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
+#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
+#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
+#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
+#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
+#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
+#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
+#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
+#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
+#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
+#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
+#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
+#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
+#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
+#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
+#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
+#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
+#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
+#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
+#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
+#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
+#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
+#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
+#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
+#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
+#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
+#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
+#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
+#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
+#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
+#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
+#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
+#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
+#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
+#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
+#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
+#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
+#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
+#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
+#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
+#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
+#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
+#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
+#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
+#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
+#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
+#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
+#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
+#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
+#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
+#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
+#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
+#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
+#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
+#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
+#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
+#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
+#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
+#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
+#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
+#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
+#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
+#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
+#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
+#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
+#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
+#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
+#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
+#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
+#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
+#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
+#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
+#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
+#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
+#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
+#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
+#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
+#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
+#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
+#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
+#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
+#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
+#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
+#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
+#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
+#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
+#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
+#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
+#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
+#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
+#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
+#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
+#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
+#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
+#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
+#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
+#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
+#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
+#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
+#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
+#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
+#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
+#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
+#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
+#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
+#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
+#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
+#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
+#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
+#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
+#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
+#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
+#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
+#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
+#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
+#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
+#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
+#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
+#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
+#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
+#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
+#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
+#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
+#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
+#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
+#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
+#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
+#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
+#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
+#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
+#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
+#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
+#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
+#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
+#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
+#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
+#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
+#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
+#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
+#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
+#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
+#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
+#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
+#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
+#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
+#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
+#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
+#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
+#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
+#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
+#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
+#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
+#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
+#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
+#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
+#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
+#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
+#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
+#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
+#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
+#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
+#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
+#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
+#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
+#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
+#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
+#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
+#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
+#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
+#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
+#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
+#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
+#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
+#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
+#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
+#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
+#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
+#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
+#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
+#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
+#define COMPUTE_START_X__START_MASK 0xffffffff
+#define COMPUTE_START_X__START__SHIFT 0x0
+#define COMPUTE_START_Y__START_MASK 0xffffffff
+#define COMPUTE_START_Y__START__SHIFT 0x0
+#define COMPUTE_START_Z__START_MASK 0xffffffff
+#define COMPUTE_START_Z__START__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
+#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
+#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
+#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
+#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
+#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__DATA_MASK 0xff
+#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
+#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
+#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
+#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
+#define COMPUTE_TBA_HI__DATA_MASK 0xff
+#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
+#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
+#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
+#define COMPUTE_TMA_HI__DATA_MASK 0xff
+#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
+#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
+#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
+#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
+#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
+#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
+#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
+#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
+#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
+#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
+#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
+#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
+#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
+#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
+#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
+#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
+#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
+#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
+#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
+#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
+#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
+#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
+#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
+#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
+#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
+#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
+#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
+#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
+#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
+#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
+#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
+#define COMPUTE_VMID__DATA_MASK 0xf
+#define COMPUTE_VMID__DATA__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
+#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
+#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
+#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
+#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
+#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
+#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
+#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
+#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
+#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
+#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
+#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
+#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
+#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
+#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
+#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
+#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
+#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
+#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
+#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
+#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
+#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
+#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
+#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
+#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
+#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
+#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
+#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
+#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
+#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
+#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
+#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
+#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
+#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
+#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
+#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
+#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
+#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
+#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
+#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
+#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
+#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
+#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
+#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
+#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
+#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
+#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
+#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
+#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
+#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
+#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
+#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
+#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
+#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
+#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
+#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
+#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
+#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
+#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
+#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
+#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
+#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
+#define RLC_CNTL__FORCE_RETRY_MASK 0x2
+#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
+#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
+#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
+#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
+#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
+#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
+#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
+#define RLC_CNTL__RESERVED_MASK 0xffffff00
+#define RLC_CNTL__RESERVED__SHIFT 0x8
+#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
+#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_DEBUG__DATA_MASK 0xffffffff
+#define RLC_DEBUG__DATA__SHIFT 0x0
+#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
+#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
+#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
+#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
+#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
+#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
+#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
+#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
+#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
+#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
+#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
+#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
+#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
+#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
+#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
+#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
+#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
+#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
+#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
+#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
+#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
+#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
+#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
+#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
+#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
+#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
+#define RLC_STAT__RLC_BUSY_MASK 0x1
+#define RLC_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
+#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
+#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
+#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
+#define RLC_STAT__RESERVED_MASK 0xfffffff8
+#define RLC_STAT__RESERVED__SHIFT 0x3
+#define RLC_SAFE_MODE__CMD_MASK 0x1
+#define RLC_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
+#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
+#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
+#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
+#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
+#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
+#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
+#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
+#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
+#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
+#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
+#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
+#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
+#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
+#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
+#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
+#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
+#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
+#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
+#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
+#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
+#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
+#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
+#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
+#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
+#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
+#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
+#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
+#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
+#define RLC_RLCV_COMMAND__CMD_MASK 0xf
+#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
+#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
+#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
+#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
+#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
+#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
+#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
+#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
+#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
+#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
+#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
+#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
+#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
+#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
+#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
+#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
+#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
+#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
+#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
+#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
+#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
+#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
+#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
+#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
+#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
+#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
+#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
+#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
+#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
+#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
+#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
+#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
+#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
+#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
+#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
+#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
+#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
+#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
+#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
+#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
+#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
+#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
+#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
+#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
+#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
+#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
+#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
+#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
+#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
+#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
+#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
+#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
+#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
+#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
+#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
+#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
+#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
+#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
+#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
+#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
+#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
+#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
+#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
+#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
+#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
+#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
+#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
+#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
+#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
+#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
+#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
+#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
+#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
+#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
+#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
+#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
+#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
+#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
+#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
+#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
+#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
+#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000
+#define RLC_GPM_STAT__RESERVED__SHIFT 0x12
+#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
+#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
+#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
+#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
+#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
+#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
+#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
+#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
+#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
+#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
+#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
+#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
+#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
+#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
+#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
+#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
+#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
+#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
+#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
+#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000
+#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
+#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
+#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
+#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
+#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
+#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
+#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
+#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
+#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
+#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
+#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
+#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
+#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
+#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
+#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
+#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
+#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
+#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
+#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
+#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
+#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
+#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
+#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
+#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
+#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
+#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
+#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
+#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
+#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
+#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
+#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
+#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
+#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
+#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
+#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
+#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
+#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
+#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
+#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
+#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
+#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
+#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
+#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
+#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
+#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
+#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
+#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
+#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
+#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
+#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
+#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
+#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
+#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
+#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
+#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
+#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
+#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
+#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
+#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
+#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
+#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
+#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
+#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
+#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
+#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
+#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
+#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
+#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
+#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
+#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
+#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
+#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
+#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
+#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
+#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
+#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
+#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
+#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
+#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
+#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
+#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
+#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
+#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
+#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
+#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
+#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
+#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
+#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
+#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
+#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
+#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
+#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
+#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
+#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
+#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
+#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
+#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
+#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
+#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
+#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
+#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
+#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
+#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
+#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
+#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
+#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
+#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
+#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
+#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
+#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
+#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
+#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
+#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
+#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
+#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
+#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
+#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
+#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
+#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
+#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
+#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
+#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
+#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
+#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
+#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
+#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
+#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
+#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
+#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
+#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
+#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
+#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
+#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
+#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
+#define RLC_GPR_REG1__DATA_MASK 0xffffffff
+#define RLC_GPR_REG1__DATA__SHIFT 0x0
+#define RLC_GPR_REG2__DATA_MASK 0xffffffff
+#define RLC_GPR_REG2__DATA__SHIFT 0x0
+#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
+#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
+#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
+#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
+#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
+#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
+#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
+#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
+#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
+#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
+#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
+#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
+#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
+#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
+#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
+#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
+#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
+#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
+#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
+#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
+#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
+#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
+#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
+#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
+#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
+#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
+#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
+#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
+#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
+#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
+#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
+#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
+#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
+#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
+#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
+#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
+#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
+#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
+#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
+#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
+#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00
+#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
+#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
+#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
+#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
+#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
+#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
+#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
+#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
+#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
+#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
+#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
+#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
+#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
+#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
+#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
+#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
+#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff
+#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00
+#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa
+#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
+#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff
+#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
+#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
+#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
+#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
+#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
+#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
+#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
+#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
+#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
+#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
+#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
+#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
+#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
+#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
+#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
+#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
+#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
+#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
+#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
+#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
+#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
+#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
+#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
+#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
+#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
+#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
+#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
+#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
+#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
+#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
+#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
+#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
+#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
+#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
+#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
+#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
+#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
+#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
+#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
+#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
+#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
+#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
+#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
+#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
+#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
+#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
+#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
+#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
+#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
+#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
+#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
+#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
+#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
+#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
+#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
+#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
+#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
+#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
+#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
+#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
+#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
+#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
+#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
+#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
+#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
+#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
+#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
+#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
+#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
+#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
+#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
+#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
+#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
+#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
+#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf
+#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20
+#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
+#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0
+#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf
+#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0
+#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
+#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300
+#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00
+#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff
+#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00
+#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000
+#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff
+#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000
+#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff
+#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000
+#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
+#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
+#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf
+#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0
+#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0
+#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4
+#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700
+#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8
+#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800
+#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
+#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000
+#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff
+#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
+#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1
+#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
+#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe
+#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1
+#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
+#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe
+#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100
+#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000
+#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000
+#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100
+#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000
+#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000
+#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff
+#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff
+#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000
+#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000
+#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
+#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff
+#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
+#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff
+#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
+#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
+#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0
+#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff
+#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
+#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
+#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
+#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
+#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
+#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
+#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
+#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
+#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
+#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
+#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
+#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
+#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
+#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
+#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
+#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
+#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
+#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
+#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
+#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
+#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
+#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
+#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
+#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
+#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
+#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
+#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
+#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
+#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
+#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
+#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
+#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
+#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
+#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
+#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
+#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
+#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
+#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
+#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
+#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
+#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
+#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
+#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
+#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
+#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
+#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
+#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
+#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
+#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
+#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
+#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
+#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
+#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
+#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
+#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
+#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
+#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
+#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
+#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
+#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
+#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
+#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
+#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
+#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
+#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
+#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
+#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
+#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
+#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
+#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
+#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
+#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
+#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
+#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
+#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
+#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
+#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
+#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
+#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
+#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
+#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
+#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
+#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
+#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
+#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
+#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
+#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
+#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
+#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
+#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
+#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
+#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
+#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
+#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
+#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
+#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
+#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
+#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
+#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
+#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
+#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
+#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
+#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
+#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
+#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
+#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
+#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
+#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
+#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
+#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
+#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
+#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
+#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
+#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
+#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
+#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
+#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
+#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
+#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
+#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
+#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
+#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
+#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
+#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
+#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
+#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
+#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
+#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
+#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
+#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
+#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
+#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
+#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
+#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
+#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
+#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
+#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
+#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
+#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
+#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
+#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
+#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
+#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
+#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
+#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
+#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
+#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
+#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
+#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
+#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
+#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
+#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
+#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
+#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
+#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
+#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
+#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
+#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe
+#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000
+#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000
+#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4
+#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000
+#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000
+#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3
+#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
+#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc
+#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
+#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30
+#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
+#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1
+#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
+#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
+#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
+#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
+#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
+#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
+#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
+#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
+#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
+#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
+#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
+#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
+#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
+#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
+#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
+#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
+#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
+#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
+#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
+#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
+#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
+#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
+#define SPI_DEBUG_READ__DATA_MASK 0xffffff
+#define SPI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2
+#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1
+#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4
+#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2
+#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8
+#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
+#define SPI_EDC_CNT__SED_MASK 0xff
+#define SPI_EDC_CNT__SED__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
+#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
+#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
+#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
+#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
+#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
+#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
+#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
+#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
+#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
+#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
+#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
+#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
+#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
+#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
+#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
+#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
+#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
+#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
+#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
+#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
+#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
+#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
+#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
+#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
+#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
+#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
+#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
+#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
+#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
+#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
+#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
+#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
+#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
+#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
+#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
+#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
+#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
+#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
+#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
+#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
+#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
+#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
+#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
+#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
+#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
+#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
+#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
+#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
+#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
+#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
+#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
+#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
+#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
+#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
+#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
+#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
+#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
+#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0
+#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
+#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
+#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
+#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
+#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
+#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
+#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
+#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
+#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
+#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
+#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
+#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
+#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
+#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
+#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
+#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
+#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
+#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
+#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
+#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
+#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
+#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
+#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
+#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
+#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
+#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
+#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
+#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
+#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
+#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
+#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
+#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
+#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
+#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
+#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
+#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
+#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
+#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
+#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
+#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
+#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
+#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
+#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
+#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
+#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
+#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
+#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
+#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
+#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
+#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
+#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
+#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
+#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
+#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
+#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
+#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
+#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
+#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
+#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
+#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
+#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
+#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
+#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
+#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
+#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
+#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
+#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
+#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
+#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
+#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
+#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
+#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
+#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
+#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
+#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000
+#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16
+#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
+#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
+#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
+#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
+#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
+#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
+#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
+#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
+#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
+#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
+#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
+#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
+#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
+#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
+#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
+#define BCI_DEBUG_READ__DATA_MASK 0xffffff
+#define BCI_DEBUG_READ__DATA__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
+#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
+#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
+#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
+#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
+#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
+#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
+#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
+#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
+#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
+#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
+#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
+#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
+#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
+#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
+#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
+#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
+#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
+#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
+#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
+#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
+#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000
+#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
+#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
+#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
+#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
+#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
+#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000
+#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
+#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
+#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
+#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
+#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
+#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00
+#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
+#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
+#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
+#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
+#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
+#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
+#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
+#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
+#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
+#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
+#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
+#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
+#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
+#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
+#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
+#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
+#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
+#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
+#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
+#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
+#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
+#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
+#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
+#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
+#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
+#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000
+#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
+#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
+#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
+#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
+#define SQ_CONFIG__UNUSED_MASK 0xff
+#define SQ_CONFIG__UNUSED__SHIFT 0x0
+#define SQ_CONFIG__DEBUG_EN_MASK 0x100
+#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
+#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200
+#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
+#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400
+#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
+#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
+#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
+#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
+#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000
+#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000
+#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000
+#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000
+#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
+#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000
+#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
+#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
+#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
+#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
+#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
+#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
+#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
+#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
+#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
+#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
+#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
+#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
+#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
+#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
+#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
+#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
+#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
+#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
+#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
+#define SQC_CONFIG__EVICT_LRU_MASK 0x3000
+#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
+#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000
+#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
+#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000
+#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
+#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000
+#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
+#define SQC_CACHES__TARGET_INST_MASK 0x1
+#define SQC_CACHES__TARGET_INST__SHIFT 0x0
+#define SQC_CACHES__TARGET_DATA_MASK 0x2
+#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
+#define SQC_CACHES__INVALIDATE_MASK 0x4
+#define SQC_CACHES__INVALIDATE__SHIFT 0x2
+#define SQC_CACHES__WRITEBACK_MASK 0x8
+#define SQC_CACHES__WRITEBACK__SHIFT 0x3
+#define SQC_CACHES__VOL_MASK 0x10
+#define SQC_CACHES__VOL__SHIFT 0x4
+#define SQC_CACHES__COMPLETE_MASK 0x10000
+#define SQC_CACHES__COMPLETE__SHIFT 0x10
+#define SQC_WRITEBACK__DWB_MASK 0x1
+#define SQC_WRITEBACK__DWB__SHIFT 0x0
+#define SQC_WRITEBACK__DIRTY_MASK 0x2
+#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000
+#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000
+#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000
+#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d
+#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
+#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
+#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
+#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
+#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
+#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
+#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
+#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
+#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
+#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
+#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
+#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
+#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
+#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
+#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
+#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
+#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
+#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
+#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
+#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
+#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
+#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2
+#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8
+#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200
+#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400
+#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000
+#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000
+#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000
+#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000
+#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
+#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
+#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
+#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
+#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
+#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
+#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
+#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
+#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
+#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
+#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
+#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
+#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
+#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
+#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
+#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
+#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
+#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
+#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
+#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
+#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
+#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
+#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
+#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
+#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
+#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
+#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
+#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
+#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
+#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
+#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
+#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
+#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
+#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
+#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
+#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
+#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
+#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
+#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
+#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
+#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
+#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
+#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
+#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
+#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
+#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff
+#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
+#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
+#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
+#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
+#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
+#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
+#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
+#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000
+#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
+#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
+#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
+#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
+#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
+#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
+#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
+#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
+#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
+#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
+#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
+#define SQ_TIME_HI__TIME_MASK 0xffffffff
+#define SQ_TIME_HI__TIME__SHIFT 0x0
+#define SQ_TIME_LO__TIME_MASK 0xffffffff
+#define SQ_TIME_LO__TIME__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
+#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
+#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
+#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
+#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
+#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
+#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
+#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
+#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
+#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
+#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
+#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
+#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
+#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
+#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
+#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
+#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
+#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
+#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
+#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
+#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
+#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
+#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
+#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
+#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
+#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
+#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
+#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
+#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
+#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
+#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
+#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
+#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
+#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
+#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
+#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
+#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
+#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
+#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
+#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
+#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff
+#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
+#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
+#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
+#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
+#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
+#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
+#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
+#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
+#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
+#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
+#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
+#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
+#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
+#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
+#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
+#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
+#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__START_MASK 0x1
+#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
+#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
+#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
+#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
+#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
+#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
+#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
+#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
+#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
+#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
+#define SQC_EDC_CNT__INST_SEC_MASK 0xff
+#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0
+#define SQC_EDC_CNT__INST_DED_MASK 0xff00
+#define SQC_EDC_CNT__INST_DED__SHIFT 0x8
+#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000
+#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10
+#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000
+#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18
+#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff
+#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
+#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00
+#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
+#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000
+#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
+#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff
+#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
+#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00
+#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
+#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000
+#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
+#define SQ_EDC_INFO__WAVE_ID_MASK 0xf
+#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
+#define SQ_EDC_INFO__SIMD_ID_MASK 0x30
+#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
+#define SQ_EDC_INFO__SOURCE_MASK 0x1c0
+#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
+#define SQ_EDC_INFO__VM_ID_MASK 0x1e00
+#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
+#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
+#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
+#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
+#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
+#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
+#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
+#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
+#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
+#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
+#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
+#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
+#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
+#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
+#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
+#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
+#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
+#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
+#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
+#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
+#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
+#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
+#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
+#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
+#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
+#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
+#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
+#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
+#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
+#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
+#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
+#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
+#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
+#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
+#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
+#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
+#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
+#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
+#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
+#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
+#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
+#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
+#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
+#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
+#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
+#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
+#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
+#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
+#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
+#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
+#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
+#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
+#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
+#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
+#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
+#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
+#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
+#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
+#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000
+#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000
+#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000
+#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000
+#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000
+#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff
+#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
+#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
+#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
+#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
+#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
+#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
+#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
+#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
+#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
+#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
+#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
+#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
+#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
+#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000
+#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
+#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
+#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
+#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
+#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
+#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
+#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
+#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
+#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
+#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
+#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
+#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
+#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
+#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
+#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
+#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000
+#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
+#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
+#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
+#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
+#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
+#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff
+#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000
+#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000
+#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000
+#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
+#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000
+#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
+#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
+#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
+#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
+#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
+#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
+#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
+#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
+#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
+#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
+#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
+#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
+#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
+#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
+#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
+#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
+#define SQ_IND_INDEX__INDEX__SHIFT 0x10
+#define SQ_CMD__CMD_MASK 0x7
+#define SQ_CMD__CMD__SHIFT 0x0
+#define SQ_CMD__MODE_MASK 0x70
+#define SQ_CMD__MODE__SHIFT 0x4
+#define SQ_CMD__CHECK_VMID_MASK 0x80
+#define SQ_CMD__CHECK_VMID__SHIFT 0x7
+#define SQ_CMD__DATA_MASK 0x700
+#define SQ_CMD__DATA__SHIFT 0x8
+#define SQ_CMD__WAVE_ID_MASK 0xf0000
+#define SQ_CMD__WAVE_ID__SHIFT 0x10
+#define SQ_CMD__SIMD_ID_MASK 0x300000
+#define SQ_CMD__SIMD_ID__SHIFT 0x14
+#define SQ_CMD__QUEUE_ID_MASK 0x7000000
+#define SQ_CMD__QUEUE_ID__SHIFT 0x18
+#define SQ_CMD__VM_ID_MASK 0xf0000000
+#define SQ_CMD__VM_ID__SHIFT 0x1c
+#define SQ_IND_DATA__DATA_MASK 0xffffffff
+#define SQ_IND_DATA__DATA__SHIFT 0x0
+#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
+#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
+#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
+#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
+#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
+#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
+#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
+#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
+#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
+#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
+#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
+#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
+#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
+#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
+#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
+#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
+#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
+#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
+#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
+#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
+#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
+#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
+#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000
+#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
+#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000
+#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
+#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000
+#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
+#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000
+#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
+#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000
+#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
+#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000
+#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000
+#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
+#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1
+#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
+#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2
+#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4
+#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
+#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0
+#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
+#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00
+#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8
+#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
+#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
+#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
+#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
+#define SQ_WAVE_STATUS__SCC_MASK 0x1
+#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
+#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
+#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
+#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18
+#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
+#define SQ_WAVE_STATUS__PRIV_MASK 0x20
+#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
+#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
+#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
+#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
+#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
+#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
+#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
+#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
+#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
+#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
+#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
+#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
+#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
+#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
+#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
+#define SQ_WAVE_STATUS__HALT_MASK 0x2000
+#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
+#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
+#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
+#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
+#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
+#define SQ_WAVE_STATUS__VALID_MASK 0x10000
+#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
+#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
+#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
+#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
+#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
+#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
+#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
+#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
+#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
+#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
+#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
+#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000
+#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
+#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
+#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
+#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
+#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
+#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
+#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
+#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
+#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
+#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
+#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
+#define SQ_WAVE_MODE__IEEE_MASK 0x200
+#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
+#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
+#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
+#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
+#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
+#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
+#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
+#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000
+#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
+#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
+#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
+#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
+#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
+#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
+#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
+#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400
+#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
+#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
+#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
+#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
+#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
+#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
+#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
+#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
+#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
+#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
+#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
+#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
+#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
+#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
+#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
+#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
+#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
+#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
+#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
+#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
+#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
+#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
+#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
+#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
+#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
+#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
+#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
+#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
+#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
+#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
+#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
+#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
+#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
+#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
+#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
+#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
+#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
+#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
+#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
+#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
+#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000
+#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
+#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000
+#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
+#define SQ_WAVE_M0__M0_MASK 0xffffffff
+#define SQ_WAVE_M0__M0__SHIFT 0x0
+#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
+#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
+#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
+#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
+#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
+#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
+#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
+#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
+#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0
+#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
+#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
+#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
+#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
+#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
+#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
+#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
+#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
+#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
+#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
+#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3
+#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
+#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4
+#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2
+#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18
+#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
+#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0
+#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5
+#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700
+#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8
+#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800
+#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
+#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
+#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800
+#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
+#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
+#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
+#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
+#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
+#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
+#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
+#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
+#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
+#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
+#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
+#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
+#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
+#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
+#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
+#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
+#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
+#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
+#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff
+#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff
+#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000
+#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
+#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000
+#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
+#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000
+#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
+#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000
+#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
+#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff
+#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0
+#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000
+#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000
+#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000
+#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17
+#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000
+#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000
+#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
+#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff
+#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0
+#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000
+#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10
+#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
+#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
+#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
+#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
+#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
+#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
+#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
+#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
+#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
+#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
+#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
+#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
+#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
+#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
+#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
+#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
+#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
+#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
+#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
+#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
+#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
+#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
+#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
+#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
+#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
+#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
+#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
+#define SQ_SOP2__SSRC0_MASK 0xff
+#define SQ_SOP2__SSRC0__SHIFT 0x0
+#define SQ_SOP2__SSRC1_MASK 0xff00
+#define SQ_SOP2__SSRC1__SHIFT 0x8
+#define SQ_SOP2__SDST_MASK 0x7f0000
+#define SQ_SOP2__SDST__SHIFT 0x10
+#define SQ_SOP2__OP_MASK 0x3f800000
+#define SQ_SOP2__OP__SHIFT 0x17
+#define SQ_SOP2__ENCODING_MASK 0xc0000000
+#define SQ_SOP2__ENCODING__SHIFT 0x1e
+#define SQ_VOP1__SRC0_MASK 0x1ff
+#define SQ_VOP1__SRC0__SHIFT 0x0
+#define SQ_VOP1__OP_MASK 0x1fe00
+#define SQ_VOP1__OP__SHIFT 0x9
+#define SQ_VOP1__VDST_MASK 0x1fe0000
+#define SQ_VOP1__VDST__SHIFT 0x11
+#define SQ_VOP1__ENCODING_MASK 0xfe000000
+#define SQ_VOP1__ENCODING__SHIFT 0x19
+#define SQ_MTBUF_1__VADDR_MASK 0xff
+#define SQ_MTBUF_1__VADDR__SHIFT 0x0
+#define SQ_MTBUF_1__VDATA_MASK 0xff00
+#define SQ_MTBUF_1__VDATA__SHIFT 0x8
+#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
+#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MTBUF_1__SLC_MASK 0x400000
+#define SQ_MTBUF_1__SLC__SHIFT 0x16
+#define SQ_MTBUF_1__TFE_MASK 0x800000
+#define SQ_MTBUF_1__TFE__SHIFT 0x17
+#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
+#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_EXP_1__VSRC0_MASK 0xff
+#define SQ_EXP_1__VSRC0__SHIFT 0x0
+#define SQ_EXP_1__VSRC1_MASK 0xff00
+#define SQ_EXP_1__VSRC1__SHIFT 0x8
+#define SQ_EXP_1__VSRC2_MASK 0xff0000
+#define SQ_EXP_1__VSRC2__SHIFT 0x10
+#define SQ_EXP_1__VSRC3_MASK 0xff000000
+#define SQ_EXP_1__VSRC3__SHIFT 0x18
+#define SQ_MUBUF_1__VADDR_MASK 0xff
+#define SQ_MUBUF_1__VADDR__SHIFT 0x0
+#define SQ_MUBUF_1__VDATA_MASK 0xff00
+#define SQ_MUBUF_1__VDATA__SHIFT 0x8
+#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
+#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
+#define SQ_MUBUF_1__TFE_MASK 0x800000
+#define SQ_MUBUF_1__TFE__SHIFT 0x17
+#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
+#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
+#define SQ_SMEM_1__OFFSET_MASK 0xfffff
+#define SQ_SMEM_1__OFFSET__SHIFT 0x0
+#define SQ_INST__ENCODING_MASK 0xffffffff
+#define SQ_INST__ENCODING__SHIFT 0x0
+#define SQ_EXP_0__EN_MASK 0xf
+#define SQ_EXP_0__EN__SHIFT 0x0
+#define SQ_EXP_0__TGT_MASK 0x3f0
+#define SQ_EXP_0__TGT__SHIFT 0x4
+#define SQ_EXP_0__COMPR_MASK 0x400
+#define SQ_EXP_0__COMPR__SHIFT 0xa
+#define SQ_EXP_0__DONE_MASK 0x800
+#define SQ_EXP_0__DONE__SHIFT 0xb
+#define SQ_EXP_0__VM_MASK 0x1000
+#define SQ_EXP_0__VM__SHIFT 0xc
+#define SQ_EXP_0__ENCODING_MASK 0xfc000000
+#define SQ_EXP_0__ENCODING__SHIFT 0x1a
+#define SQ_MUBUF_0__OFFSET_MASK 0xfff
+#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MUBUF_0__OFFEN_MASK 0x1000
+#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MUBUF_0__IDXEN_MASK 0x2000
+#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MUBUF_0__GLC_MASK 0x4000
+#define SQ_MUBUF_0__GLC__SHIFT 0xe
+#define SQ_MUBUF_0__LDS_MASK 0x10000
+#define SQ_MUBUF_0__LDS__SHIFT 0x10
+#define SQ_MUBUF_0__SLC_MASK 0x20000
+#define SQ_MUBUF_0__SLC__SHIFT 0x11
+#define SQ_MUBUF_0__OP_MASK 0x1fc0000
+#define SQ_MUBUF_0__OP__SHIFT 0x12
+#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
+#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP_SDWA__SRC0_MASK 0xff
+#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
+#define SQ_VOP_SDWA__DST_SEL_MASK 0x700
+#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
+#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800
+#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
+#define SQ_VOP_SDWA__CLAMP_MASK 0x2000
+#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
+#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000
+#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
+#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000
+#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
+#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000
+#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000
+#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000
+#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
+#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000
+#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
+#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000
+#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
+#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000
+#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
+#define SQ_VOP3_0__VDST_MASK 0xff
+#define SQ_VOP3_0__VDST__SHIFT 0x0
+#define SQ_VOP3_0__ABS_MASK 0x700
+#define SQ_VOP3_0__ABS__SHIFT 0x8
+#define SQ_VOP3_0__CLAMP_MASK 0x8000
+#define SQ_VOP3_0__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0__OP_MASK 0x3ff0000
+#define SQ_VOP3_0__OP__SHIFT 0x10
+#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
+#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP2__SRC0_MASK 0x1ff
+#define SQ_VOP2__SRC0__SHIFT 0x0
+#define SQ_VOP2__VSRC1_MASK 0x1fe00
+#define SQ_VOP2__VSRC1__SHIFT 0x9
+#define SQ_VOP2__VDST_MASK 0x1fe0000
+#define SQ_VOP2__VDST__SHIFT 0x11
+#define SQ_VOP2__OP_MASK 0x7e000000
+#define SQ_VOP2__OP__SHIFT 0x19
+#define SQ_VOP2__ENCODING_MASK 0x80000000
+#define SQ_VOP2__ENCODING__SHIFT 0x1f
+#define SQ_MTBUF_0__OFFSET_MASK 0xfff
+#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
+#define SQ_MTBUF_0__OFFEN_MASK 0x1000
+#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
+#define SQ_MTBUF_0__IDXEN_MASK 0x2000
+#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
+#define SQ_MTBUF_0__GLC_MASK 0x4000
+#define SQ_MTBUF_0__GLC__SHIFT 0xe
+#define SQ_MTBUF_0__OP_MASK 0x78000
+#define SQ_MTBUF_0__OP__SHIFT 0xf
+#define SQ_MTBUF_0__DFMT_MASK 0x780000
+#define SQ_MTBUF_0__DFMT__SHIFT 0x13
+#define SQ_MTBUF_0__NFMT_MASK 0x3800000
+#define SQ_MTBUF_0__NFMT__SHIFT 0x17
+#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
+#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
+#define SQ_SOPP__SIMM16_MASK 0xffff
+#define SQ_SOPP__SIMM16__SHIFT 0x0
+#define SQ_SOPP__OP_MASK 0x7f0000
+#define SQ_SOPP__OP__SHIFT 0x10
+#define SQ_SOPP__ENCODING_MASK 0xff800000
+#define SQ_SOPP__ENCODING__SHIFT 0x17
+#define SQ_FLAT_0__GLC_MASK 0x10000
+#define SQ_FLAT_0__GLC__SHIFT 0x10
+#define SQ_FLAT_0__SLC_MASK 0x20000
+#define SQ_FLAT_0__SLC__SHIFT 0x11
+#define SQ_FLAT_0__OP_MASK 0x1fc0000
+#define SQ_FLAT_0__OP__SHIFT 0x12
+#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
+#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
+#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
+#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
+#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
+#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000
+#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
+#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000
+#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
+#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
+#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_1__VADDR_MASK 0xff
+#define SQ_MIMG_1__VADDR__SHIFT 0x0
+#define SQ_MIMG_1__VDATA_MASK 0xff00
+#define SQ_MIMG_1__VDATA__SHIFT 0x8
+#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
+#define SQ_MIMG_1__SRSRC__SHIFT 0x10
+#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
+#define SQ_MIMG_1__SSAMP__SHIFT 0x15
+#define SQ_MIMG_1__D16_MASK 0x80000000
+#define SQ_MIMG_1__D16__SHIFT 0x1f
+#define SQ_SOP1__SSRC0_MASK 0xff
+#define SQ_SOP1__SSRC0__SHIFT 0x0
+#define SQ_SOP1__OP_MASK 0xff00
+#define SQ_SOP1__OP__SHIFT 0x8
+#define SQ_SOP1__SDST_MASK 0x7f0000
+#define SQ_SOP1__SDST__SHIFT 0x10
+#define SQ_SOP1__ENCODING_MASK 0xff800000
+#define SQ_SOP1__ENCODING__SHIFT 0x17
+#define SQ_SOPC__SSRC0_MASK 0xff
+#define SQ_SOPC__SSRC0__SHIFT 0x0
+#define SQ_SOPC__SSRC1_MASK 0xff00
+#define SQ_SOPC__SSRC1__SHIFT 0x8
+#define SQ_SOPC__OP_MASK 0x7f0000
+#define SQ_SOPC__OP__SHIFT 0x10
+#define SQ_SOPC__ENCODING_MASK 0xff800000
+#define SQ_SOPC__ENCODING__SHIFT 0x17
+#define SQ_FLAT_1__ADDR_MASK 0xff
+#define SQ_FLAT_1__ADDR__SHIFT 0x0
+#define SQ_FLAT_1__DATA_MASK 0xff00
+#define SQ_FLAT_1__DATA__SHIFT 0x8
+#define SQ_FLAT_1__TFE_MASK 0x800000
+#define SQ_FLAT_1__TFE__SHIFT 0x17
+#define SQ_FLAT_1__VDST_MASK 0xff000000
+#define SQ_FLAT_1__VDST__SHIFT 0x18
+#define SQ_DS_1__ADDR_MASK 0xff
+#define SQ_DS_1__ADDR__SHIFT 0x0
+#define SQ_DS_1__DATA0_MASK 0xff00
+#define SQ_DS_1__DATA0__SHIFT 0x8
+#define SQ_DS_1__DATA1_MASK 0xff0000
+#define SQ_DS_1__DATA1__SHIFT 0x10
+#define SQ_DS_1__VDST_MASK 0xff000000
+#define SQ_DS_1__VDST__SHIFT 0x18
+#define SQ_VOP3_1__SRC0_MASK 0x1ff
+#define SQ_VOP3_1__SRC0__SHIFT 0x0
+#define SQ_VOP3_1__SRC1_MASK 0x3fe00
+#define SQ_VOP3_1__SRC1__SHIFT 0x9
+#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
+#define SQ_VOP3_1__SRC2__SHIFT 0x12
+#define SQ_VOP3_1__OMOD_MASK 0x18000000
+#define SQ_VOP3_1__OMOD__SHIFT 0x1b
+#define SQ_VOP3_1__NEG_MASK 0xe0000000
+#define SQ_VOP3_1__NEG__SHIFT 0x1d
+#define SQ_SMEM_0__SBASE_MASK 0x3f
+#define SQ_SMEM_0__SBASE__SHIFT 0x0
+#define SQ_SMEM_0__SDATA_MASK 0x1fc0
+#define SQ_SMEM_0__SDATA__SHIFT 0x6
+#define SQ_SMEM_0__GLC_MASK 0x10000
+#define SQ_SMEM_0__GLC__SHIFT 0x10
+#define SQ_SMEM_0__IMM_MASK 0x20000
+#define SQ_SMEM_0__IMM__SHIFT 0x11
+#define SQ_SMEM_0__OP_MASK 0x3fc0000
+#define SQ_SMEM_0__OP__SHIFT 0x12
+#define SQ_SMEM_0__ENCODING_MASK 0xfc000000
+#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
+#define SQ_MIMG_0__DMASK_MASK 0xf00
+#define SQ_MIMG_0__DMASK__SHIFT 0x8
+#define SQ_MIMG_0__UNORM_MASK 0x1000
+#define SQ_MIMG_0__UNORM__SHIFT 0xc
+#define SQ_MIMG_0__GLC_MASK 0x2000
+#define SQ_MIMG_0__GLC__SHIFT 0xd
+#define SQ_MIMG_0__DA_MASK 0x4000
+#define SQ_MIMG_0__DA__SHIFT 0xe
+#define SQ_MIMG_0__R128_MASK 0x8000
+#define SQ_MIMG_0__R128__SHIFT 0xf
+#define SQ_MIMG_0__TFE_MASK 0x10000
+#define SQ_MIMG_0__TFE__SHIFT 0x10
+#define SQ_MIMG_0__LWE_MASK 0x20000
+#define SQ_MIMG_0__LWE__SHIFT 0x11
+#define SQ_MIMG_0__OP_MASK 0x1fc0000
+#define SQ_MIMG_0__OP__SHIFT 0x12
+#define SQ_MIMG_0__SLC_MASK 0x2000000
+#define SQ_MIMG_0__SLC__SHIFT 0x19
+#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
+#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
+#define SQ_SOPK__SIMM16_MASK 0xffff
+#define SQ_SOPK__SIMM16__SHIFT 0x0
+#define SQ_SOPK__SDST_MASK 0x7f0000
+#define SQ_SOPK__SDST__SHIFT 0x10
+#define SQ_SOPK__OP_MASK 0xf800000
+#define SQ_SOPK__OP__SHIFT 0x17
+#define SQ_SOPK__ENCODING_MASK 0xf0000000
+#define SQ_SOPK__ENCODING__SHIFT 0x1c
+#define SQ_DS_0__OFFSET0_MASK 0xff
+#define SQ_DS_0__OFFSET0__SHIFT 0x0
+#define SQ_DS_0__OFFSET1_MASK 0xff00
+#define SQ_DS_0__OFFSET1__SHIFT 0x8
+#define SQ_DS_0__GDS_MASK 0x10000
+#define SQ_DS_0__GDS__SHIFT 0x10
+#define SQ_DS_0__OP_MASK 0x1fe0000
+#define SQ_DS_0__OP__SHIFT 0x11
+#define SQ_DS_0__ENCODING_MASK 0xfc000000
+#define SQ_DS_0__ENCODING__SHIFT 0x1a
+#define SQ_VOP_DPP__SRC0_MASK 0xff
+#define SQ_VOP_DPP__SRC0__SHIFT 0x0
+#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00
+#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
+#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000
+#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
+#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000
+#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
+#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000
+#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
+#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000
+#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
+#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000
+#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
+#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000
+#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
+#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000
+#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
+#define SQ_VOPC__SRC0_MASK 0x1ff
+#define SQ_VOPC__SRC0__SHIFT 0x0
+#define SQ_VOPC__VSRC1_MASK 0x1fe00
+#define SQ_VOPC__VSRC1__SHIFT 0x9
+#define SQ_VOPC__OP_MASK 0x1fe0000
+#define SQ_VOPC__OP__SHIFT 0x11
+#define SQ_VOPC__ENCODING_MASK 0xfe000000
+#define SQ_VOPC__ENCODING__SHIFT 0x19
+#define SQ_VINTRP__VSRC_MASK 0xff
+#define SQ_VINTRP__VSRC__SHIFT 0x0
+#define SQ_VINTRP__ATTRCHAN_MASK 0x300
+#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
+#define SQ_VINTRP__ATTR_MASK 0xfc00
+#define SQ_VINTRP__ATTR__SHIFT 0xa
+#define SQ_VINTRP__OP_MASK 0x30000
+#define SQ_VINTRP__OP__SHIFT 0x10
+#define SQ_VINTRP__VDST_MASK 0x3fc0000
+#define SQ_VINTRP__VDST__SHIFT 0x12
+#define SQ_VINTRP__ENCODING_MASK 0xfc000000
+#define SQ_VINTRP__ENCODING__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
+#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
+#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
+#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
+#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
+#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
+#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
+#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
+#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
+#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
+#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
+#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
+#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
+#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
+#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
+#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
+#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
+#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
+#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
+#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
+#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
+#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
+#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
+#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
+#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
+#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
+#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
+#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
+#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
+#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
+#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
+#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
+#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
+#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
+#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
+#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
+#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
+#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
+#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
+#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
+#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
+#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
+#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
+#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
+#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
+#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
+#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
+#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
+#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_CTRL__CACHE_SIZE_MASK 0x3
+#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
+#define TCC_CTRL__RATE_MASK 0xc
+#define TCC_CTRL__RATE__SHIFT 0x2
+#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
+#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
+#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00
+#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
+#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
+#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
+#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
+#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
+#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
+#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
+#define TCC_CTRL__MDC_SIZE_MASK 0x3000000
+#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
+#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000
+#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
+#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000
+#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
+#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff
+#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000
+#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
+#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
+#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
+#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
+#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2
+#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
+#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
+#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
+#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
+#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
+#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
+#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
+#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
+#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
+#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
+#define TD_CNTL__PAD_STALL_EN_MASK 0x100
+#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
+#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
+#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
+#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
+#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
+#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
+#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
+#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
+#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
+#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
+#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
+#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
+#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
+#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000
+#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
+#define TD_STATUS__BUSY_MASK 0x80000000
+#define TD_STATUS__BUSY__SHIFT 0x1f
+#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
+#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
+#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
+#define TD_DEBUG_DATA__DATA__SHIFT 0x0
+#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1
+#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0
+#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2
+#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1
+#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4
+#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
+#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
+#define TD_SCRATCH__SCRATCH__SHIFT 0x0
+#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
+#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
+#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
+#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
+#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
+#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
+#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
+#define TA_CNTL_AUX__RESERVED_MASK 0xe
+#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
+#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
+#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000
+#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
+#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000
+#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000
+#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
+#define TA_RESERVED_010C__Unused_MASK 0xffffffff
+#define TA_RESERVED_010C__Unused__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
+#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
+#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
+#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
+#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
+#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
+#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
+#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
+#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
+#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
+#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
+#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
+#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
+#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
+#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
+#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
+#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
+#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
+#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
+#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
+#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
+#define TA_STATUS__IN_BUSY_MASK 0x1000000
+#define TA_STATUS__IN_BUSY__SHIFT 0x18
+#define TA_STATUS__FG_BUSY_MASK 0x2000000
+#define TA_STATUS__FG_BUSY__SHIFT 0x19
+#define TA_STATUS__LA_BUSY_MASK 0x4000000
+#define TA_STATUS__LA_BUSY__SHIFT 0x1a
+#define TA_STATUS__FL_BUSY_MASK 0x8000000
+#define TA_STATUS__FL_BUSY__SHIFT 0x1b
+#define TA_STATUS__TA_BUSY_MASK 0x10000000
+#define TA_STATUS__TA_BUSY__SHIFT 0x1c
+#define TA_STATUS__FA_BUSY_MASK 0x20000000
+#define TA_STATUS__FA_BUSY__SHIFT 0x1d
+#define TA_STATUS__AL_BUSY_MASK 0x40000000
+#define TA_STATUS__AL_BUSY__SHIFT 0x1e
+#define TA_STATUS__BUSY_MASK 0x80000000
+#define TA_STATUS__BUSY__SHIFT 0x1f
+#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
+#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
+#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
+#define TA_DEBUG_DATA__DATA__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
+#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
+#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
+#define TA_SCRATCH__SCRATCH__SHIFT 0x0
+#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
+#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
+#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
+#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
+#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
+#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
+#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
+#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
+#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
+#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
+#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
+#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
+#define TCP_INVALIDATE__START_MASK 0x1
+#define TCP_INVALIDATE__START__SHIFT 0x0
+#define TCP_STATUS__TCP_BUSY_MASK 0x1
+#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
+#define TCP_STATUS__INPUT_BUSY_MASK 0x2
+#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
+#define TCP_STATUS__ADRS_BUSY_MASK 0x4
+#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
+#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8
+#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
+#define TCP_STATUS__CNTRL_BUSY_MASK 0x10
+#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
+#define TCP_STATUS__LFIFO_BUSY_MASK 0x20
+#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
+#define TCP_STATUS__READ_BUSY_MASK 0x40
+#define TCP_STATUS__READ_BUSY__SHIFT 0x6
+#define TCP_STATUS__FORMAT_BUSY_MASK 0x80
+#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
+#define TCP_CNTL__FORCE_HIT_MASK 0x1
+#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
+#define TCP_CNTL__FORCE_MISS_MASK 0x2
+#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
+#define TCP_CNTL__L1_SIZE_MASK 0xc
+#define TCP_CNTL__L1_SIZE__SHIFT 0x2
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
+#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
+#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
+#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
+#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
+#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
+#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
+#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
+#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
+#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
+#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
+#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
+#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
+#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
+#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
+#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
+#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
+#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
+#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
+#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
+#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
+#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
+#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
+#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
+#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
+#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
+#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
+#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
+#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
+#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
+#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
+#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
+#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
+#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
+#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
+#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
+#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
+#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
+#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
+#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
+#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
+#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
+#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
+#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
+#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
+#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
+#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
+#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
+#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
+#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
+#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
+#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
+#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
+#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
+#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
+#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
+#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff
+#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
+#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00
+#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
+#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000
+#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
+#define TCP_EDC_CNT__UNUSED_MASK 0xff000000
+#define TCP_EDC_CNT__UNUSED__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
+#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
+#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
+#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
+#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
+#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
+#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
+#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
+#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
+#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
+#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
+#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
+#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
+#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
+#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
+#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
+#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
+#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
+#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
+#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
+#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
+#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
+#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
+#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
+#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
+#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
+#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
+#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
+#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
+#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
+#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
+#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
+#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
+#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
+#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
+#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
+#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
+#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
+#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
+#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
+#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
+#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
+#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
+#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
+#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
+#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
+#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
+#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
+#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
+#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
+#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
+#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
+#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
+#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
+#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
+#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
+#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
+#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
+#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
+#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
+#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
+#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
+#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
+#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
+#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
+#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
+#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
+#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
+#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
+#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
+#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
+#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
+#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
+#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
+#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
+#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
+#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
+#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000
+#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
+#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000
+#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000
+#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
+#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
+#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff
+#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2
+#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4
+#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
+#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20
+#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
+#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff
+#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
+#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
+#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
+#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define TCI_STATUS__TCI_BUSY_MASK 0x1
+#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
+#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
+#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
+#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
+#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
+#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
+#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
+#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
+#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
+#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
+#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
+#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
+#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
+#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
+#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
+#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
+#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
+#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
+#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
+#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
+#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
+#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
+#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
+#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80
+#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
+#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100
+#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
+#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200
+#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400
+#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
+#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800
+#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
+#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000
+#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
+#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000
+#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
+#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000
+#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
+#define GDS_ENHANCE2__MISC_MASK 0xffff
+#define GDS_ENHANCE2__MISC__SHIFT 0x0
+#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
+#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
+#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
+#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
+#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
+#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
+#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
+#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
+#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
+#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
+#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
+#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
+#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
+#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
+#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
+#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
+#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
+#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
+#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
+#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
+#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
+#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
+#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
+#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
+#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
+#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
+#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
+#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
+#define GDS_EDC_CNT__DED_MASK 0xff
+#define GDS_EDC_CNT__DED__SHIFT 0x0
+#define GDS_EDC_CNT__SED_MASK 0xff00
+#define GDS_EDC_CNT__SED__SHIFT 0x8
+#define GDS_EDC_CNT__SEC_MASK 0xff0000
+#define GDS_EDC_CNT__SEC__SHIFT 0x10
+#define GDS_EDC_GRBM_CNT__DED_MASK 0xff
+#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
+#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000
+#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
+#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
+#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4
+#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
+#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8
+#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10
+#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20
+#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40
+#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80
+#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100
+#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200
+#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400
+#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800
+#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
+#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000
+#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
+#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
+#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
+#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
+#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
+#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
+#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10
+#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20
+#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5
+#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0
+#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6
+#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
+#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
+#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
+#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
+#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
+#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
+#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
+#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
+#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
+#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
+#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
+#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
+#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
+#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
+#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
+#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
+#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
+#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
+#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
+#define GDS_ATOM_CNTL__AINC_MASK 0x3f
+#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
+#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
+#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
+#define GDS_ATOM_CNTL__DMODE_MASK 0x300
+#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
+#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00
+#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
+#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
+#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
+#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
+#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
+#define GDS_ATOM_BASE__BASE_MASK 0xffff
+#define GDS_ATOM_BASE__BASE__SHIFT 0x0
+#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
+#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
+#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
+#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
+#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
+#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
+#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
+#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
+#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
+#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
+#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
+#define GDS_ATOM_DST__DST_MASK 0xffffffff
+#define GDS_ATOM_DST__DST__SHIFT 0x0
+#define GDS_ATOM_OP__OP_MASK 0xff
+#define GDS_ATOM_OP__OP__SHIFT 0x0
+#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
+#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
+#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
+#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ0__DATA__SHIFT 0x0
+#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ1__DATA__SHIFT 0x0
+#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
+#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
+#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
+#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
+#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
+#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
+#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
+#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
+#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
+#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
+#define GDS_GWS_RESOURCE__DED_MASK 0x4000
+#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
+#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
+#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
+#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
+#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
+#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
+#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
+#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
+#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
+#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
+#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
+#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
+#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
+#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
+#define GDS_OA_CNTL__INDEX_MASK 0xf
+#define GDS_OA_CNTL__INDEX__SHIFT 0x0
+#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
+#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
+#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
+#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
+#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
+#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
+#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000
+#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
+#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000
+#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
+#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000
+#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
+#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
+#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
+#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
+#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
+#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
+#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
+#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
+#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
+#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
+#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
+#define GDS_DEBUG_REG0__spare1_MASK 0x3f
+#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
+#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
+#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
+#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
+#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
+#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
+#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
+#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
+#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
+#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
+#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
+#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
+#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
+#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
+#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
+#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
+#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
+#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
+#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
+#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
+#define GDS_DEBUG_REG0__spare__SHIFT 0x16
+#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
+#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
+#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
+#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
+#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
+#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
+#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
+#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
+#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
+#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
+#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
+#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
+#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
+#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
+#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
+#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
+#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
+#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
+#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
+#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
+#define GDS_DEBUG_REG1__spare_MASK 0xff000000
+#define GDS_DEBUG_REG1__spare__SHIFT 0x18
+#define GDS_DEBUG_REG2__ds_full_MASK 0x1
+#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
+#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
+#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
+#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
+#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
+#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
+#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
+#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
+#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
+#define GDS_DEBUG_REG2__req_MASK 0x7fff00
+#define GDS_DEBUG_REG2__req__SHIFT 0x8
+#define GDS_DEBUG_REG2__spare_MASK 0xff800000
+#define GDS_DEBUG_REG2__spare__SHIFT 0x17
+#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
+#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
+#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
+#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
+#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
+#define GDS_DEBUG_REG3__spare__SHIFT 0xf
+#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
+#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
+#define GDS_DEBUG_REG4__gws_req_MASK 0x2
+#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
+#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
+#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
+#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
+#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
+#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
+#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
+#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
+#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
+#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
+#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
+#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
+#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
+#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
+#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
+#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
+#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
+#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
+#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
+#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
+#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
+#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
+#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
+#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
+#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
+#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
+#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
+#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
+#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
+#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
+#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
+#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
+#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
+#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
+#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
+#define GDS_DEBUG_REG4__spare_MASK 0xff000000
+#define GDS_DEBUG_REG4__spare__SHIFT 0x18
+#define GDS_DEBUG_REG5__write_dis_MASK 0x1
+#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
+#define GDS_DEBUG_REG5__dec_error_MASK 0x2
+#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
+#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
+#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
+#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
+#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
+#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
+#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
+#define GDS_DEBUG_REG5__spare_MASK 0xe0
+#define GDS_DEBUG_REG5__spare__SHIFT 0x5
+#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
+#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
+#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
+#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
+#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
+#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
+#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
+#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
+#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
+#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
+#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
+#define GDS_DEBUG_REG6__spare__SHIFT 0x15
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
+#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
+#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
+#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
+#define GDS_VMID0_BASE__BASE_MASK 0xffff
+#define GDS_VMID0_BASE__BASE__SHIFT 0x0
+#define GDS_VMID1_BASE__BASE_MASK 0xffff
+#define GDS_VMID1_BASE__BASE__SHIFT 0x0
+#define GDS_VMID2_BASE__BASE_MASK 0xffff
+#define GDS_VMID2_BASE__BASE__SHIFT 0x0
+#define GDS_VMID3_BASE__BASE_MASK 0xffff
+#define GDS_VMID3_BASE__BASE__SHIFT 0x0
+#define GDS_VMID4_BASE__BASE_MASK 0xffff
+#define GDS_VMID4_BASE__BASE__SHIFT 0x0
+#define GDS_VMID5_BASE__BASE_MASK 0xffff
+#define GDS_VMID5_BASE__BASE__SHIFT 0x0
+#define GDS_VMID6_BASE__BASE_MASK 0xffff
+#define GDS_VMID6_BASE__BASE__SHIFT 0x0
+#define GDS_VMID7_BASE__BASE_MASK 0xffff
+#define GDS_VMID7_BASE__BASE__SHIFT 0x0
+#define GDS_VMID8_BASE__BASE_MASK 0xffff
+#define GDS_VMID8_BASE__BASE__SHIFT 0x0
+#define GDS_VMID9_BASE__BASE_MASK 0xffff
+#define GDS_VMID9_BASE__BASE__SHIFT 0x0
+#define GDS_VMID10_BASE__BASE_MASK 0xffff
+#define GDS_VMID10_BASE__BASE__SHIFT 0x0
+#define GDS_VMID11_BASE__BASE_MASK 0xffff
+#define GDS_VMID11_BASE__BASE__SHIFT 0x0
+#define GDS_VMID12_BASE__BASE_MASK 0xffff
+#define GDS_VMID12_BASE__BASE__SHIFT 0x0
+#define GDS_VMID13_BASE__BASE_MASK 0xffff
+#define GDS_VMID13_BASE__BASE__SHIFT 0x0
+#define GDS_VMID14_BASE__BASE_MASK 0xffff
+#define GDS_VMID14_BASE__BASE__SHIFT 0x0
+#define GDS_VMID15_BASE__BASE_MASK 0xffff
+#define GDS_VMID15_BASE__BASE__SHIFT 0x0
+#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
+#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
+#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
+#define GDS_GWS_VMID0__BASE_MASK 0x3f
+#define GDS_GWS_VMID0__BASE__SHIFT 0x0
+#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID1__BASE_MASK 0x3f
+#define GDS_GWS_VMID1__BASE__SHIFT 0x0
+#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID2__BASE_MASK 0x3f
+#define GDS_GWS_VMID2__BASE__SHIFT 0x0
+#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID3__BASE_MASK 0x3f
+#define GDS_GWS_VMID3__BASE__SHIFT 0x0
+#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID4__BASE_MASK 0x3f
+#define GDS_GWS_VMID4__BASE__SHIFT 0x0
+#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID5__BASE_MASK 0x3f
+#define GDS_GWS_VMID5__BASE__SHIFT 0x0
+#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID6__BASE_MASK 0x3f
+#define GDS_GWS_VMID6__BASE__SHIFT 0x0
+#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID7__BASE_MASK 0x3f
+#define GDS_GWS_VMID7__BASE__SHIFT 0x0
+#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID8__BASE_MASK 0x3f
+#define GDS_GWS_VMID8__BASE__SHIFT 0x0
+#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID9__BASE_MASK 0x3f
+#define GDS_GWS_VMID9__BASE__SHIFT 0x0
+#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID10__BASE_MASK 0x3f
+#define GDS_GWS_VMID10__BASE__SHIFT 0x0
+#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID11__BASE_MASK 0x3f
+#define GDS_GWS_VMID11__BASE__SHIFT 0x0
+#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID12__BASE_MASK 0x3f
+#define GDS_GWS_VMID12__BASE__SHIFT 0x0
+#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID13__BASE_MASK 0x3f
+#define GDS_GWS_VMID13__BASE__SHIFT 0x0
+#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID14__BASE_MASK 0x3f
+#define GDS_GWS_VMID14__BASE__SHIFT 0x0
+#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
+#define GDS_GWS_VMID15__BASE_MASK 0x3f
+#define GDS_GWS_VMID15__BASE__SHIFT 0x0
+#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
+#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
+#define GDS_OA_VMID0__MASK_MASK 0xffff
+#define GDS_OA_VMID0__MASK__SHIFT 0x0
+#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID1__MASK_MASK 0xffff
+#define GDS_OA_VMID1__MASK__SHIFT 0x0
+#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID2__MASK_MASK 0xffff
+#define GDS_OA_VMID2__MASK__SHIFT 0x0
+#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID3__MASK_MASK 0xffff
+#define GDS_OA_VMID3__MASK__SHIFT 0x0
+#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID4__MASK_MASK 0xffff
+#define GDS_OA_VMID4__MASK__SHIFT 0x0
+#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID5__MASK_MASK 0xffff
+#define GDS_OA_VMID5__MASK__SHIFT 0x0
+#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID6__MASK_MASK 0xffff
+#define GDS_OA_VMID6__MASK__SHIFT 0x0
+#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID7__MASK_MASK 0xffff
+#define GDS_OA_VMID7__MASK__SHIFT 0x0
+#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID8__MASK_MASK 0xffff
+#define GDS_OA_VMID8__MASK__SHIFT 0x0
+#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID9__MASK_MASK 0xffff
+#define GDS_OA_VMID9__MASK__SHIFT 0x0
+#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID10__MASK_MASK 0xffff
+#define GDS_OA_VMID10__MASK__SHIFT 0x0
+#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID11__MASK_MASK 0xffff
+#define GDS_OA_VMID11__MASK__SHIFT 0x0
+#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID12__MASK_MASK 0xffff
+#define GDS_OA_VMID12__MASK__SHIFT 0x0
+#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID13__MASK_MASK 0xffff
+#define GDS_OA_VMID13__MASK__SHIFT 0x0
+#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID14__MASK_MASK 0xffff
+#define GDS_OA_VMID14__MASK__SHIFT 0x0
+#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
+#define GDS_OA_VMID15__MASK_MASK 0xffff
+#define GDS_OA_VMID15__MASK__SHIFT 0x0
+#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
+#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
+#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
+#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
+#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
+#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
+#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
+#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
+#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
+#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
+#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
+#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
+#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
+#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
+#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
+#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
+#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
+#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
+#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
+#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
+#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
+#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
+#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
+#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
+#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
+#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
+#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
+#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
+#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
+#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
+#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
+#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
+#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
+#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
+#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
+#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
+#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
+#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
+#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
+#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
+#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
+#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
+#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
+#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
+#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
+#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
+#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
+#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
+#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
+#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
+#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
+#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
+#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
+#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
+#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
+#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
+#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
+#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
+#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
+#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
+#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
+#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
+#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
+#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
+#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
+#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
+#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
+#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
+#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
+#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
+#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
+#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
+#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
+#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
+#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
+#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
+#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
+#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
+#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
+#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
+#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
+#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
+#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
+#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
+#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
+#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
+#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
+#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
+#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
+#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
+#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
+#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
+#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
+#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
+#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
+#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
+#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
+#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
+#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
+#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
+#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
+#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
+#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
+#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
+#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
+#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
+#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
+#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
+#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
+#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
+#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
+#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
+#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
+#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
+#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
+#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
+#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
+#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
+#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
+#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
+#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
+#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
+#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
+#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
+#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
+#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
+#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
+#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
+#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
+#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
+#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
+#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
+#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
+#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
+#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
+#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
+#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
+#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
+#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
+#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
+#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
+#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
+#define GDS_OA_RESET__RESET_MASK 0x1
+#define GDS_OA_RESET__RESET__SHIFT 0x0
+#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
+#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
+#define GDS_ENHANCE__MISC_MASK 0xffff
+#define GDS_ENHANCE__MISC__SHIFT 0x0
+#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
+#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
+#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
+#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
+#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
+#define GDS_ENHANCE__UNUSED__SHIFT 0x12
+#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
+#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
+#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
+#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
+#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
+#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
+#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000
+#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
+#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000
+#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
+#define GDS_CS_CTXSW_STATUS__R_MASK 0x1
+#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_CS_CTXSW_STATUS__W_MASK 0x2
+#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
+#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1
+#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
+#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2
+#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
+#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
+#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
+#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
+#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
+#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff
+#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
+#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000
+#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
+#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
+#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
+#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
+#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
+#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
+#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
+#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
+#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
+#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
+#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
+#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
+#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
+#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
+#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
+#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
+#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
+#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
+#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
+#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
+#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40
+#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
+#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
+#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
+#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
+#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
+#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800
+#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
+#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define IA_ENHANCE__MISC_MASK 0xffffffff
+#define IA_ENHANCE__MISC__SHIFT 0x0
+#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
+#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
+#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
+#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
+#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
+#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
+#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
+#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
+#define VGT_IMMED_DATA__DATA__SHIFT 0x0
+#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
+#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
+#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
+#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
+#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
+#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
+#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
+#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
+#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
+#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
+#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
+#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
+#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
+#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
+#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
+#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
+#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
+#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
+#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
+#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
+#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
+#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
+#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
+#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
+#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
+#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
+#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
+#define VGT_ENHANCE__MISC_MASK 0xffffffff
+#define VGT_ENHANCE__MISC__SHIFT 0x0
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
+#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
+#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
+#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
+#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
+#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
+#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
+#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
+#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
+#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
+#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
+#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
+#define VGT_GROUP_DECR__DECR_MASK 0xf
+#define VGT_GROUP_DECR__DECR__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
+#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
+#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
+#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
+#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
+#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
+#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
+#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
+#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
+#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
+#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
+#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
+#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
+#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
+#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
+#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
+#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
+#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
+#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
+#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
+#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
+#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
+#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
+#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
+#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
+#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
+#define VGT_GS_MODE__MODE_MASK 0x7
+#define VGT_GS_MODE__MODE__SHIFT 0x0
+#define VGT_GS_MODE__RESERVED_0_MASK 0x8
+#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
+#define VGT_GS_MODE__CUT_MODE_MASK 0x30
+#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
+#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
+#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
+#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
+#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
+#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
+#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
+#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
+#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
+#define VGT_GS_MODE__RESERVED_3_MASK 0x4000
+#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
+#define VGT_GS_MODE__RESERVED_4_MASK 0x8000
+#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
+#define VGT_GS_MODE__RESERVED_5_MASK 0x10000
+#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
+#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
+#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
+#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
+#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
+#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
+#define VGT_GS_MODE__ONCHIP_MASK 0x600000
+#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
+#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
+#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
+#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
+#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
+#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10
+#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
+#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
+#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
+#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
+#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
+#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
+#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
+#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
+#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
+#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
+#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
+#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
+#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
+#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
+#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
+#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
+#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
+#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
+#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
+#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
+#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
+#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
+#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
+#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
+#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000
+#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
+#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
+#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
+#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
+#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
+#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
+#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
+#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
+#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
+#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
+#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
+#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
+#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
+#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
+#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
+#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
+#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
+#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
+#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
+#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
+#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
+#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
+#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
+#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
+#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
+#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
+#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
+#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
+#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
+#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
+#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
+#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
+#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
+#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
+#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
+#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
+#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
+#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200
+#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800
+#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000
+#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
+#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
+#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
+#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
+#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
+#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
+#define VGT_TF_PARAM__TYPE_MASK 0x3
+#define VGT_TF_PARAM__TYPE__SHIFT 0x0
+#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
+#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
+#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
+#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
+#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
+#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
+#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
+#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
+#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
+#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
+#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000
+#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
+#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000
+#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
+#define VGT_TF_PARAM__MTYPE_MASK 0x180000
+#define VGT_TF_PARAM__MTYPE__SHIFT 0x13
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff
+#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00
+#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000
+#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000
+#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
+#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
+#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
+#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
+#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
+#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
+#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
+#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
+#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
+#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
+#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
+#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
+#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
+#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
+#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
+#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
+#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
+#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
+#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000
+#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
+#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
+#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
+#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
+#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
+#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
+#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
+#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
+#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
+#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
+#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
+#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
+#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
+#define WD_ENHANCE__MISC_MASK 0xffffffff
+#define WD_ENHANCE__MISC__SHIFT 0x0
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
+#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
+#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
+#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
+#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
+#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
+#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
+#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
+#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
+#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
+#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
+#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
+#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
+#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
+#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
+#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
+#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
+#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
+#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
+#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
+#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
+#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
+#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
+#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
+#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
+#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
+#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
+#define IA_DEBUG_DATA__DATA__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
+#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
+#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
+#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
+#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
+#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
+#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
+#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
+#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
+#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
+#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
+#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
+#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
+#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
+#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
+#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
+#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
+#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
+#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
+#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
+#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
+#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
+#define WD_DEBUG_DATA__DATA__SHIFT 0x0
+#define WD_QOS__DRAW_STALL_MASK 0x1
+#define WD_QOS__DRAW_STALL__SHIFT 0x0
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
+#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
+#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
+#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
+#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
+#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
+#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
+#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
+#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
+#define WD_DEBUG_REG0__wd_busy_MASK 0x4
+#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
+#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
+#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
+#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
+#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
+#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
+#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
+#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
+#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
+#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
+#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
+#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
+#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
+#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
+#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
+#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
+#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
+#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
+#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
+#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
+#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
+#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
+#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
+#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
+#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
+#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
+#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
+#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
+#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
+#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
+#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
+#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
+#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
+#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
+#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
+#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
+#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
+#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
+#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
+#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
+#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
+#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
+#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
+#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
+#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
+#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
+#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
+#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
+#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
+#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
+#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
+#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
+#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
+#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
+#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
+#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
+#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
+#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
+#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
+#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
+#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
+#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
+#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
+#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
+#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
+#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
+#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
+#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
+#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
+#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
+#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
+#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
+#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
+#define WD_DEBUG_REG1__SPARE0_MASK 0x100
+#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
+#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
+#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
+#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
+#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
+#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
+#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
+#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
+#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
+#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
+#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
+#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
+#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
+#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
+#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
+#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
+#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
+#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
+#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
+#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
+#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
+#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
+#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
+#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
+#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
+#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
+#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
+#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
+#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
+#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
+#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
+#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
+#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
+#define WD_DEBUG_REG2__SPARE0_MASK 0x100
+#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
+#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
+#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
+#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
+#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
+#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
+#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
+#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
+#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
+#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
+#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
+#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
+#define WD_DEBUG_REG3__SPARE0_MASK 0x2
+#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
+#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
+#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
+#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
+#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
+#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
+#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
+#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
+#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
+#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
+#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
+#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
+#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
+#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
+#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
+#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
+#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
+#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
+#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
+#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
+#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
+#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
+#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
+#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
+#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
+#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
+#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
+#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
+#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
+#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
+#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
+#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
+#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
+#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
+#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
+#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
+#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
+#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
+#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
+#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
+#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
+#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
+#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
+#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
+#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
+#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
+#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
+#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
+#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
+#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
+#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
+#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
+#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
+#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
+#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
+#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
+#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
+#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
+#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
+#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
+#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
+#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
+#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
+#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
+#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
+#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
+#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
+#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
+#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
+#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
+#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
+#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
+#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
+#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
+#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
+#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
+#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
+#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
+#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
+#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
+#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
+#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
+#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
+#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
+#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
+#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
+#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
+#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
+#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
+#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
+#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
+#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
+#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
+#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
+#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
+#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
+#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
+#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
+#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
+#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
+#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
+#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
+#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
+#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
+#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
+#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
+#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
+#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
+#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
+#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
+#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
+#define WD_DEBUG_REG5__SPARE0_MASK 0x2
+#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
+#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
+#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
+#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
+#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
+#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
+#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
+#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
+#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
+#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
+#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
+#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
+#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
+#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
+#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
+#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
+#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
+#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
+#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
+#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
+#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
+#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
+#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
+#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
+#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
+#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
+#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
+#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
+#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
+#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
+#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
+#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
+#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
+#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
+#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
+#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
+#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
+#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
+#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
+#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
+#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
+#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
+#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
+#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
+#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
+#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff
+#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0
+#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1
+#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8
+#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3
+#define WD_DEBUG_REG7__SPARE0_MASK 0xf0
+#define WD_DEBUG_REG7__SPARE0__SHIFT 0x4
+#define WD_DEBUG_REG7__SPARE1_MASK 0xf00
+#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8
+#define WD_DEBUG_REG7__SPARE2_MASK 0xf000
+#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc
+#define WD_DEBUG_REG7__SPARE3_MASK 0xf0000
+#define WD_DEBUG_REG7__SPARE3__SHIFT 0x10
+#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000
+#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
+#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000
+#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15
+#define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000
+#define WD_DEBUG_REG7__SPARE4__SHIFT 0x16
+#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000
+#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000
+#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e
+#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000
+#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f
+#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1
+#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0
+#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2
+#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1
+#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4
+#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2
+#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8
+#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3
+#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10
+#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4
+#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20
+#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5
+#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40
+#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6
+#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80
+#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7
+#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100
+#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8
+#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200
+#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9
+#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400
+#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa
+#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800
+#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb
+#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000
+#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc
+#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000
+#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12
+#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000
+#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13
+#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000
+#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
+#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000
+#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b
+#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000
+#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c
+#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000
+#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d
+#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000
+#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e
+#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000
+#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f
+#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1
+#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0
+#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2
+#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1
+#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4
+#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2
+#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8
+#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3
+#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10
+#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4
+#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20
+#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5
+#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40
+#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6
+#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80
+#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7
+#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100
+#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8
+#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200
+#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9
+#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400
+#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa
+#define WD_DEBUG_REG9__SPARE0_MASK 0xf800
+#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb
+#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000
+#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10
+#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000
+#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13
+#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000
+#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
+#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000
+#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18
+#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000
+#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19
+#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000
+#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a
+#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000
+#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b
+#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000
+#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c
+#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000
+#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e
+#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000
+#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f
+#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1
+#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0
+#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2
+#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1
+#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4
+#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2
+#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8
+#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3
+#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10
+#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4
+#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20
+#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5
+#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40
+#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6
+#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80
+#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7
+#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100
+#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8
+#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200
+#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9
+#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400
+#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa
+#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800
+#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb
+#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000
+#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc
+#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000
+#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd
+#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000
+#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe
+#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000
+#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf
+#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000
+#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000
+#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000
+#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000
+#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000
+#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f
+#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
+#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
+#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
+#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
+#define IA_DEBUG_REG0__ia_busy_MASK 0x4
+#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
+#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
+#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
+#define IA_DEBUG_REG0__SPARE0_MASK 0x10
+#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
+#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
+#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
+#define IA_DEBUG_REG0__dma_busy_MASK 0x40
+#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
+#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
+#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
+#define IA_DEBUG_REG0__grp_busy_MASK 0x100
+#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
+#define IA_DEBUG_REG0__SPARE1_MASK 0x200
+#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
+#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
+#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
+#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
+#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
+#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
+#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
+#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
+#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
+#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
+#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
+#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
+#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
+#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
+#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
+#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
+#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
+#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
+#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
+#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
+#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
+#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
+#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
+#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
+#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
+#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
+#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
+#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
+#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
+#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
+#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
+#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
+#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
+#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
+#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
+#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
+#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
+#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
+#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
+#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
+#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
+#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
+#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
+#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
+#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
+#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
+#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
+#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
+#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
+#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
+#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
+#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
+#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
+#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
+#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
+#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
+#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
+#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
+#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
+#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
+#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
+#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
+#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
+#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
+#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
+#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
+#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
+#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
+#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
+#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
+#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
+#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
+#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
+#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
+#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
+#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
+#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
+#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
+#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
+#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
+#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
+#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
+#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
+#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
+#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
+#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
+#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
+#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
+#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
+#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
+#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
+#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
+#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
+#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
+#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
+#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
+#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
+#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
+#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
+#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
+#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
+#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
+#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
+#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
+#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
+#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
+#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
+#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
+#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
+#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
+#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
+#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
+#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
+#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
+#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
+#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
+#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
+#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
+#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
+#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
+#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
+#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
+#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
+#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
+#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
+#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
+#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
+#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
+#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
+#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
+#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
+#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
+#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
+#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
+#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
+#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
+#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
+#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
+#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
+#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
+#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
+#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
+#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
+#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
+#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
+#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
+#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
+#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
+#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
+#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
+#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
+#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
+#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
+#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
+#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
+#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
+#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
+#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
+#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
+#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
+#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
+#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
+#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
+#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
+#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
+#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
+#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
+#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
+#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
+#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
+#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
+#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
+#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
+#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
+#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
+#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
+#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
+#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
+#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
+#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
+#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
+#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
+#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
+#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
+#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
+#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
+#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
+#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
+#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
+#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
+#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
+#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
+#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
+#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
+#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
+#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
+#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
+#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
+#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
+#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
+#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
+#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
+#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
+#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
+#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
+#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
+#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
+#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
+#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
+#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
+#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
+#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
+#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
+#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
+#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
+#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
+#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
+#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
+#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
+#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
+#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
+#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
+#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
+#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
+#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
+#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
+#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
+#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
+#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
+#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
+#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
+#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
+#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
+#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
+#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
+#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
+#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
+#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
+#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
+#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
+#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
+#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
+#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
+#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
+#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
+#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
+#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
+#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
+#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
+#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
+#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
+#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
+#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
+#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
+#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
+#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
+#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
+#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
+#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
+#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
+#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
+#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
+#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
+#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
+#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
+#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
+#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
+#define IA_DEBUG_REG6__extract_group_MASK 0x800000
+#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
+#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
+#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
+#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
+#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
+#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
+#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
+#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
+#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
+#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
+#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
+#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
+#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
+#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
+#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
+#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
+#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
+#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
+#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
+#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
+#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
+#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
+#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
+#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
+#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
+#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
+#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
+#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
+#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
+#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
+#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
+#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
+#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
+#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
+#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
+#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
+#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
+#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
+#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
+#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
+#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
+#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
+#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
+#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
+#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
+#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
+#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
+#define IA_DEBUG_REG8__grp_continued_MASK 0x800
+#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
+#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
+#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
+#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
+#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
+#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
+#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
+#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
+#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
+#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
+#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
+#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
+#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
+#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
+#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
+#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
+#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
+#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
+#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
+#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
+#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
+#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
+#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
+#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
+#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
+#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
+#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
+#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
+#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
+#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
+#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
+#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
+#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
+#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
+#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
+#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
+#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
+#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
+#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
+#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
+#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
+#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
+#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
+#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
+#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
+#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
+#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
+#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
+#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
+#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
+#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
+#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
+#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
+#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
+#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
+#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
+#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
+#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
+#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
+#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
+#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
+#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
+#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
+#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
+#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
+#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
+#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
+#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
+#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
+#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
+#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
+#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
+#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
+#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
+#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
+#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
+#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
+#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
+#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
+#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
+#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
+#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
+#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
+#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
+#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
+#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
+#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
+#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
+#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
+#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
+#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
+#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
+#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
+#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
+#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
+#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
+#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
+#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
+#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
+#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
+#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
+#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
+#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
+#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
+#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
+#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
+#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
+#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
+#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
+#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
+#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
+#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
+#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
+#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
+#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
+#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
+#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
+#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
+#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
+#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
+#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
+#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
+#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
+#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
+#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
+#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
+#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
+#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
+#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
+#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
+#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
+#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
+#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
+#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
+#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
+#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
+#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
+#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
+#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
+#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
+#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
+#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
+#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
+#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
+#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
+#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
+#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
+#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
+#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
+#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
+#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
+#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
+#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
+#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
+#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
+#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
+#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
+#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
+#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
+#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
+#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
+#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
+#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
+#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
+#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
+#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
+#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
+#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
+#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
+#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
+#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
+#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
+#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
+#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
+#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
+#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
+#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
+#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
+#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
+#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
+#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
+#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
+#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
+#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
+#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
+#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
+#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
+#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
+#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
+#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
+#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
+#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
+#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
+#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
+#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
+#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
+#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
+#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
+#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
+#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
+#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
+#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
+#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
+#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
+#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
+#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
+#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
+#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
+#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
+#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
+#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
+#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
+#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
+#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
+#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
+#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
+#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
+#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
+#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
+#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
+#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
+#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
+#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
+#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
+#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
+#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
+#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
+#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
+#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
+#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
+#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
+#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
+#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
+#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
+#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
+#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
+#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
+#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
+#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
+#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
+#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
+#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
+#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
+#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
+#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
+#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
+#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
+#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
+#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
+#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
+#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
+#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
+#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
+#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
+#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
+#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
+#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
+#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
+#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
+#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
+#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
+#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
+#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
+#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
+#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
+#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
+#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
+#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
+#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
+#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
+#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
+#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
+#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
+#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
+#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
+#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
+#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
+#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
+#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
+#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
+#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
+#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
+#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
+#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
+#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
+#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
+#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
+#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
+#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
+#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
+#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
+#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
+#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
+#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
+#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
+#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
+#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
+#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
+#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
+#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
+#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
+#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
+#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
+#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
+#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
+#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
+#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
+#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
+#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
+#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
+#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
+#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
+#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
+#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
+#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
+#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
+#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
+#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
+#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
+#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
+#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
+#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
+#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
+#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
+#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
+#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
+#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
+#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
+#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
+#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
+#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
+#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
+#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
+#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
+#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
+#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
+#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
+#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
+#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
+#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
+#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
+#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
+#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
+#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
+#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
+#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
+#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
+#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
+#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
+#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
+#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
+#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
+#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
+#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
+#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
+#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
+#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
+#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
+#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
+#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
+#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
+#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
+#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
+#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
+#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
+#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
+#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
+#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
+#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
+#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
+#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
+#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
+#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
+#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
+#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
+#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
+#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
+#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
+#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
+#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
+#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
+#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
+#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
+#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
+#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
+#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
+#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
+#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
+#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
+#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
+#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
+#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
+#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
+#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
+#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
+#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
+#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
+#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
+#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
+#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
+#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
+#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
+#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
+#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
+#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
+#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
+#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
+#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
+#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
+#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
+#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
+#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
+#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
+#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
+#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
+#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
+#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
+#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
+#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
+#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
+#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
+#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
+#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
+#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
+#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
+#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
+#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
+#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
+#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
+#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
+#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
+#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
+#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
+#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
+#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
+#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
+#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
+#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
+#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
+#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
+#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
+#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
+#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
+#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
+#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
+#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
+#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
+#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
+#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
+#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
+#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
+#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
+#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
+#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
+#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
+#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
+#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
+#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
+#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
+#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
+#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
+#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
+#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
+#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
+#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
+#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
+#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
+#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
+#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
+#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
+#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
+#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
+#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
+#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
+#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
+#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
+#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
+#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
+#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
+#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
+#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
+#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
+#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
+#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
+#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
+#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
+#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
+#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
+#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
+#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
+#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
+#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
+#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
+#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
+#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
+#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
+#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
+#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
+#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
+#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
+#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
+#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
+#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
+#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
+#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
+#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
+#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
+#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
+#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
+#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
+#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
+#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
+#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
+#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
+#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
+#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
+#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
+#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
+#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
+#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
+#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
+#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
+#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
+#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
+#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
+#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
+#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
+#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
+#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
+#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
+#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
+#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
+#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
+#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
+#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
+#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
+#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
+#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
+#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
+#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
+#define VGT_DEBUG_REG15__counters_full_MASK 0x10
+#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
+#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
+#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
+#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
+#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
+#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
+#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
+#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
+#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
+#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
+#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
+#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
+#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
+#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
+#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
+#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
+#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
+#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
+#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
+#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
+#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
+#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
+#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
+#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
+#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
+#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
+#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
+#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
+#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
+#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
+#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
+#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
+#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
+#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
+#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
+#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
+#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
+#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
+#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
+#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
+#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
+#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
+#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
+#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
+#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
+#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
+#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
+#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
+#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
+#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
+#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
+#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
+#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
+#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
+#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
+#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
+#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
+#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
+#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
+#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
+#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
+#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
+#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
+#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
+#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
+#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
+#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
+#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
+#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
+#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
+#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
+#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
+#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
+#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
+#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
+#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
+#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
+#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
+#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
+#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
+#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
+#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
+#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
+#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
+#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
+#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
+#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
+#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
+#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
+#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
+#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
+#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
+#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
+#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
+#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
+#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
+#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
+#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
+#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
+#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
+#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
+#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
+#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
+#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
+#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
+#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
+#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
+#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
+#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
+#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
+#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
+#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
+#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
+#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
+#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
+#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
+#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
+#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
+#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
+#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
+#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
+#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
+#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
+#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
+#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
+#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
+#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
+#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
+#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
+#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
+#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
+#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
+#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
+#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
+#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
+#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
+#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
+#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
+#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
+#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
+#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
+#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
+#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
+#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
+#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
+#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
+#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
+#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
+#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
+#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
+#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
+#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
+#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
+#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
+#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
+#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
+#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
+#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
+#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
+#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
+#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
+#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
+#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
+#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
+#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
+#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
+#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
+#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
+#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
+#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
+#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
+#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
+#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
+#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
+#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
+#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
+#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
+#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
+#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
+#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
+#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
+#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
+#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
+#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
+#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
+#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
+#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
+#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
+#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
+#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
+#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
+#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
+#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
+#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
+#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
+#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
+#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
+#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
+#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
+#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
+#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
+#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
+#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
+#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
+#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
+#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
+#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
+#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
+#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
+#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
+#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
+#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
+#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
+#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
+#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
+#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
+#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
+#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
+#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
+#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
+#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
+#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
+#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
+#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
+#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
+#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
+#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
+#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
+#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
+#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
+#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
+#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
+#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
+#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
+#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
+#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
+#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
+#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
+#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
+#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
+#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
+#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
+#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
+#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
+#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
+#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
+#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
+#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
+#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
+#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
+#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
+#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
+#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
+#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
+#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
+#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
+#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
+#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
+#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
+#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
+#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
+#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
+#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
+#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
+#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
+#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
+#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
+#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
+#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
+#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
+#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
+#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
+#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
+#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
+#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
+#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
+#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
+#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
+#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
+#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
+#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
+#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
+#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
+#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
+#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
+#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
+#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
+#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
+#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
+#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
+#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
+#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
+#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
+#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
+#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
+#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
+#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
+#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
+#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
+#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
+#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
+#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
+#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
+#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
+#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
+#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
+#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
+#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
+#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
+#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
+#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
+#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
+#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
+#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
+#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
+#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
+#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
+#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
+#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
+#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
+#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
+#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
+#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
+#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
+#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
+#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
+#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
+#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
+#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
+#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
+#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
+#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
+#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
+#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
+#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
+#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
+#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
+#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
+#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
+#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
+#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
+#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
+#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
+#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
+#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
+#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
+#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
+#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
+#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
+#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
+#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
+#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
+#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
+#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
+#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
+#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
+#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
+#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
+#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
+#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
+#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
+#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
+#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
+#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
+#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
+#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
+#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
+#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
+#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
+#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
+#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
+#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
+#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
+#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
+#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
+#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
+#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
+#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
+#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
+#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
+#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
+#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
+#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
+#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
+#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
+#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
+#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
+#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
+#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
+#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
+#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
+#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
+#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
+#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
+#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
+#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
+#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
+#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
+#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
+#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
+#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
+#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
+#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
+#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
+#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
+#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
+#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
+#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
+#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
+#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
+#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
+#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
+#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
+#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
+#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
+#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
+#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
+#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
+#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
+#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
+#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
+#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
+#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
+#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
+#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
+#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
+#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
+#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
+#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
+#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
+#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
+#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
+#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
+#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
+#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
+#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
+#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
+#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
+#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
+#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
+#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
+#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
+#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
+#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
+#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
+#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
+#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
+#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
+#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
+#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
+#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
+#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
+#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
+#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
+#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
+#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
+#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
+#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
+#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
+#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
+#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
+#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
+#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
+#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
+#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
+#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
+#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
+#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
+#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
+#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
+#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
+#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
+#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
+#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
+#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
+#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
+#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
+#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
+#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
+#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
+#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
+#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
+#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
+#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
+#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
+#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
+#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
+#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
+#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
+#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
+#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
+#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
+#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
+#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
+#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
+#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
+#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
+#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
+#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
+#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
+#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
+#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
+#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
+#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
+#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
+#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
+#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
+#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
+#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
+#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
+#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
+#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
+#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
+#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
+#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
+#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
+#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
+#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
+#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
+#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
+#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
+#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
+#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
+#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
+#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
+#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
+#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
+#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
+#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
+#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
+#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
+#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
+#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
+#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
+#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
+#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
+#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
+#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
+#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
+#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
+#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
+#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
+#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
+#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
+#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
+#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
+#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
+#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
+#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
+#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
+#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
+#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
+#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
+#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
+#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
+#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
+#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
+#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
+#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
+#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
+#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
+#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
+#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
+#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
+#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
+#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
+#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
+#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
+#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
+#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
+#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
+#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
+#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
+#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
+#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
+#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
+#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
+#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
+#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
+#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
+#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
+#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
+#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
+#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
+#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
+#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
+#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
+#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
+#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
+#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
+#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
+#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff
+#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
+#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
+#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
+#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
+#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
+#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
+#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
+#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
+#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
+#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
+#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
+#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
+#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
+#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
+#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
+#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
+#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1
+#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
+#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2
+#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1
+#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc
+#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2
+#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10
+#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
+#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
+#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
+#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0
+#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6
+#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff
+#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
+#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000
+#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
+#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
+#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
+#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000
+#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
+#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
+#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
+#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000
+#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
+#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
+#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
+#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000
+#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
+#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff
+#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0
+#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
+#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
+#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff
+#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
+#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00
+#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
+#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000
+#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
+#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000
+#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
+#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff
+#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
+#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00
+#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
+#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000
+#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
+#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000
+#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
+#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff
+#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
+#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00
+#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
+#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000
+#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
+#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000
+#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18
+
+#endif /* GFX_8_0_SH_MASK_H */