arm: fsl-layerscape: Migrate more DP-DDR options to Kconfig

Based on current usage, migrate a number of DP-DDR related options to
Kconfig.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 6273a7f..d503357 100644 (file)
--- a/README
+++ b/README
@@ -487,9 +487,6 @@ The following options need to be configured:
                CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
                Number of controllers used for other than main memory.
 
-               CONFIG_SYS_FSL_HAS_DP_DDR
-               Defines the SoC has DP-DDR used for DPAA.
-
                CONFIG_SYS_FSL_SEC_BE
                Defines the SEC controller register space as Big Endian
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9bb870d..5ea99c4 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -502,6 +502,31 @@ config SYS_FSL_HAS_CCN508
 
 config SYS_FSL_HAS_DP_DDR
        bool
+       help
+         Defines the SoC has DP-DDR used for DPAA.
+
+config DP_DDR_CTRL
+       int
+       depends on SYS_FSL_HAS_DP_DDR
+       default 2 if ARCH_LS2080A
+
+config DP_DDR_NUM_CTRLS
+       int
+       depends on SYS_FSL_HAS_DP_DDR
+       default 1 if ARCH_LS2080A
+
+config SYS_DP_DDR_BASE
+       hex
+       depends on SYS_FSL_HAS_DP_DDR
+       default 0x6000000000 if ARCH_LS2080A
+
+config SYS_DP_DDR_BASE_PHY
+       int
+       depends on SYS_FSL_HAS_DP_DDR
+       default 0 if ARCH_LS2080A
+       help
+         DDR controller uses this value as the base address for binding.
+         It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 
 config SYS_FSL_SRDS_1
        bool

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 9027bd0..82585f5 100644 (file)
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -40,16 +40,6 @@
 #define CPU_RELEASE_ADDR               secondary_boot_addr
 
 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-#define CONFIG_SYS_DP_DDR_BASE         0x6000000000ULL
-/*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
-#define CONFIG_SYS_DP_DDR_BASE_PHY     0
-#define CONFIG_DP_DDR_CTRL             2
-#define CONFIG_DP_DDR_NUM_CTRLS                1
-#endif
 
 /* Generic Timer Definitions */
 /*