: "cc",
"memory",
"x0", "x1", "x2", "x3", "x4", "x5",
- "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7"
+ "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8"
);
}
ld2 {v2.2d, v3.2d}, [pA]
add pA, pA, #32
- OP_rr v20.2d, v0.2d, v8.d[0]
- OP_ii v20.2d, v1.2d, v8.d[1]
- OP_ri v21.2d, v0.2d, v8.d[1]
- OP_ir v21.2d, v1.2d, v8.d[0]
+ OP_rr v20.2d, v0.2d, v9.d[0]
+ OP_ii v20.2d, v1.2d, v9.d[1]
+ OP_ri v21.2d, v0.2d, v9.d[1]
+ OP_ir v21.2d, v1.2d, v9.d[0]
ldr q10, [pB]
ldr q11, [pB, #16]
add pB, pB, #32
- OP_rr v18.2d, v2.2d, v9.d[0]
- OP_ii v18.2d, v3.2d, v9.d[1]
- OP_ri v19.2d, v2.2d, v9.d[1]
- OP_ir v19.2d, v3.2d, v9.d[0]
+ OP_rr v18.2d, v2.2d, v8.d[0]
+ OP_ii v18.2d, v3.2d, v8.d[1]
+ OP_ri v19.2d, v2.2d, v8.d[1]
+ OP_ir v19.2d, v3.2d, v8.d[0]
prfm PLDL1KEEP, [pB, #B_PRE_SIZE]