memory: mtk-smi: mt8188: Add SMI Support

Add mt8188 smi common & larb support

Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220817124608.10062-5-chengci.xu@mediatek.com

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index 73a8a98..5a97544 100644 (file)
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -283,6 +283,55 @@ static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
        return 0;
 }
 
+static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
+       [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
+       [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
+       [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},
+       [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
+       [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,},
+       [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,},
+       [6] = {0x06, 0x01, 0x06, 0x0a,},
+       [7] = {0x0c, 0x0c, 0x12,},
+       [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14,
+              0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05,
+              0x03, 0x01, 0x1e, 0x01, 0x05,},
+       [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10,
+              0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,},
+       [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
+               0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
+               0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
+       [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
+               0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
+               0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
+       [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c,
+               0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14,
+               0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,},
+       [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
+               0x07, 0x02, 0x04, 0x02, 0x05, 0x05,},
+       [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02,
+               0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+               0x02, 0x02, 0x01, 0x01,},
+       [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c,
+               0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02,
+               0x0c, 0x01, 0x01,},
+       [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d,
+               0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,},
+       [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
+               0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
+       [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
+               0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,},
+       [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
+       [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
+       [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
+               0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
+               0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
+       [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,
+               0x01,},
+       [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,},
+       [24] = {0x12, 0x06, 0x12, 0x06,},
+       [25] = {0x01},
+};
+
 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
        [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
        [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
@@ -369,6 +418,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
        .flags_general              = MTK_SMI_FLAG_SLEEP_CTL,
 };
 
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
+       .config_port                = mtk_smi_larb_config_port_gen2_general,
+       .flags_general              = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
+                                     MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
+       .ostd                       = mtk_smi_larb_mt8188_ostd,
+};
+
 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
        .config_port                = mtk_smi_larb_config_port_gen2_general,
 };
@@ -389,6 +445,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = {
        {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
        {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
        {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
+       {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
        {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
        {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
        {}
@@ -617,6 +674,18 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
        .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
 };
 
+static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = {
+       .type     = MTK_SMI_GEN2,
+       .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7),
+       .init     = mtk_smi_common_mt8195_init,
+};
+
+static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
+       .type     = MTK_SMI_GEN2,
+       .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
+       .init     = mtk_smi_common_mt8195_init,
+};
+
 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
        .type     = MTK_SMI_GEN2,
        .has_gals = true,
@@ -653,6 +722,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
        {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
        {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
        {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
+       {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
+       {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
        {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
        {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
        {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},