RISC-V: don't parse dt/acpi isa string to get rv32/rv64

When filling hwcap the kernel already expects the isa string to start with
rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT.

So when recreating the runtime isa-string we can also just go the other way
to get the correct starting point for it.

Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230713-masculine-saddlebag-67a94966b091@wendy
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3af2d21..f808b67 100644 (file)
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -257,13 +257,16 @@ static void print_isa_ext(struct seq_file *f)
  */
 static const char base_riscv_exts[13] = "imafdqcbkjpvh";
 
-static void print_isa(struct seq_file *f, const char *isa)
+static void print_isa(struct seq_file *f)
 {
        int i;
 
        seq_puts(f, "isa\t\t: ");
-       /* Print the rv[64/32] part */
-       seq_write(f, isa, 4);
+       if (IS_ENABLED(CONFIG_32BIT))
+               seq_write(f, "rv32", 4);
+       else
+               seq_write(f, "rv64", 4);
+
        for (i = 0; i < sizeof(base_riscv_exts); i++) {
                if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
                        /* Print only enabled the base ISA extensions */
@@ -320,27 +323,21 @@ static int c_show(struct seq_file *m, void *v)
        unsigned long cpu_id = (unsigned long)v - 1;
        struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
        struct device_node *node;
-       const char *compat, *isa;
+       const char *compat;
 
        seq_printf(m, "processor\t: %lu\n", cpu_id);
        seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
+       print_isa(m);
+       print_mmu(m);
 
        if (acpi_disabled) {
                node = of_get_cpu_node(cpu_id, NULL);
-               if (!of_property_read_string(node, "riscv,isa", &isa))
-                       print_isa(m, isa);
 
-               print_mmu(m);
                if (!of_property_read_string(node, "compatible", &compat) &&
                    strcmp(compat, "riscv"))
                        seq_printf(m, "uarch\t\t: %s\n", compat);
 
                of_node_put(node);
-       } else {
-               if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
-                       print_isa(m, isa);
-
-               print_mmu(m);
        }
 
        seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);