set (CLR_CROSS_COMPONENTS_LIST
crossgen
clrjit
- legacyjit
)
if(NOT CLR_CMAKE_PLATFORM_LINUX AND NOT FEATURE_CROSSBITNESS)
// We use this class (vs variables) so that the static functions can access data here.
class Constants {
- // We have very limited ARM64 hardware (used for ARM/ARMLB/ARM64 testing). So only allow certain branches to use it.
+ // We have very limited ARM64 hardware (used for ARM/ARM64 testing). So only allow certain branches to use it.
def static LimitedHardwareBranches = [
'master']
],
'arm64': [
'Checked'
- ],
- 'armlb': [
- 'Checked'
]
],
'Windows_NT_BuildOnly': [
],
]
- // A set of scenarios that are valid for arm/arm64/armlb tests run on hardware. This is a map from valid scenario name
+ // A set of scenarios that are valid for arm/arm64 tests run on hardware. This is a map from valid scenario name
// to Tests.lst file categories to exclude.
//
// This list should contain a subset of the scenarios from `allScenarios`. Please keep this in the same order as that,
// This is the set of architectures
// Some of these are pseudo-architectures:
- // armlb -- same as arm, but use the LEGACY_BACKEND JIT
// armem -- ARM builds/runs using an emulator. Used for Ubuntu/Ubuntu16.04/Tizen runs.
// x86_arm_altjit -- ARM runs on x86 using the ARM altjit
// x64_arm64_altjit -- ARM64 runs on x64 using the ARM64 altjit
- def static architectureList = ['arm', 'armlb', 'armem', 'x86_arm_altjit', 'x64_arm64_altjit', 'arm64', 'x64', 'x86']
+ def static architectureList = ['arm', 'armem', 'x86_arm_altjit', 'x64_arm64_altjit', 'arm64', 'x64', 'x86']
// This set of architectures that cross build on Windows and run on Windows ARM64 hardware.
- def static armWindowsCrossArchitectureList = ['arm', 'armlb', 'arm64']
+ def static armWindowsCrossArchitectureList = ['arm', 'arm64']
}
// **************************************************************
assert os instanceof String
assert architecture instanceof String
- def armArches = ['arm', 'armlb', 'armem', 'arm64']
+ def armArches = ['arm', 'armem', 'arm64']
def supportedArmLinuxOs = ['Ubuntu', 'Ubuntu16.04', 'Tizen']
if (!(architecture in armArches)) {
// Windows_NT
//
// Arm32 (Build) -> latest-arm64
- // |-> os == "Windows_NT" && (architecture == "arm" || architecture == "armlb") && options['use_arm64_build_machine'] == true
+ // |-> os == "Windows_NT" && (architecture == "arm") && options['use_arm64_build_machine'] == true
// Arm32 (Test) -> arm64-windows_nt
- // |-> os == "Windows_NT" && (architecture == "arm" || architecture == "armlb") && options['use_arm64_build_machine'] == false
+ // |-> os == "Windows_NT" && (architecture == "arm") && options['use_arm64_build_machine'] == false
//
// Arm64 (Build) -> latest-arm64
// |-> os == "Windows_NT" && architecture == "arm64" && options['use_arm64_build_machine'] == true
else if (isGcReliabilityFramework(scenario)) {
timeout = 1440
}
- else if (architecture == 'armlb' || architecture == 'armem' || architecture == 'arm64') {
+ else if (architecture == 'armem' || architecture == 'arm64') {
timeout = 240
}
// We have a limited amount of some hardware. For these, scale back the periodic testing we do,
// and only allowing using this hardware in some specific branches.
def static jobRequiresLimitedHardware(def architecture, def os) {
- if (((architecture == 'arm64') || (architecture == 'arm') || (architecture == 'armlb')) && (os == 'Windows_NT')) {
+ if (((architecture == 'arm64') || (architecture == 'arm')) && (os == 'Windows_NT')) {
// These test jobs require ARM64 hardware
return true
}
baseName = architecture.toLowerCase() + '_cross_' + configuration.toLowerCase() + '_' + os.toLowerCase()
}
break
- case 'armlb':
case 'arm':
baseName = architecture.toLowerCase() + '_cross_' + configuration.toLowerCase() + '_' + os.toLowerCase()
break
}
break
case 'armem':
- case 'armlb':
addGithubPushTriggerHelper(job)
break
case 'x86_arm_altjit':
break
// editor brace matching: }
- case 'armlb':
case 'arm': // editor brace matching: {
// Triggers on the non-flow jobs aren't necessary
switch (os) {
case 'Ubuntu':
- if (architecture == 'armlb') { // No arm legacy backend testing for Ubuntu
- break
- }
-
if (scenario == 'innerloop') {
if (configuration == 'Checked') {
Utilities.addGithubPRTriggerForBranch(job, branch, contextString)
break
case 'Windows_NT':
- if (architecture == "armlb") {
- // Disable armlb windows jobs
- break
- }
switch (scenario) {
case 'innerloop':
// Only Checked is an innerloop trigger.
}
}
break
- case 'armlb':
case 'arm':
assert isArmWindowsScenario(scenario)
def buildArchitecture = 'arm'
-
def buildOpts = ''
- // For 'armlb' (the JIT LEGACY_BACKEND architecture for arm), tell build.cmd to use legacy backend for crossgen compilation.
- // Legacy backend is not the default JIT; it is an aljit. So, this is a special case.
- if (architecture == 'armlb') {
- buildOpts += ' -crossgenaltjit legacyjit.dll'
- }
-
if (doCoreFxTesting) {
// We shouldn't need to build the tests. However, run-corefx-tests.py currently depends on having the restored corefx
// package available, to determine the correct corefx version git commit hash, and we need to build the tests before
return false
}
break
- case 'armlb':
- // Do not create armlb jobs
- return false
case 'x86_arm_altjit':
case 'x64_arm64_altjit':
if (os != 'Windows_NT') {
break
default:
- // arm64, armlb: stress is handled through flow jobs.
+ // arm64: stress is handled through flow jobs.
// armem: no stress jobs for ARM emulator.
return false
}
} // isPR
} // scenario
-// Create a Windows ARM/ARMLB/ARM64 test job that will be used by a flow job.
+// Create a Windows ARM/ARM64 test job that will be used by a flow job.
// Returns the newly created job.
def static CreateWindowsArmTestJob(def dslFactory, def project, def architecture, def os, def configuration, def scenario, def isPR, def inputCoreCLRBuildName)
{
addEnvVariable("COMPlus_NoGuiOnAssert", "1")
addEnvVariable("COMPlus_ContinueOnAssert", "0")
- // ARM legacy backend; this is an altjit.
- if (architecture == 'armlb') {
- addEnvVariable("COMPlus_AltJit", "*")
- addEnvVariable("COMPlus_AltJitNgen", "*")
- addEnvVariable("COMPlus_AltJitName", "legacyjit.dll")
- addEnvVariable("COMPlus_AltJitAssertOnNYI", "1")
- }
-
// If we are running a stress mode, we'll set those variables as well
if (isJitStressScenario(scenario) || isR2RStressScenario(scenario)) {
def stressValues = null
def smartyCommand = "C:\\Tools\\Smarty.exe /noecid /noie /workers 9 /inc EXPECTED_PASS "
def addSmartyFlag = { flag -> smartyCommand += flag + " "}
def addExclude = { exclude -> addSmartyFlag("/exc " + exclude)}
- def addArchSpecificExclude = { architectureToExclude, exclude -> if (architectureToExclude == "armlb") { addExclude("LEGACYJIT_" + exclude) } else { addExclude(exclude) } }
-
- if (architecture == 'armlb') {
- addExclude("LEGACYJIT_FAIL")
- }
+ def addArchSpecificExclude = { architectureToExclude, exclude -> addExclude(exclude) }
// Exclude tests based on scenario.
Constants.validArmWindowsScenarios[scenario].each { excludeTag ->
def testListArch = [
'arm64': 'arm64',
- 'arm': 'arm',
- 'armlb': 'arm'
+ 'arm': 'arm'
]
def archLocation = testListArch[architecture]
return false
}
break
- case 'armlb':
- if (os != 'Windows_NT') {
- return false
- }
- // Do not create armlb windows jobs.
- return false
case 'arm':
if (os != "Ubuntu" && os != "Windows_NT") {
return false
return false
}
- // On Windows, CoreFx tests currently not implemented for ARM64 or ARMLB.
- if (isCoreFxScenario(scenario) && (os == 'Windows_NT') && ((architecture == 'arm64') || (architecture == 'armlb'))) {
+ // On Windows, CoreFx tests currently not implemented for ARM64.
+ if (isCoreFxScenario(scenario) && (os == 'Windows_NT') && (architecture == 'arm64')) {
return false
}
}
return true
}
-// Create jobs requiring flow jobs. This includes x64 non-Windows, arm/arm64 Ubuntu, and arm/arm64/armlb Windows.
-// Note: no armlb non-Windows; we expect to deprecate/remove armlb soon, so don't want to add new testing for it.
+// Create jobs requiring flow jobs. This includes x64 non-Windows, arm/arm64 Ubuntu, and arm/arm64 Windows.
Constants.allScenarios.each { scenario ->
[true, false].each { isPR ->
Constants.architectureList.each { architecture ->
registerarm.h
registerarm64.h
reglist.h
- regpair.h
regset.h
sideeffects.h
simd.h
include(${CLR_DIR}/crossgen.cmake)
-if(CLR_CMAKE_TARGET_ARCH_ARM)
- add_definitions(-DLEGACY_BACKEND)
-endif()
-
add_library_clr(clrjit_crossgen ${SOURCES} ${JIT_ARCH_SOURCES})
if(FEATURE_MERGE_JIT_AND_ENGINE)
target_link_libraries(clrjit_crossgen ${RYUJIT_LINK_LIBRARIES})
project(ClrJit)
-if(CLR_CMAKE_TARGET_ARCH_ARM)
- add_definitions(-DLEGACY_BACKEND)
-endif(CLR_CMAKE_TARGET_ARCH_ARM)
-
if(CLR_CMAKE_PLATFORM_UNIX)
add_compile_options(-fPIC)
+++ /dev/null
-// Licensed to the .NET Foundation under one or more agreements.
-// The .NET Foundation licenses this file to you under the MIT license.
-// See the LICENSE file in the project root for more information.
-
-/*****************************************************************************/
-
-#ifndef PAIRBEG
-#define PAIRBEG(reg)
-#endif
-
-#ifndef PAIRDEF
-#define PAIRDEF(r1, r2)
-#endif
-
-#ifndef PAIRSTK
-#define PAIRSTK(r1, r2) PAIRDEF(r1, r2)
-#endif
-
-#if defined(_TARGET_X86_)
-/*****************************************************************************/
-/* The following is for x86 */
-/*****************************************************************************/
-
-// rlo rhi
-
-PAIRBEG(EAX)
-PAIRDEF(EAX, ECX)
-PAIRDEF(EAX, EDX)
-PAIRDEF(EAX, EBX)
-PAIRDEF(EAX, EBP)
-PAIRDEF(EAX, ESI)
-PAIRDEF(EAX, EDI)
-PAIRSTK(EAX, STK)
-
-PAIRBEG(ECX)
-PAIRDEF(ECX, EAX)
-PAIRDEF(ECX, EDX)
-PAIRDEF(ECX, EBX)
-PAIRDEF(ECX, EBP)
-PAIRDEF(ECX, ESI)
-PAIRDEF(ECX, EDI)
-PAIRSTK(ECX, STK)
-
-PAIRBEG(EDX)
-PAIRDEF(EDX, EAX)
-PAIRDEF(EDX, ECX)
-PAIRDEF(EDX, EBX)
-PAIRDEF(EDX, EBP)
-PAIRDEF(EDX, ESI)
-PAIRDEF(EDX, EDI)
-PAIRSTK(EDX, STK)
-
-PAIRBEG(EBX)
-PAIRDEF(EBX, EAX)
-PAIRDEF(EBX, EDX)
-PAIRDEF(EBX, ECX)
-PAIRDEF(EBX, EBP)
-PAIRDEF(EBX, ESI)
-PAIRDEF(EBX, EDI)
-PAIRSTK(EBX, STK)
-
-PAIRBEG(EBP)
-PAIRDEF(EBP, EAX)
-PAIRDEF(EBP, EDX)
-PAIRDEF(EBP, ECX)
-PAIRDEF(EBP, EBX)
-PAIRDEF(EBP, ESI)
-PAIRDEF(EBP, EDI)
-PAIRSTK(EBP, STK)
-
-PAIRBEG(ESI)
-PAIRDEF(ESI, EAX)
-PAIRDEF(ESI, EDX)
-PAIRDEF(ESI, ECX)
-PAIRDEF(ESI, EBX)
-PAIRDEF(ESI, EBP)
-PAIRDEF(ESI, EDI)
-PAIRSTK(ESI, STK)
-
-PAIRBEG(EDI)
-PAIRDEF(EDI, EAX)
-PAIRDEF(EDI, EDX)
-PAIRDEF(EDI, ECX)
-PAIRDEF(EDI, EBX)
-PAIRDEF(EDI, EBP)
-PAIRDEF(EDI, ESI)
-PAIRSTK(EDI, STK)
-
-PAIRBEG(STK)
-PAIRSTK(STK, EAX)
-PAIRSTK(STK, EDX)
-PAIRSTK(STK, ECX)
-PAIRSTK(STK, EBX)
-PAIRSTK(STK, EBP)
-PAIRSTK(STK, ESI)
-PAIRSTK(STK, EDI)
-
-#endif
-
-/*****************************************************************************/
-
-#ifdef _TARGET_ARM_
-/*****************************************************************************/
-/* The following is for ARM */
-/*****************************************************************************/
-
-// rlo rhi
-
-PAIRBEG(R0)
-PAIRDEF(R0, R1)
-PAIRDEF(R0, R2)
-PAIRDEF(R0, R3)
-PAIRDEF(R0, R4)
-PAIRDEF(R0, R5)
-PAIRDEF(R0, R6)
-PAIRDEF(R0, R7)
-PAIRDEF(R0, R8)
-PAIRDEF(R0, R9)
-PAIRDEF(R0, R10)
-PAIRDEF(R0, R11)
-PAIRDEF(R0, R12)
-PAIRDEF(R0, LR)
-PAIRSTK(R0, STK)
-
-PAIRBEG(R1)
-PAIRDEF(R1, R0)
-PAIRDEF(R1, R2)
-PAIRDEF(R1, R3)
-PAIRDEF(R1, R4)
-PAIRDEF(R1, R5)
-PAIRDEF(R1, R6)
-PAIRDEF(R1, R7)
-PAIRDEF(R1, R8)
-PAIRDEF(R1, R9)
-PAIRDEF(R1, R10)
-PAIRDEF(R1, R11)
-PAIRDEF(R1, R12)
-PAIRDEF(R1, LR)
-PAIRSTK(R1, STK)
-
-PAIRBEG(R2)
-PAIRDEF(R2, R0)
-PAIRDEF(R2, R1)
-PAIRDEF(R2, R3)
-PAIRDEF(R2, R4)
-PAIRDEF(R2, R5)
-PAIRDEF(R2, R6)
-PAIRDEF(R2, R7)
-PAIRDEF(R2, R8)
-PAIRDEF(R2, R9)
-PAIRDEF(R2, R10)
-PAIRDEF(R2, R11)
-PAIRDEF(R2, R12)
-PAIRDEF(R2, LR)
-PAIRSTK(R2, STK)
-
-PAIRBEG(R3)
-PAIRDEF(R3, R0)
-PAIRDEF(R3, R1)
-PAIRDEF(R3, R2)
-PAIRDEF(R3, R4)
-PAIRDEF(R3, R5)
-PAIRDEF(R3, R6)
-PAIRDEF(R3, R7)
-PAIRDEF(R3, R8)
-PAIRDEF(R3, R9)
-PAIRDEF(R3, R10)
-PAIRDEF(R3, R11)
-PAIRDEF(R3, R12)
-PAIRDEF(R3, LR)
-PAIRSTK(R3, STK)
-
-PAIRBEG(R4)
-PAIRDEF(R4, R0)
-PAIRDEF(R4, R1)
-PAIRDEF(R4, R2)
-PAIRDEF(R4, R3)
-PAIRDEF(R4, R5)
-PAIRDEF(R4, R6)
-PAIRDEF(R4, R7)
-PAIRDEF(R4, R8)
-PAIRDEF(R4, R9)
-PAIRDEF(R4, R10)
-PAIRDEF(R4, R11)
-PAIRDEF(R4, R12)
-PAIRDEF(R4, LR)
-PAIRSTK(R4, STK)
-
-PAIRBEG(R5)
-PAIRDEF(R5, R0)
-PAIRDEF(R5, R1)
-PAIRDEF(R5, R2)
-PAIRDEF(R5, R3)
-PAIRDEF(R5, R4)
-PAIRDEF(R5, R6)
-PAIRDEF(R5, R7)
-PAIRDEF(R5, R8)
-PAIRDEF(R5, R9)
-PAIRDEF(R5, R10)
-PAIRDEF(R5, R11)
-PAIRDEF(R5, R12)
-PAIRDEF(R5, LR)
-PAIRSTK(R5, STK)
-
-PAIRBEG(R6)
-PAIRDEF(R6, R0)
-PAIRDEF(R6, R1)
-PAIRDEF(R6, R2)
-PAIRDEF(R6, R3)
-PAIRDEF(R6, R4)
-PAIRDEF(R6, R5)
-PAIRDEF(R6, R7)
-PAIRDEF(R6, R8)
-PAIRDEF(R6, R9)
-PAIRDEF(R6, R10)
-PAIRDEF(R6, R11)
-PAIRDEF(R6, R12)
-PAIRDEF(R6, LR)
-PAIRSTK(R6, STK)
-
-PAIRBEG(R7)
-PAIRDEF(R7, R0)
-PAIRDEF(R7, R1)
-PAIRDEF(R7, R2)
-PAIRDEF(R7, R3)
-PAIRDEF(R7, R4)
-PAIRDEF(R7, R5)
-PAIRDEF(R7, R6)
-PAIRDEF(R7, R8)
-PAIRDEF(R7, R9)
-PAIRDEF(R7, R10)
-PAIRDEF(R7, R11)
-PAIRDEF(R7, R12)
-PAIRDEF(R7, LR)
-PAIRSTK(R7, STK)
-
-PAIRBEG(R8)
-PAIRDEF(R8, R0)
-PAIRDEF(R8, R1)
-PAIRDEF(R8, R2)
-PAIRDEF(R8, R3)
-PAIRDEF(R8, R4)
-PAIRDEF(R8, R5)
-PAIRDEF(R8, R6)
-PAIRDEF(R8, R7)
-PAIRDEF(R8, R9)
-PAIRDEF(R8, R10)
-PAIRDEF(R8, R11)
-PAIRDEF(R8, R12)
-PAIRDEF(R8, LR)
-PAIRSTK(R8, STK)
-
-PAIRBEG(R9)
-PAIRDEF(R9, R0)
-PAIRDEF(R9, R1)
-PAIRDEF(R9, R2)
-PAIRDEF(R9, R3)
-PAIRDEF(R9, R4)
-PAIRDEF(R9, R5)
-PAIRDEF(R9, R6)
-PAIRDEF(R9, R7)
-PAIRDEF(R9, R8)
-PAIRDEF(R9, R10)
-PAIRDEF(R9, R11)
-PAIRDEF(R9, R12)
-PAIRDEF(R9, LR)
-PAIRSTK(R9, STK)
-
-PAIRBEG(R10)
-PAIRDEF(R10, R0)
-PAIRDEF(R10, R1)
-PAIRDEF(R10, R2)
-PAIRDEF(R10, R3)
-PAIRDEF(R10, R4)
-PAIRDEF(R10, R5)
-PAIRDEF(R10, R6)
-PAIRDEF(R10, R7)
-PAIRDEF(R10, R8)
-PAIRDEF(R10, R9)
-PAIRDEF(R10, R11)
-PAIRDEF(R10, R12)
-PAIRDEF(R10, LR)
-PAIRSTK(R10, STK)
-
-PAIRBEG(R11)
-PAIRDEF(R11, R0)
-PAIRDEF(R11, R1)
-PAIRDEF(R11, R2)
-PAIRDEF(R11, R3)
-PAIRDEF(R11, R4)
-PAIRDEF(R11, R5)
-PAIRDEF(R11, R6)
-PAIRDEF(R11, R7)
-PAIRDEF(R11, R8)
-PAIRDEF(R11, R9)
-PAIRDEF(R11, R10)
-PAIRDEF(R11, R12)
-PAIRDEF(R11, LR)
-PAIRSTK(R11, STK)
-
-PAIRBEG(R12)
-PAIRDEF(R12, R0)
-PAIRDEF(R12, R1)
-PAIRDEF(R12, R2)
-PAIRDEF(R12, R3)
-PAIRDEF(R12, R4)
-PAIRDEF(R12, R5)
-PAIRDEF(R12, R6)
-PAIRDEF(R12, R7)
-PAIRDEF(R12, R8)
-PAIRDEF(R12, R9)
-PAIRDEF(R12, R10)
-PAIRDEF(R12, R11)
-PAIRDEF(R12, LR)
-PAIRSTK(R12, STK)
-
-PAIRBEG(LR)
-PAIRDEF(LR, R0)
-PAIRDEF(LR, R1)
-PAIRDEF(LR, R2)
-PAIRDEF(LR, R3)
-PAIRDEF(LR, R4)
-PAIRDEF(LR, R5)
-PAIRDEF(LR, R6)
-PAIRDEF(LR, R7)
-PAIRDEF(LR, R8)
-PAIRDEF(LR, R9)
-PAIRDEF(LR, R10)
-PAIRDEF(LR, R11)
-PAIRDEF(LR, R12)
-PAIRSTK(LR, STK)
-
-PAIRBEG(STK)
-PAIRSTK(STK, R0)
-PAIRSTK(STK, R1)
-PAIRSTK(STK, R2)
-PAIRSTK(STK, R3)
-PAIRSTK(STK, R4)
-PAIRSTK(STK, R5)
-PAIRSTK(STK, R6)
-PAIRSTK(STK, R7)
-PAIRSTK(STK, R8)
-PAIRSTK(STK, R9)
-PAIRSTK(STK, R10)
-PAIRSTK(STK, R11)
-PAIRSTK(STK, R12)
-PAIRSTK(STK, LR)
-
-#endif
-
-/*****************************************************************************/
-
-#undef PAIRBEG
-#undef PAIRDEF
-#undef PAIRSTK
-
-/*****************************************************************************/
WorkingDir=baseservices\compilerservices\dynamicobjectproperties\test448035
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[ldc_conv_ovf_u4_u2.cmd_343]
WorkingDir=baseservices\exceptions\regressions\V1\SEH\VJ\UserExceptionThread
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[thread22.cmd_651]
WorkingDir=baseservices\threading\mutex\abandonedmutex\am07abandonmultiplemutex
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[MathFIEEERemainder.cmd_1805]
WorkingDir=Loader\classloader\regressions\523654\test532654_b
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203
+Categories=EXPECTED_PASS
HostStyle=0
[Generated501.cmd_1908]
WorkingDir=GC\Features\Finalizer\finalizeother\finalizearraysleep
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_JITSTRESS_FAIL;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[_il_dbgindcall.cmd_1949]
WorkingDir=JIT\Methodical\explicit\basic\_il_relrefloc_r8
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203
+Categories=EXPECTED_PASS
HostStyle=0
[RuntimeMethodHanldeGetHashCode.cmd_2529]
WorkingDir=baseservices\threading\waithandle\waitall\waitallex9
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[float_cs_ro.cmd_3090]
WorkingDir=baseservices\exceptions\regressions\V1\SEH\VJ\HandlerException
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13206;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[bool_cs_d.cmd_3192]
WorkingDir=JIT\Directed\lifetime\lifetime1
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13200;13203;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[castclass-interface003.cmd_3807]
WorkingDir=JIT\Methodical\explicit\basic\_il_relrefloc_i1
Expected=0
MaxAllowedDurationSeconds=600
-Categories=EXPECTED_PASS;LEGACYJIT_GCSTRESS_FAIL;13203;Pri1
+Categories=EXPECTED_PASS;Pri1
HostStyle=0
[b16423.cmd_4054]
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[waitallex7a.cmd_4061]
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[Generated248.cmd_5066]
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[b47093.cmd_5523]
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[Generated1448.cmd_5528]
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[b57516.cmd_8471]
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[494226.cmd_9689]
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[KeyCollectionCtor.cmd_10305]
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[5w1d-06_cs_d.cmd_10704]
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[b16054.cmd_10888]
<Issue>2420. x86 JIT doesn't support implicit tail call optimization or tail. call pop ret sequence</Issue>
</ExcludeList>
<ExcludeList Include="$(XunitTestBinBase)\JIT\Regression\Dev11\External\dev11_239804\ShowLocallocAlignment\ShowLocallocAlignment.cmd">
- <Issue>7163, fails on both legacy backend and RyuJIT</Issue>
+ <Issue>7163</Issue>
</ExcludeList>
<ExcludeList Include="$(XunitTestBinBase)\JIT\Regression\JitBlue\DevDiv_255294\DevDiv_255294\DevDiv_255294.cmd">
<Issue>11469, The test causes OutOfMemory exception in crossgen mode.</Issue>