val inst_type = Cat(dec.io.isFinish,
dec.io.isAlu,
- dec.io.isGemm,
- dec.io.isLoadAcc,
- dec.io.isLoadUop).asUInt
+ dec.io.isGemm,
+ dec.io.isLoadAcc,
+ dec.io.isLoadUop).asUInt
val sprev = inst_q.io.deq.valid & Mux(dec.io.pop_prev, s(0).io.sready, true.B)
val snext = inst_q.io.deq.valid & Mux(dec.io.pop_next, s(1).io.sready, true.B)
switch (state) {
is (sIdle) {
when (start) {
- when (dec.io.isSync) {
+ when (dec.io.isSync) {
state := sSync
- } .elsewhen (inst_type.orR) {
+ } .elsewhen (inst_type.orR) {
state := sExe
- }
+ }
}
}
is (sSync) {
is (sIdle) {
when (pulse) {
state := sReadCmd
- when (xsize < xmax) {
+ when (xsize < xmax) {
rlen := xsize
- ilen := xsize >> 1.U
+ ilen := xsize >> 1.U
xrem := 0.U
- } .otherwise {
+ } .otherwise {
rlen := xmax - 1.U
- ilen := (xmax >> 1.U) - 1.U
+ ilen := (xmax >> 1.U) - 1.U
xrem := xsize - xmax
- }
+ }
}
}
is (sReadCmd) {
state := sDrain
} .otherwise {
state := sReadLSB
- }
+ }
}
}
is (sDrain) {
} .elsewhen (xrem < xmax) {
state := sReadCmd
rlen := xrem
- ilen := xrem >> 1.U
+ ilen := xrem >> 1.U
xrem := 0.U
} .otherwise {
state := sReadCmd
rlen := xmax - 1.U
- ilen := (xmax >> 1.U) - 1.U
+ ilen := (xmax >> 1.U) - 1.U
xrem := xrem - xmax
}
}
when (start) {
when (dec.io.isSync) {
state := sSync
- } .elsewhen (dec.io.isInput || dec.io.isWeight) {
+ } .elsewhen (dec.io.isInput || dec.io.isWeight) {
state := sExe
- }
+ }
}
}
is (sSync) {
when (state === sExe) {
when (done) {
when (dec.io.isInput) {
- printf("[Load] done input\n")
- } .elsewhen (dec.io.isWeight) {
- printf("[Load] done weight\n")
- }
+ printf("[Load] done input\n")
+ } .elsewhen (dec.io.isWeight) {
+ printf("[Load] done weight\n")
+ }
}
}
}
is (sIdle) {
when (io.start) {
state := sReadCmd
- when (xsize < xmax) {
+ when (xsize < xmax) {
xlen := xsize
xrem := 0.U
- } .otherwise {
+ } .otherwise {
xlen := xmax - 1.U
xrem := xsize - xmax
- }
+ }
}
}
is (sReadCmd) {
when (start) {
when (dec.io.isSync) {
state := sSync
- } .elsewhen (dec.io.isStore) {
+ } .elsewhen (dec.io.isStore) {
state := sExe
- }
+ }
}
}
is (sSync) {
}
when (state === sExe) {
when (done) {
- printf("[Store] done\n")
+ printf("[Store] done\n")
}
}
}
Mux(io.a < io.b, io.b, io.a),
io.a + io.b,
io.a >> n,
- io.a << m)
+ io.a << m)
val opmux = Seq.tabulate(ALU_OP_NUM)(i => ALU_OP(i) -> fop(i))
io.y := MuxLookup(io.opcode, io.a, opmux)
is (sExe) {
when (alu.io.out.data.valid) {
when ((cnt_o === dec.lp_0 - 1.U) &&
- (cnt_i === dec.lp_1 - 1.U) &&
- (uop_idx === uop_end - 1.U)) {
+ (cnt_i === dec.lp_1 - 1.U) &&
+ (uop_idx === uop_end - 1.U)) {
state := sIdle
} .otherwise {
state := sReadUop
when (state === sIdle ||
(state === sExe &&
- alu.io.out.data.valid &&
- uop_idx === uop_end - 1.U)) {
+ alu.io.out.data.valid &&
+ uop_idx === uop_end - 1.U)) {
uop_idx := dec.uop_begin
} .elsewhen (state === sExe && alu.io.out.data.valid) {
uop_idx := uop_idx + 1.U
} .elsewhen (state === sExe &&
alu.io.out.data.valid &&
uop_idx === uop_end - 1.U &&
- cnt_i === dec.lp_1 - 1.U) {
+ cnt_i === dec.lp_1 - 1.U) {
cnt_o := cnt_o + 1.U
dst_o := dst_o + dec.dst_0
src_o := src_o + dec.src_0
src_i := src_o
} .elsewhen (state === sExe &&
alu.io.out.data.valid &&
- uop_idx === uop_end - 1.U) {
+ uop_idx === uop_end - 1.U) {
cnt_i := cnt_i + 1.U
dst_i := dst_i + dec.dst_1
src_i := src_i + dec.src_1
val done = inflight === 0.U &
((state === sExe &
cnt_o === dec.lp_0 - 1.U &
- cnt_i === dec.lp_1 - 1.U &
- uop_idx === uop_end - 1.U &
- inflight === 0.U) |
- state === sWait)
+ cnt_i === dec.lp_1 - 1.U &
+ uop_idx === uop_end - 1.U &
+ inflight === 0.U) |
+ state === sWait)
switch (state) {
is (sIdle) {
when ((cnt_o === dec.lp_0 - 1.U) &&
(cnt_i === dec.lp_1 - 1.U) &&
(uop_idx === uop_end - 1.U)) {
- when (inflight =/= 0.U) {
+ when (inflight =/= 0.U) {
state := sWait
- } .otherwise {
+ } .otherwise {
state := sIdle
- }
+ }
} .otherwise {
state := sReadUop
}
when (state === sIdle ||
(state === sExe &&
- uop_idx === uop_end - 1.U)) {
+ uop_idx === uop_end - 1.U)) {
uop_idx := dec.uop_begin
} .elsewhen (state === sExe) {
uop_idx := uop_idx + 1.U
inp_o := 0.U
wgt_o := 0.U
} .elsewhen (state === sExe &&
- uop_idx === uop_end - 1.U &&
- cnt_i === dec.lp_1 - 1.U) {
+ uop_idx === uop_end - 1.U &&
+ cnt_i === dec.lp_1 - 1.U) {
cnt_o := cnt_o + 1.U
acc_o := acc_o + dec.acc_0
inp_o := inp_o + dec.inp_0
inp_i := inp_o
wgt_i := wgt_o
} .elsewhen (state === sExe &&
- uop_idx === uop_end - 1.U) {
+ uop_idx === uop_end - 1.U) {
cnt_i := cnt_i + 1.U
acc_i := acc_i + dec.acc_1
inp_i := inp_i + dec.inp_1
when (io.start) {
when (dec.ypad_0 =/= 0.U) {
state := sYPad0
- } .elsewhen (dec.xpad_0 =/= 0.U) {
+ } .elsewhen (dec.xpad_0 =/= 0.U) {
state := sXPad0
- } .otherwise {
+ } .otherwise {
state := sReadCmd
- }
+ }
}
}
is (sYPad0) {
when (yPadCtrl0.io.done) {
when (dec.xpad_0 =/= 0.U) {
state := sXPad0
- } .otherwise {
+ } .otherwise {
state := sReadCmd
- }
+ }
}
}
is (sXPad0) {
is (sReadData) {
when (io.vme_rd.data.valid) {
when (dataCtrl.io.done) {
- when (dec.xpad_1 =/= 0.U) {
- state := sXPad1
- } .elsewhen (dec.ypad_1 =/= 0.U) {
- state := sYPad1
- } .otherwise {
- state := sIdle
- }
- } .elsewhen (dataCtrl.io.stride || dataCtrl.io.split) {
when (dec.xpad_1 =/= 0.U) {
- state := sXPad1
- } .elsewhen (dec.xpad_0 =/= 0.U) {
+ state := sXPad1
+ } .elsewhen (dec.ypad_1 =/= 0.U) {
+ state := sYPad1
+ } .otherwise {
+ state := sIdle
+ }
+ } .elsewhen (dataCtrl.io.stride || dataCtrl.io.split) {
+ when (dec.xpad_1 =/= 0.U) {
+ state := sXPad1
+ } .elsewhen (dec.xpad_0 =/= 0.U) {
state := sXPad0
- } .otherwise {
+ } .otherwise {
state := sReadCmd
- }
- }
+ }
+ }
}
}
is (sXPad1) {
xPadCtrl0.io.start := dec.xpad_0 =/= 0.U &
((state === sIdle & io.start) |
- (state === sYPad0 & yPadCtrl0.io.done) |
+ (state === sYPad0 & yPadCtrl0.io.done) |
(io.vme_rd.data.fire() & ~dataCtrlDone & (dataCtrl.io.stride | dataCtrl.io.split) & dec.xpad_1 === 0.U) |
- (state === sXPad1 & xPadCtrl1.io.done & ~dataCtrlDone))
+ (state === sXPad1 & xPadCtrl1.io.done & ~dataCtrlDone))
xPadCtrl1.io.start := dec.xpad_1 =/= 0.U & io.vme_rd.data.fire() &
((dataCtrl.io.done) |
// write-to-sram
val isZeroPad = state === sYPad0 |
state === sXPad0 |
- state === sXPad1 |
- state === sYPad1
+ state === sXPad1 |
+ state === sYPad1
when (state === sIdle || state === sReadCmd || tag === (tp.numMemBlock - 1).U) {
tag := 0.U
is (sIdle) {
when (io.start) {
state := sWriteCmd
- when (xsize < xmax) {
+ when (xsize < xmax) {
xlen := xsize
xrem := 0.U
- } .otherwise {
+ } .otherwise {
xlen := xmax - 1.U
xrem := xsize - xmax
- }
+ }
}
}
is (sWriteCmd) {
state := sWriteAck
} .elsewhen (tag === (numMemBlock - 1).U) {
state := sReadMem
- }
+ }
}
}
is (sReadMem) {
is (sWriteAck) {
when (io.vme_wr.ack) {
when (xrem === 0.U) {
- when (ycnt === ysize - 1.U) {
+ when (ycnt === ysize - 1.U) {
state := sIdle
- } .otherwise {
+ } .otherwise {
state := sWriteCmd
- when (xsize < xmax) {
+ when (xsize < xmax) {
xlen := xsize
xrem := 0.U
- } .otherwise {
+ } .otherwise {
xlen := xmax - 1.U
xrem := xsize - xmax
- }
- }
- } .elsewhen (xrem < xmax) {
+ }
+ }
+ } .elsewhen (xrem < xmax) {
state := sWriteCmd
xlen := xrem
xrem := 0.U
- } .otherwise {
+ } .otherwise {
state := sWriteCmd
xlen := xmax - 1.U
xrem := xrem - xmax
- }
+ }
}
}
}
val stride = state === sWriteAck &
io.vme_wr.ack &
xcnt === xlen + 1.U &
- xrem === 0.U &
- ycnt =/= ysize - 1.U
+ xrem === 0.U &
+ ycnt =/= ysize - 1.U
when (state === sIdle) {
ycnt := 0.U
val ycnt = Reg(chiselTypeOf(dec.ysize))
val stride = xcnt === len &
- xrem === 0.U &
- ycnt =/= dec.ysize - 1.U
+ xrem === 0.U &
+ ycnt =/= dec.ysize - 1.U
val split = xcnt === len & xrem =/= 0.U
io.addr := caddr
io.len := len
io.done := xcnt === len &
- xrem === 0.U &
- ycnt === dec.ysize - 1.U
+ xrem === 0.U &
+ ycnt === dec.ysize - 1.U
}
projects / platform / upstream / tvm.git / commitdiff