powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDB
authorPoonam Aggrwal <poonam.aggrwal@freescale.com>
Mon, 7 Feb 2011 11:47:28 +0000 (17:17 +0530)
committerKumar Gala <galak@kernel.crashing.org>
Mon, 4 Apr 2011 14:24:42 +0000 (09:24 -0500)
Changed the following DDR timing parameters for 800Mt/s:
tRRT    BL/2+1 to  BL/2
tWWT    BL/2+1 to  BL/2
tWRT    BL/2+1 to  BL/2
tRWT    BL/2+1 to  BL/2
REFINT  6500ns to  7800ns

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/freescale/p1_p2_rdb/ddr.c

index 853044e..71c6088 100644 (file)
@@ -74,13 +74,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_DDR_INTERVAL_667    0x0a280100
 
 #define CONFIG_SYS_DDR_TIMING_3_800    0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800    0x55770802
+#define CONFIG_SYS_DDR_TIMING_0_800    0x00770802
 #define CONFIG_SYS_DDR_TIMING_1_800    0x6f6b6543
 #define CONFIG_SYS_DDR_TIMING_2_800    0x0fa074d1
 #define CONFIG_SYS_DDR_CLK_CTRL_800    0x02800000
 #define CONFIG_SYS_DDR_MODE_1_800      0x00040852
 #define CONFIG_SYS_DDR_MODE_2_800      0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800    0x0a280100
+#define CONFIG_SYS_DDR_INTERVAL_800    0x0c300100
 
 fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
        .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,