High-16 registers of XMM and YMM need to be encoded with EVEX not VEX.
Even if all the operand types match with VEX instruction format,
it should use EVEX instead.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
MERR_BADCPU,
MERR_BADMODE,
MERR_BADHLE,
+ MERR_ENCMISMATCH,
/*
* Matching success; the conditional ones first
*/
if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
return -1;
+ } else if (!(ins->rex & REX_EV) &&
+ ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
+ errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
+ return -1;
}
if (ins->rex & REX_EV)
length += 4;
*/
opsizemissing = true;
}
+ } else if (instruction->oprs[i].basereg >= 16 &&
+ (itemp->flags & IF_INSMASK) != IF_AVX512) {
+ return MERR_ENCMISMATCH;
}
}