PCI: keystone: Cleanup ks_pcie_msi_irq_handler()

ks_pcie_msi_irq_handler() invokes ks_pcie_handle_msi_irq() for handling
the interrupts.

Having two functions for handling the interrupt was used when keystone
PCIe driver was implemented using two files but with commit b492aca35c98
("PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c"), which
merged the keystone PCIe driver to use a single file, two functions for
handling the interrupt handler are not required.

Handle MSI interrupt in a single interrupt handler here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index fce25a0..39542f2 100644 (file)
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -105,13 +105,6 @@ struct keystone_pcie {
        struct resource         app;
 };
 
-static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
-                                            u32 *bit_pos)
-{
-       *reg_offset = offset % 8;
-       *bit_pos = offset >> 3;
-}
-
 static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp)
 {
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -131,31 +124,6 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
        writel(val, ks_pcie->va_app_base + offset);
 }
 
-static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
-{
-       struct dw_pcie *pci = ks_pcie->pci;
-       struct pcie_port *pp = &pci->pp;
-       struct device *dev = pci->dev;
-       u32 pending, vector;
-       int src, virq;
-
-       pending = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset));
-
-       /*
-        * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
-        * shows 1, 9, 17, 25 and so forth
-        */
-       for (src = 0; src < 4; src++) {
-               if (BIT(src) & pending) {
-                       vector = offset + (src << 3);
-                       virq = irq_linear_revmap(pp->irq_domain, vector);
-                       dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
-                               src, vector, virq);
-                       generic_handle_irq(virq);
-               }
-       }
-}
-
 static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
 {
        u32 reg_offset, bit_pos;
@@ -164,7 +132,9 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
 
        pci = to_dw_pcie_from_pp(pp);
        ks_pcie = to_keystone_pcie(pci);
-       update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
+
+       reg_offset = irq % 8;
+       bit_pos = irq >> 3;
 
        ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset),
                           BIT(bit_pos));
@@ -177,7 +147,9 @@ static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq)
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 
-       update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
+       reg_offset = irq % 8;
+       bit_pos = irq >> 3;
+
        ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset),
                           BIT(bit_pos));
 }
@@ -188,7 +160,9 @@ static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
        struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
 
-       update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
+       reg_offset = irq % 8;
+       bit_pos = irq >> 3;
+
        ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset),
                           BIT(bit_pos));
 }
@@ -556,8 +530,10 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
        struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
        u32 offset = irq - ks_pcie->msi_host_irq;
        struct dw_pcie *pci = ks_pcie->pci;
+       struct pcie_port *pp = &pci->pp;
        struct device *dev = pci->dev;
        struct irq_chip *chip = irq_desc_get_chip(desc);
+       u32 vector, virq, reg, pos;
 
        dev_dbg(dev, "%s, irq %d\n", __func__, irq);
 
@@ -567,7 +543,23 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
         * ack operation.
         */
        chained_irq_enter(chip, desc);
-       ks_pcie_handle_msi_irq(ks_pcie, offset);
+
+       reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset));
+       /*
+        * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
+        * shows 1, 9, 17, 25 and so forth
+        */
+       for (pos = 0; pos < 4; pos++) {
+               if (!(reg & BIT(pos)))
+                       continue;
+
+               vector = offset + (pos << 3);
+               virq = irq_linear_revmap(pp->irq_domain, vector);
+               dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector,
+                       virq);
+               generic_handle_irq(virq);
+       }
+
        chained_irq_exit(chip, desc);
 }