[(set_attr "type" "load,*")])
(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
""
"")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lux %3,%1,%2
- lu %3,%2(%1)"
+ lux %3,%0,%2
+ lu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- stux %3,%1,%2
- stu %3,%2(%1)")
+ stux %3,%0,%2
+ stu %3,%2(%0)")
(define_insn ""
[(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lhzux %3,%1,%2
- lhzu %3,%2(%1)"
+ lhzux %3,%0,%2
+ lhzu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lhzux %3,%1,%2
- lhzu %3,%2(%1)"
+ lhzux %3,%0,%2
+ lhzu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lhaux %3,%1,%2
- lhau %3,%2(%1)"
+ lhaux %3,%0,%2
+ lhau %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- sthux %3,%1,%2
- sthu %3,%2(%1)"
+ sthux %3,%0,%2
+ sthu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lbzux %3,%1,%2
- lbzu %3,%2(%1)"
+ lbzux %3,%0,%2
+ lbzu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lbzux %3,%1,%2
- lbzu %3,%2(%1)"
+ lbzux %3,%0,%2
+ lbzu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- stbux %3,%1,%2
- stbu %3,%2(%1)")
+ stbux %3,%0,%2
+ stbu %3,%2(%0)")
(define_insn ""
[(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lfsux %3,%1,%2
- lfsu %3,%2(%1)"
+ lfsux %3,%0,%2
+ lfsu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- frsp %3,%3\;stfsux %3,%1,%2
- frsp %3,%3\;stfsu %3,%2(%1)")
+ frsp %3,%3\;stfsux %3,%0,%2
+ frsp %3,%3\;stfsu %3,%2(%0)")
(define_insn ""
[(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- lfdux %3,%1,%2
- lfdu %3,%2(%1)"
+ lfdux %3,%0,%2
+ lfdu %3,%2(%0)"
[(set_attr "type" "load,load")])
(define_insn ""
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
- stfdux %3,%1,%2
- stfdu %3,%2(%1)")
+ stfdux %3,%0,%2
+ stfdu %3,%2(%0)")
\f
;; Next come insns related to the calling sequence.
;;
bl %z0\;cror 15,15,15")
(define_insn ""
- [(set (match_operand 0 "" "fg,fg")
+ [(set (match_operand 0 "" "=fg,fg")
(call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
(match_operand 2 "" "fg,fg")))
(clobber (match_scratch:SI 3 "=l,l"))]