[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
},
{
"BriefDescription": "L1D miss outstanding duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
},
{
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "Not rejected writebacks that hit L2 cache.",
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "L2 cache lines in E state filling L2.",
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "L2 cache lines in I state filling L2.",
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "L2 cache lines in S state filling L2.",
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"PublicDescription": "Clean L2 cache lines evicted by demand.",
},
{
"BriefDescription": "Dirty L2 cache lines evicted by demand",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_DIRTY",
"PublicDescription": "Dirty L2 cache lines evicted by demand.",
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts all L2 code requests.",
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
},
{
"BriefDescription": "Demand requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts all L2 HW prefetcher requests.",
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts all L2 store RFO requests.",
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
},
{
"BriefDescription": "All requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "Transactions accessing L2 pipe.",
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "L2 cache accesses when fetching instructions.",
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "Demand data read requests that access L2 cache.",
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "L1D writebacks that access L2 cache.",
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "L2 fill requests that access L2 cache.",
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "L2 writebacks that access L2 cache.",
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "RFO requests that access L2 cache.",
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D is locked.",
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD2",
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM30",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD3",
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD76, HSD29, HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"EventCode": "0xD1",
},
{
"BriefDescription": "Retired load uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
},
{
"BriefDescription": "Retired store uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts all retired store uops.",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Retired load uops with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD76, HSD29, HSM30",
"EventCode": "0xD0",
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "HSD29, HSM30",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "100003",
"UMask": "0x12"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
},
{
"BriefDescription": "Cacheable and noncacheable code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Demand code read requests sent to uncore.",
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSM80",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "HSD78, HSD62, HSD61, HSM63, HSM80",
"EventCode": "0x60",
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD62, HSD61, HSM63",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
[
{
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC6",
"EventName": "AVX_INSTS.ALL",
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "Number of SIMD FP assists due to input values.",
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "Number of SIMD FP assists due to output values.",
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "Number of X87 FP assists due to input values.",
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "Number of X87 FP assists due to output values.",
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD56, HSM57",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Number of front end re-steers due to BPU misprediction.",
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFETCH_STALL",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "Number of uops delivered to IDQ from any path.",
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD135",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD135",
"EventCode": "0x9C",
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD135",
"EventCode": "0x9C",
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD135",
"EventCode": "0x9C",
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD135",
"EventCode": "0x9C",
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
- "MetricExpr": "ICACHE.IFDATA_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "4 * CORE_CLKS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "0",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "RESOURCE_STALLS.SB / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "tma_backend_bound - tma_memory_bound",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cbox_0@event\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if (IPC > 1.8) else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
- "ScaleUnit": "100%"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_2",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_4",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_7",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "tma_retiring - tma_heavy_operations",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "tma_microcode_sequencer",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time",
+ "MetricName": "qpi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "4 * CORE_CLKS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)) if #SMT_on else UOPS_EXECUTED.CORE / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "(UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_loop_stream_detector",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "0",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cbox_0@event\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "tma_backend_bound - tma_memory_bound",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_2",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_3",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+ "MetricExpr": "tma_store_op_utilization",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_4",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "qpi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_7",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "tma_heavy_operations",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_heavy_operations - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "C3 residency percent per core",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS ) / UOPS_ISSUED.ANY",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_loop_stream_detector",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "C7 residency percent per core",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "C3 residency percent per package",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
+ },
+ {
+ "BriefDescription": "C7 residency percent per package",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
[
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD65",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).",
},
{
"BriefDescription": "Number of times an HLE execution successfully committed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.START",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.",
},
{
"BriefDescription": "Randomly selected loads with latency value being above 128.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x80",
"PEBS": "2",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 16.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x10",
"PEBS": "2",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 256.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x100",
"PEBS": "2",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 32.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x20",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 4.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x4",
"PEBS": "2",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 512.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x200",
"PEBS": "2",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 64.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x40",
"PEBS": "2",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 8.",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "HSD76, HSD25, HSM26",
"EventCode": "0xcd",
"MSRValue": "0x8",
"PEBS": "2",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.",
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63F800091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6004007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63F8007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x600400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00040",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD65",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
},
{
"BriefDescription": "Number of times an RTM execution successfully committed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.START",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"SampleAfterValue": "2000003",
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
[
{
"BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_UOPS",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
},
{
"BriefDescription": "Speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Not taken macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired direct near calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "Branch instructions at retirement.",
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PublicDescription": "Number of far branches retired.",
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "Counts the number of not taken branch instructions retired.",
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "Counts all near executed branches (not necessarily retired).",
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"SampleAfterValue": "200003",
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Mispredicted branch instructions at retirement.",
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
},
{
"BriefDescription": "Core cycles when the thread is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
"SampleAfterValue": "2000003",
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.",
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles with pending L1 cache miss loads.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
},
{
"BriefDescription": "Cycles with pending L2 cache miss loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD78, HSM63, HSM80",
"EventCode": "0xa3",
},
{
"BriefDescription": "Cycles with pending memory loads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
},
{
"BriefDescription": "Execution stalls due to L1 data cache misses",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
},
{
"BriefDescription": "Execution stalls due to L2 cache misses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"Errata": "HSM63, HSM80",
"EventCode": "0xa3",
},
{
"BriefDescription": "Execution stalls due to memory subsystem.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
},
{
"BriefDescription": "Stall cycles because IQ is full",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.IQ_FULL",
"PublicDescription": "Stall cycles due to IQ is full.",
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).",
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"Errata": "HSD140, HSD143",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD11, HSD140",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "HSD140",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
},
{
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
},
{
"BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.",
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.",
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.",
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.",
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered by the LSD.",
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
},
{
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.",
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"PublicDescription": "Number of integer move elimination candidate uops that were eliminated.",
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.",
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.",
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD135",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.",
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Count cases of saving new LBR records by hardware.",
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.",
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD30, HSM31",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "HSD30, HSM31",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"Errata": "HSD144, HSD30, HSM31",
"EventCode": "0xB1",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are executed in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.",
{
"AnyThread": "1",
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
},
{
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"PublicDescription": "Number of multiply packed/scalar single precision uops allocated.",
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.",
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
},
{
"BriefDescription": "Actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
{
"AnyThread": "1",
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.CORE_STALL_CYCLES",
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
[
{
- "BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_C_BOUNCE_CONTROL",
+ "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
+ "Filter": "filter_opc=0x191",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_C_CLOCKTICKS",
+ "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
+ "Filter": "filter_opc=0x192",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+ "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.DATA_READ",
+ "Filter": "filter_opc=0x182",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "FaST wire asserted",
- "Counter": "0,1",
- "EventCode": "0x9",
- "EventName": "UNC_C_FAST_ASSERTED",
+ "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_READ",
+ "Filter": "filter_opc=0x187,filter_nc=1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_WRITE",
+ "Filter": "filter_opc=0x18f,filter_nc=1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+ "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
+ "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_READ",
+ "Filter": "filter_opc=0x19e",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_WRITE",
+ "Filter": "filter_opc=0x1c8",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
+ "Filter": "filter_opc=0x190",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.UNCACHEABLE",
+ "Filter": "filter_opc=0x187",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
+ "Filter": "filter_opc=0x181",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
+ "Filter": "filter_opc=0x180,filter_tid=0x3e",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_READ",
+ "Filter": "filter_opc=0x19e",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_WRITE",
+ "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_FULL",
+ "Filter": "filter_opc=0x18c",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+ "Filter": "filter_opc=0x18d",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Bounce Control",
+ "EventCode": "0xA",
+ "EventName": "UNC_C_BOUNCE_CONTROL",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Uncore Clocks",
+ "EventName": "UNC_C_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "FaST wire asserted",
+ "EventCode": "0x9",
+ "EventName": "UNC_C_FAST_ASSERTED",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.",
"Unit": "CBO"
},
{
"BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.ANY",
"Filter": "filter_state=0x1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
"ScaleUnit": "64Bytes",
"UMask": "0x11",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Cache Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Cache Lookups; Lookups that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
"UMask": "0x41",
"Unit": "CBO"
},
{
"BriefDescription": "Cache Lookups; Any Read Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.READ",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
"UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "M line evictions from LLC (writebacks to memory)",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "Cache Lookups; External Snoop Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+ "UMask": "0x9",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "Cache Lookups; Write Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.",
+ "UMask": "0x5",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines in S State",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Lines Victimized; Lines in E state",
"EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+ "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Lines Victimized; Lines in S State",
"EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.NID",
+ "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "M line evictions from LLC (writebacks to memory)",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.NID",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x40",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.WC_ALIASING",
+ "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.STARTED",
+ "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+ "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cbo Misc",
"EventCode": "0x39",
- "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+ "EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.WC_ALIASING",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE0",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 0",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE1",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 1",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 2",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE2",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 2",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Age 3",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE3",
"PerPkg": "1",
+ "PublicDescription": "How often age was set to 3",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; LRU Bits Decremented",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.LRU_DECREMENT",
"PerPkg": "1",
+ "PublicDescription": "How often all LRU bits were decremented by 1",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "LRU Queue; Non-0 Aged Victim",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
"PerPkg": "1",
+ "PublicDescription": "How often we picked a victim that had a non-zero age",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; All",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_AD_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Down",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+ "EventName": "UNC_C_RING_AD_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Even",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.DOWN",
+ "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Odd",
"EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.ALL",
+ "EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; All",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_AK_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Down",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+ "EventName": "UNC_C_RING_AK_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Even",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.DOWN",
+ "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Odd",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.ALL",
+ "EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+ "EventName": "UNC_C_RING_BL_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Even",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.DOWN",
+ "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Odd",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.ALL",
+ "EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AD",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL",
"PerPkg": "1",
"Unit": "CBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_C_RING_IV_USED.UP",
+ "EventName": "UNC_C_RING_IV_USED.DN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DOWN",
"PerPkg": "1",
- "UMask": "0xCC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_C_RING_IV_USED.DN",
+ "EventName": "UNC_C_RING_IV_USED.UP",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
"BriefDescription": "UNC_C_RING_SINK_STARVED.AD",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "UNC_C_RING_SINK_STARVED.AK",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AK",
"PerPkg": "1",
"Unit": "CBO"
},
{
- "BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
"EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.IV",
+ "EventName": "UNC_C_RING_SINK_STARVED.BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "UNC_C_RING_SINK_STARVED.BL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "UNC_C_RING_SINK_STARVED.IV",
"EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.BL",
+ "EventName": "UNC_C_RING_SINK_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
"EventCode": "0x7",
"EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+ "EventCode": "0x12",
+ "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
"EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+ "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.",
"UMask": "0x4",
"Unit": "CBO"
},
- {
- "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+ {
+ "BriefDescription": "Ingress Allocations; IPQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_C_RxR_INSERTS.IPQ",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
"EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
+ "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
"EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+ "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
"UMask": "0x10",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Probe Queue Retries; Address Conflict",
+ "EventCode": "0x31",
+ "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+ "EventCode": "0x32",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No IIO Credits",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No QPI Credits",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No RTIDs",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x80",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Occupancy; IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Occupancy; IRQ",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Occupancy; IPQ",
+ "BriefDescription": "Ingress Occupancy; IRQ Rejected",
"EventCode": "0x11",
- "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+ "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x20",
"Unit": "CBO"
},
{
"BriefDescription": "SBo Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "SBo Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x2",
"Unit": "CBO"
},
"EventCode": "0x3E",
"EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x1",
"Unit": "CBO"
},
"EventCode": "0x3E",
"EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.OPCODE",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
- "Filter": "filter_opc=0x180,filter_tid=0x3e",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
- "Filter": "filter_opc=0x181",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_FULL",
- "Filter": "filter_opc=0x18c",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
- "Filter": "filter_opc=0x18d",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_READ",
- "Filter": "filter_opc=0x19e",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_WRITE",
- "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.EVICTION",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "TOR Inserts; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WB",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.DATA_READ",
- "Filter": "filter_opc=0x182",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.UNCACHEABLE",
- "Filter": "filter_opc=0x187",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_READ",
- "Filter": "filter_opc=0x187,filter_nc=1",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_WRITE",
- "Filter": "filter_opc=0x18f,filter_nc=1",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Evictions",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
- "Filter": "filter_opc=0x190",
+ "EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Local Memory",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
- "Filter": "filter_opc=0x191",
+ "EventName": "UNC_C_TOR_INSERTS.LOCAL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x28",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
- "Filter": "filter_opc=0x192",
+ "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Local Memory",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_READ",
- "Filter": "filter_opc=0x19e",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
- "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_WRITE",
- "Filter": "filter_opc=0x1c8",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x23",
"Unit": "CBO"
},
{
- "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Miss Opcode Match",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
- "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Remote Memory",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x83",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
"UMask": "0x48",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Evictions",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_WB",
+ "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
- "UMask": "0x50",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+ "UMask": "0x44",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Miss All",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
- "UMask": "0x43",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+ "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
- "UMask": "0x4A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+ "UMask": "0x43",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Local Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID and Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+ "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
- "UMask": "0x2A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
+ "UMask": "0x41",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Remote Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Writebacks",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+ "EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
- "UMask": "0x8A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.",
+ "UMask": "0x50",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Local Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Opcode Match",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+ "EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
- "UMask": "0x28",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Remote Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.",
"UMask": "0x88",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
- "PerPkg": "1",
- "UMask": "0x23",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
- "PerPkg": "1",
- "UMask": "0x83",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x81",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Writebacks",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
- "UMask": "0x81",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Opcode Match",
+ "BriefDescription": "TOR Occupancy; Any",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Any",
+ "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
+ "Filter": "filter_opc=0x182",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x28",
"Unit": "CBO"
},
{
- "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch)",
+ "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x21",
"Unit": "CBO"
},
{
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0xa",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID Matched Evictions",
+ "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
"PerPkg": "1",
- "UMask": "0x44",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.",
+ "UMask": "0x23",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID Matched",
+ "BriefDescription": "TOR Occupancy; Miss Opcode Match",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
"PerPkg": "1",
- "UMask": "0x48",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
"PerPkg": "1",
- "UMask": "0x43",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x8a",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+ "PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.",
+ "UMask": "0x83",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Occupancy; NID Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
"PerPkg": "1",
- "UMask": "0x4A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x48",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID Matched Evictions",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
"PerPkg": "1",
- "UMask": "0x2A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
+ "UMask": "0x44",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
- "UMask": "0x8A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
"PerPkg": "1",
- "UMask": "0x28",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
+ "UMask": "0x43",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
"PerPkg": "1",
- "UMask": "0x88",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+ "UMask": "0x41",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
+ "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
"PerPkg": "1",
- "UMask": "0x23",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+ "UMask": "0x50",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
+ "BriefDescription": "TOR Occupancy; Opcode Match",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
"PerPkg": "1",
- "UMask": "0x83",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x88",
"Unit": "CBO"
},
{
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.",
"UMask": "0x81",
"Unit": "CBO"
},
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.WB",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.",
"UMask": "0x10",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
- "PerPkg": "1",
- "UMask": "0x50",
- "Unit": "CBO"
- },
{
"BriefDescription": "Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AK",
"PerPkg": "1",
},
{
"BriefDescription": "Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.BL",
"PerPkg": "1",
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AD - Corebo",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
+ "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AK - Cachebo",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.AD_CORE",
+ "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; BL - Cacheno",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
+ "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
+ "BriefDescription": "Egress Allocations; BL - Corebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
- "BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.IV",
+ "BriefDescription": "Egress Allocations; IV - Cachebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AD_CORE",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Occupancy; IRQ Rejected",
- "EventCode": "0x11",
- "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
+ "BriefDescription": "Injection Starvation; Onto AK Ring",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.AK_BOTH",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+ "BriefDescription": "Injection Starvation; Onto BL Ring",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.BL_BOTH",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Address",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
+ "BriefDescription": "Injection Starvation; Onto IV Ring",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
"UMask": "0x8",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "HA"
+ "Unit": "CBO"
},
{
"BriefDescription": "BT Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
"EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
"EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Bypass; Not Taken",
"EventCode": "0x14",
- "EventName": "UNC_H_BYPASS_IMC.TAKEN",
+ "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Bypass; Taken",
"EventCode": "0x14",
- "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
+ "EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
"Unit": "HA"
},
{
"BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
+ "PublicDescription": "Number of Direct2Core messages sent",
"Unit": "HA"
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles in which Direct2Core was disabled",
"Unit": "HA"
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
+ "PublicDescription": "Number of Reads where Direct2Core overridden",
"Unit": "HA"
},
{
"BriefDescription": "Directory Lat Opt Return",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_H_DIRECTORY_LAT_OPT",
"PerPkg": "1",
+ "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Lookups; Snoop Not Needed",
"EventCode": "0xC",
- "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
+ "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Lookups; Snoop Needed",
"EventCode": "0xC",
- "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
+ "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Updates; Any Directory Update",
"EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Directory Updates; Directory Set",
"EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+ "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.WBMTOI",
+ "EventName": "UNC_H_HITME_HIT.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+ "EventName": "UNC_H_HITME_HIT.ALLOCS",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x70",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+ "EventName": "UNC_H_HITME_HIT.EVICTS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x42",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+ "EventName": "UNC_H_HITME_HIT.HOM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+ "EventName": "UNC_H_HITME_HIT.INVALS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x26",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+ "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSP",
"PerPkg": "1",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ALLOCS",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
"PerPkg": "1",
- "UMask": "0x70",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.EVICTS",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x42",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.INVALS",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDS",
"PerPkg": "1",
- "UMask": "0x26",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ALL",
+ "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
"EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.HOM",
+ "EventName": "UNC_H_HITME_HIT.WBMTOI",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "HA"
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
"PerPkg": "1",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
"EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+ "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+ "EventName": "UNC_H_HITME_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+ "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x70",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+ "EventName": "UNC_H_HITME_LOOKUP.HOM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+ "EventName": "UNC_H_HITME_LOOKUP.INVALS",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x26",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+ "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSP",
"PerPkg": "1",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
"PerPkg": "1",
- "UMask": "0x70",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x26",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ALL",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
"EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.HOM",
+ "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
"EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
"EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x20",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_H_IMC_READS.NORMAL",
"PerPkg": "1",
+ "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.FULL",
+ "EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+ "EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+ "EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
"EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.ALL",
+ "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
- "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+ "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
- "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+ "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS2",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS3",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Local Reads",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Cancelled",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.READS_LOCAL",
+ "EventName": "UNC_H_OSB.CANCELLED",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.INVITOE_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Remote",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Local Reads",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.REMOTE",
+ "EventName": "UNC_H_OSB.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Cancelled",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.CANCELLED",
+ "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Snoop Broadcast; Remote",
"EventCode": "0x53",
- "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+ "EventName": "UNC_H_OSB.REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE_USEFUL",
"PerPkg": "1",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
"UMask": "0x40",
"Unit": "HA"
},
{
"BriefDescription": "OSB Early Data Return; All",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Remote I",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Early Data Return; Reads to Local S",
"EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+ "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Local S",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OSB Early Data Return; Reads to Remote I",
"EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+ "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Read and Write Requests; Local InvItoEs",
"EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.READS",
+ "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Read and Write Requests; Remote InvItoEs",
"EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.WRITES",
+ "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+ "UMask": "0x20",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Read and Write Requests; Reads",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs).",
+ "UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Remote Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Read and Write Requests; Writes",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.WRITES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+ "UMask": "0xc",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Read and Write Requests; Local Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Remote Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
"UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Local InvItoEs",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Read and Write Requests; Remote InvItoEs",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AD Ring in Use; Counterclockwise",
"EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_H_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
"EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CCW",
+ "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AK Ring in Use; Counterclockwise",
"EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_H_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
"EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CCW",
+ "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA BL Ring in Use; Counterclockwise",
"EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_H_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
"EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CCW",
+ "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Data beat the Snoop Responses; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Data beat the Snoop Responses; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+ "EventCode": "0x8",
+ "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
- {
- "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Snoop Responses Received; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
"UMask": "0x1",
"Unit": "HA"
},
+ {
+ "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Shared line response from remote cache",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"ScaleUnit": "64Bytes",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Shared line forwarded from remote cache",
"EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
"ScaleUnit": "64Bytes",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Shared line forwarded from remote cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
"EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"ScaleUnit": "64Bytes",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "HA"
},
{
"BriefDescription": "Snoop Responses Received; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "Snoop Responses Received Local; Other",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x20",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for all other snoop responses.",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "HA"
},
{
"BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
"UMask": "0x1",
"Unit": "HA"
},
- {
- "BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
{
"BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Snoop Responses Received Local; RspS",
"EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Snoop Responses Received Local; RspSFwd",
"EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
"UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Snoop Responses Received Local; Other",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
"EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
"UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
"UMask": "0x20",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
"UMask": "0x40",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
"UMask": "0x80",
"Unit": "HA"
},
+ {
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+ "UMask": "0x8",
+ "Unit": "HA"
+ },
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+ "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+ "EventCode": "0x2",
+ "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries. It will not return valid count when BT is disabled.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+ "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+ "EventCode": "0x2",
+ "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used. It will not return valid count when BT is disabled.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+ "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+ "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
+ {
+ "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x40",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x80",
+ "Unit": "HA"
+ },
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x10",
"Unit": "HA"
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
"UMask": "0x20",
"Unit": "HA"
},
- {
- "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "HA"
- },
{
"BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_H_TxR_AD.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for non-data response and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets.",
"UMask": "0x4",
"Unit": "HA"
},
+ {
+ "BriefDescription": "AD Egress Full; All",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
{
"BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Full; Filter for cycles full from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Full; Filter for cycles full from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+ "BriefDescription": "AD Egress Not Empty; All",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+ "BriefDescription": "AD Egress Allocations; All",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+ "BriefDescription": "AK Egress Full; All",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Filter for cycles full from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Filter for cycles full from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "AK Egress Not Empty; All",
+ "EventCode": "0x31",
+ "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+ "BriefDescription": "AK Egress Allocations; All",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
- {
- "BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
"UMask": "0x4",
"Unit": "HA"
},
+ {
+ "BriefDescription": "BL Egress Full; All",
+ "EventCode": "0x36",
+ "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
{
"BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Filter for cycles full from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Filter for cycles full from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x36",
- "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "BL Egress Not Empty; All",
+ "EventCode": "0x35",
+ "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+ "BriefDescription": "BL Egress Allocations; All",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
- {
- "BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
{
"BriefDescription": "Injection Starvation; For AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "Injection Starvation; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Tracker Cycles Not Empty; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
}
]
[
+ {
+ "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
+ "EventName": "QPI_CTL_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
+ "ScaleUnit": "8Bytes",
+ "UMask": "0x4",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
+ "EventName": "QPI_DATA_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
+ "ScaleUnit": "8Bytes",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Number of qfclks",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Count of CTO Events",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
- "ExtSel": "1",
"PerPkg": "1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
- "PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
"UMask": "0x8",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+ "EventCode": "0x13",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+ "UMask": "0x80",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+ "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
"Unit": "QPI LL"
},
{
"BriefDescription": "CRC Errors Detected; LinkInit",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
"PerPkg": "1",
+ "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "CRC Errors Detected; Normal Operations",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
"PerPkg": "1",
+ "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "VN0 Credit Consumed; HOM",
+ "EventCode": "0x1E",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "VN0 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN0 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN0 Credit Consumed; NDR",
"EventCode": "0x1E",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN0 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
- "ExtSel": "1",
+ "BriefDescription": "VN1 Credit Consumed; DRS",
+ "EventCode": "0x39",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN1 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN1 Credit Consumed; HOM",
"EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN1 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN1 Credit Consumed; NDR",
"EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "VN1 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.",
+ "UMask": "0x18",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_Q_RxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
"UMask": "0x6",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 1; SNP Flits",
"EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x18",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
"EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
"EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
"EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_Q_RxL_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
"EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_Q_RxL_STALLS_VN0.GV",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
"UMask": "0x80",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
"EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_TxL0P_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_Q_TxL0_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_Q_TxL_BYPASSED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
"EventCode": "0x2",
- "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
+ "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
"EventCode": "0x2",
- "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+ "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Cycles not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.DATA",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
- "Counter": "0,1,2,3",
- "EventName": "QPI_DATA_BANDWIDTH_TX",
- "PerPkg": "1",
- "ScaleUnit": "8Bytes",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
- "Counter": "0,1,2,3",
- "EventName": "QPI_CTL_BANDWIDTH_TX",
- "PerPkg": "1",
- "ScaleUnit": "8Bytes",
- "UMask": "0x4",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.",
+ "UMask": "0x18",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.HOM",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
"UMask": "0x6",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
- "UMask": "0x18",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
+ "EventCode": "0x1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Returned",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of VNA credits returned.",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "QPI LL"
}
]
[
{
- "BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.RD",
+ "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_READ",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.WR",
+ "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_WRITE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x8",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Read",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.RD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Write",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.WR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
"UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_READ",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR",
+ "EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_WRITE",
+ "EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0xC",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.ALL",
+ "EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+ "EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+ "BriefDescription": "DRAM Clockticks",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_CLOCKTICKS",
+ "EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.READ",
+ "EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.WRITE",
+ "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+ "EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+ "EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
"Unit": "iMC"
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M_POWER_PCU_THROTTLING",
"PerPkg": "1",
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
"EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.BYP",
+ "BriefDescription": "Read CAS issued with HIGH priority",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
- {
- "BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANK0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 4",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB4",
"EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB5",
"EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 1",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"Unit": "iMC"
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
"EventCode": "0x90",
- "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+ "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
"EventCode": "0x90",
- "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+ "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
"UMask": "0x3",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
"UMask": "0x7",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+ "PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
"UMask": "0x9",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
- "PerPkg": "1",
- "UMask": "0xA",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
- "PerPkg": "1",
- "UMask": "0xB",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
- "PerPkg": "1",
- "UMask": "0xD",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
- "PerPkg": "1",
- "UMask": "0xE",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
"EventCode": "0xB9",
- "EventName": "UNC_M_WR_CAS_RANK1.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK1.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 1",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 2",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 3",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 4",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 5",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 6",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 7",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 8",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 4; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 4; Bank 9",
"EventCode": "0xBC",
- "EventName": "UNC_M_WR_CAS_RANK4.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK4.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "UNC_M_WR_CAS_RANK4.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 1",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 2",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 3",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 4",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 5",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 6",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 7",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 8",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 5; Bank 9",
"EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK5.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBD",
"EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : All Banks",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)",
"UMask": "0x14",
"Unit": "iMC"
- },
- {
- "BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_DCLOCKTICKS",
- "PerPkg": "1",
- "Unit": "iMC"
}
]
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Number of clocks in the IRP.",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; CLFlush",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; RFO",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; PCIDCAHin5t",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; PCIRdCur",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; RFO",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_MISC0.FAST_REQ",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
"EventCode": "0x14",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
"UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
"EventCode": "0x14",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
+ "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_MISC0.PF_TIMEOUT",
+ "PerPkg": "1",
+ "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut",
+ "UMask": "0x80",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Data Throttled",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "IRP throttled switch data",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Received Invalid",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Received Valid",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Data Throttled",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Hit E or S",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Snoop Responses : Hit E or S",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : Hit I",
"UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Hit M",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Snoop Responses : Hit M",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Miss",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Snoop Responses : Miss",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : SnpCode",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : SnpData",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
+ "PublicDescription": "Snoop Responses : SnpInv",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Atomic",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.READS",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Other",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
"UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Write Prefetches",
- "Counter": "0,1",
- "EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Reads",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Writes",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Select Source",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Write Prefetches",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_MISC0.PF_TIMEOUT",
- "PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x8",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
- "Counter": "0,1",
+ "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CCW",
+ "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "AK Ingress Bounced; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+ "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x7",
+ "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "AK Ingress Bounced; Up",
+ "EventCode": "0x12",
+ "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
"EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
"EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CCW",
+ "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x8",
+ "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CCW",
+ "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x9",
+ "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2 IV Ring in Use; Any",
"EventCode": "0xA",
- "EventName": "UNC_R2_RING_IV_USED.CW",
+ "EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 IV Ring in Use; Clockwise",
"EventCode": "0xA",
- "EventName": "UNC_R2_RING_IV_USED.ANY",
+ "EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
"EventCode": "0x13",
"EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
"EventCode": "0x2A",
"EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
"EventCode": "0x2A",
"EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
"UMask": "0x2",
"Unit": "R2PCIe"
},
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue",
"UMask": "0x2",
"Unit": "R2PCIe"
},
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; AK CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
+ "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "AK CounterClockwise Egress Queue",
+ "UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
+ "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+ "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "AD Clockwise Egress Queue",
+ "UMask": "0x20",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
+ "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
+ "UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0xB",
- "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
+ "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0xB",
- "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
+ "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0xD",
"EventName": "UNC_R3_IOT_CTS_HI.CTS2",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0xD",
"EventName": "UNC_R3_IOT_CTS_HI.CTS3",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0xC",
"EventName": "UNC_R3_IOT_CTS_LO.CTS0",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0xC",
"EventName": "UNC_R3_IOT_CTS_LO.CTS1",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
- "EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CCW",
+ "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
- "EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x7",
+ "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CCW",
+ "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
- "EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x8",
+ "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CCW",
+ "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 IV Ring in Use; Clockwise",
- "Counter": "0,1,2",
- "EventCode": "0xA",
- "EventName": "UNC_R3_RING_IV_USED.CW",
+ "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x9",
+ "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 IV Ring in Use; Any",
- "Counter": "0,1,2",
"EventCode": "0xA",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xf",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "R3 IV Ring in Use; Clockwise",
+ "EventCode": "0xA",
+ "EventName": "UNC_R3_RING_IV_USED.CW",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ring Stop Starved; AK",
- "Counter": "0,1,2",
"EventCode": "0xE",
"EventName": "UNC_R3_RING_SINK_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "Ingress Cycles Not Empty; NDR",
+ "EventCode": "0x10",
+ "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
+ "EventCode": "0x14",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
+ "BriefDescription": "Ingress Allocations; DRS",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; HOM",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "Ingress Allocations; SNP",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.SNP",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "Ingress Allocations; NDR",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.NDR",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "Ingress Allocations; DRS",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.DRS",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; HOM",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+ "BriefDescription": "Ingress Allocations; NDR",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; SNP",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
+ "BriefDescription": "Ingress Allocations; SNP",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; NDR",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Allocations; DRS",
"EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; DRS",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Allocations; HOM",
"EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
- "EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
+ "BriefDescription": "VN1 Ingress Allocations; NDR",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
- "EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+ "BriefDescription": "VN1 Ingress Allocations; SNP",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
"EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
"EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+ "EventCode": "0x13",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
+ "EventCode": "0x13",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
"EventCode": "0x2A",
"EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
"EventCode": "0x2A",
"EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
"EventCode": "0x2B",
"EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
"EventCode": "0x2B",
"EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"EventCode": "0x2C",
- "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AD",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
- "EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.DN_BL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AK",
"PerPkg": "1",
+ "PublicDescription": "AK CounterClockwise Egress Queue",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.UP_AD",
+ "EventName": "UNC_R3_TxR_NACK.DN_BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; AK CCW",
"EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.UP_BL",
+ "EventName": "UNC_R3_TxR_NACK.UP_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.UP_AK",
"PerPkg": "1",
+ "PublicDescription": "AD Clockwise Egress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
+ "EventCode": "0x26",
+ "EventName": "UNC_R3_TxR_NACK.UP_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
"EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
"EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+ "EventCode": "0x37",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+ "EventCode": "0x37",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Used; DRS Message Class",
"EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Used; HOM Message Class",
"EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+ "BriefDescription": "VN0 Credit Used; NDR Message Class",
+ "EventCode": "0x36",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+ "BriefDescription": "VN0 Credit Used; SNP Message Class",
+ "EventCode": "0x36",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
"EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
"EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+ "EventCode": "0x39",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+ "EventCode": "0x39",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Used; DRS Message Class",
"EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Used; HOM Message Class",
"EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "VN1 Credit Used; NDR Message Class",
+ "EventCode": "0x38",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Credit Used; SNP Message Class",
+ "EventCode": "0x38",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; HOM Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; DRS Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; SNP Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; HOM Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NCB Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NCS Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NCB Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NDR Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NCS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; SNP Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_S_BOUNCE_CONTROL",
"PerPkg": "1",
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_S_CLOCKTICKS",
"PerPkg": "1",
"Unit": "SBO"
},
{
"BriefDescription": "FaST wire asserted",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_S_FAST_ASSERTED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "SBO"
- },
- {
- "BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Down",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+ "EventName": "UNC_S_RING_AD_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Even",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.DOWN",
+ "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
+ "BriefDescription": "AD Ring In Use; Up and Odd",
+ "EventCode": "0x1B",
+ "EventName": "UNC_S_RING_AD_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Down",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+ "EventName": "UNC_S_RING_AK_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Even",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.DOWN",
+ "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+ "BriefDescription": "AK Ring In Use; Up and Odd",
+ "EventCode": "0x1C",
+ "EventName": "UNC_S_RING_AK_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP_ODD",
+ "EventName": "UNC_S_RING_BL_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP",
+ "EventName": "UNC_S_RING_BL_USED.UP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x3",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "BL Ring in Use; Up and Even",
+ "EventCode": "0x1D",
+ "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Odd",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.DOWN",
+ "EventName": "UNC_S_RING_BL_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
"Unit": "SBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_S_RING_IV_USED.UP",
+ "EventName": "UNC_S_RING_IV_USED.DN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_S_RING_IV_USED.DN",
+ "EventName": "UNC_S_RING_IV_USED.UP",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0x3",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
"PerPkg": "1",
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
"PerPkg": "1",
},
{
"BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
- {
- "BriefDescription": "Injection Starvation; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "SBO"
- },
{
"BriefDescription": "Injection Starvation; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; AD - Credits",
"EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Injection Starvation; BL - Credits",
+ "EventCode": "0x15",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Bypass; AD - Credits",
"EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x1",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "Bypass; AK",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.AK",
+ "PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Bypass; BL - Credits",
"EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AK",
+ "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Bypass; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_S_RxR_BYPASS.IV",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x20",
"Unit": "SBO"
},
- {
- "BriefDescription": "Injection Starvation; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "SBO"
- },
{
"BriefDescription": "Injection Starvation; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; AD - Credits",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; AK",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; BL - Bounces",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AK",
+ "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Injection Starvation; BL - Credits",
"EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.IV",
+ "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; IVF Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_S_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
"UMask": "0x40",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Injection Starvation; IV",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; AD - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Allocations; AD - Credits",
"EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
+ "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x1",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "Ingress Allocations; AK",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.AK",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Allocations; BL - Credits",
"EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AK",
+ "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Allocations; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_S_RxR_INSERTS.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AD - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; AD - Bounces",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AD - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; AD - Credits",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; AK",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Occupancy; BL - Credits",
"EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AK",
+ "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Ingress Occupancy; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_S_RxR_OCCUPANCY.IV",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.AD",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.AD",
"PerPkg": "1",
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.AK",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.AK",
"PerPkg": "1",
},
{
"BriefDescription": "UNC_S_TxR_ADS_USED.BL",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_S_TxR_ADS_USED.BL",
"PerPkg": "1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AD - Bounces",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
+ "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AD - Credits",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
+ "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AK",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
+ "EventName": "UNC_S_TxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; BL - Credits",
"EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AK",
+ "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Allocations; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_S_TxR_INSERTS.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AD - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; AD - Bounces",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AD - Bounces",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; AD - Credits",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; BL - Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; AK",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; BL - Bounces",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Occupancy; BL - Credits",
"EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AK",
+ "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Egress Occupancy; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_S_TxR_OCCUPANCY.IV",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x8",
"Unit": "SBO"
},
+ {
+ "BriefDescription": "UNC_U_CLOCKTICKS",
+ "EventName": "UNC_U_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "UBOX"
+ },
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
"UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.ENABLE",
+ "EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+ "EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
+ "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+ "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
+ "PublicDescription": "PHOLD cycles. Filter from source CoreID.",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
+ "PublicDescription": "Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
- "EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
- },
- {
- "BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+ "EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
"UMask": "0x8",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Monitor T0",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.CMC",
+ "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Monitor T1",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.UMC",
+ "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Other",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.TRAP",
+ "EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+ "UMask": "0x80",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Trap",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.OTHER",
+ "EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x40",
"Unit": "UBOX"
},
{
- "BriefDescription": "UNC_U_CLOCKTICKS",
- "Counter": "0,1",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+ "EventCode": "0x43",
+ "EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x20",
"Unit": "UBOX"
}
]
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
+ "Unit": "PCU"
+ },
+ {
+ "BriefDescription": "Package C State Residency - C1E",
+ "EventCode": "0x4E",
+ "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C7 State Residency",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
"PerPkg": "1",
+ "PublicDescription": "Ring GV with same final and initial frequency",
"Unit": "PCU"
},
{
- "BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_P_VR_HOT_CYCLES",
- "PerPkg": "1",
- "Unit": "PCU"
- },
- {
- "BriefDescription": "Package C State Residency - C1E",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+ "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
+ "EventCode": "0x79",
+ "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
+ "PublicDescription": "Ring GV with same final and initial frequency",
"Unit": "PCU"
},
{
- "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
- "Counter": "0,1,2,3",
- "EventCode": "0x79",
- "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+ "BriefDescription": "VR Hot",
+ "EventCode": "0x42",
+ "EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs",
"Unit": "PCU"
}
]
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
},
{
"BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.",
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.",
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.",
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
},
{
"BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
"PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.",
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.",
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.",
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.",
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.",
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xae",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Misses in ITLB that causes a page walk of any page size.",
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"PublicDescription": "ITLB misses that hit STLB (2M).",
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"PublicDescription": "ITLB misses that hit STLB (4K).",
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB of any page size.",
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"SampleAfterValue": "100003",
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.",
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.",
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.",
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
"PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.",
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"PublicDescription": "Number of DTLB page walker loads that hit in the L2.",
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY",
"SampleAfterValue": "2000003",
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
},
{
"BriefDescription": "Number of ITLB page walker hits in Memory",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "HSD25",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY",
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Count number of STLB flush attempts.",
projects / platform / kernel / linux-rpi.git / commitdiff