clk: renesas: r9a07g043: Add USB clocks/resets

Add clock/reset entries for USB PHY control, USB2.0 host and device.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index d54bccf..ea826f0 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -160,6 +160,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
                                0x570, 6),
        DEF_MOD("ssi3_sfr",     R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
                                0x570, 7),
+       DEF_MOD("usb0_host",    R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
+                               0x578, 0),
+       DEF_MOD("usb1_host",    R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
+                               0x578, 1),
+       DEF_MOD("usb0_func",    R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
+                               0x578, 2),
+       DEF_MOD("usb_pclk",     R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
+                               0x578, 3),
        DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
                                0x57c, 0),
        DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
@@ -206,6 +214,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
        DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
        DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
        DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
+       DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
+       DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
+       DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
+       DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
        DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
        DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
        DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),