clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK critical
authorBiju Das <biju.das.jz@bp.renesas.com>
Wed, 22 Sep 2021 11:24:04 +0000 (12:24 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 24 Sep 2021 13:11:05 +0000 (15:11 +0200)
Add IA55_CLK and DMAC_ACLK as critical clocks.

Previously it worked ok, because of a bug in clock status function
and the following patch in this series fixes the original bug.

Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions")
Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922112405.26413-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c

index 4c94b94..1490446 100644 (file)
@@ -186,6 +186,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 
 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
        MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
+       MOD_CLK_BASE + R9A07G044_IA55_CLK,
+       MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 };
 
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {