ARM: dts: exynos: Add cooling levels for Exynos5420 CPUs

On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and
12 steps for big core (700-1800 MHz). Add respective cooling cells.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 261d251..5c052d7 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -33,6 +33,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu1: cpu@1 {
@@ -42,6 +45,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu2: cpu@2 {
@@ -51,6 +57,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu3: cpu@3 {
@@ -60,6 +69,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu4: cpu@100 {
@@ -70,6 +82,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu5: cpu@101 {
@@ -79,6 +94,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu6: cpu@102 {
@@ -88,6 +106,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu7: cpu@103 {
@@ -97,6 +118,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
        };
 };