audio: correct the 958 clock setting after dd+ pass through

PD#166264: correct the 958 clock

Change-Id: I3961bc21e9d9c13973ecdbc0d944b5411750f377
Signed-off-by: Shen Liu <shen.liu@amlogic.com>
Signed-off-by: Shuai Li <shuai.li@amlogic.com>

diff --git a/sound/soc/amlogic/meson/spdif_dai.c b/sound/soc/amlogic/meson/spdif_dai.c
index 4fb604f..58990a6 100644 (file)
--- a/sound/soc/amlogic/meson/spdif_dai.c
+++ b/sound/soc/amlogic/meson/spdif_dai.c
@@ -115,11 +115,12 @@ void aml_spdif_play(int samesrc)
                        flag_samesrc = samesrc;
                        aml_set_spdif_clk(48000 * 512, samesrc);
                }
-               if (IEC958_mode_codec == 4 || IEC958_mode_codec == 5 ||
-               IEC958_mode_codec == 7 || IEC958_mode_codec == 8) {
-                       pr_info("set 4x audio clk for 958\n");
-                       div = 1;
-               } else if (samesrc) {
+               // if (IEC958_mode_codec == 4 || IEC958_mode_codec == 5 ||
+               // IEC958_mode_codec == 7 || IEC958_mode_codec == 8) {
+               //      pr_info("set 4x audio clk for 958\n");
+               //      div = 1;
+               // } else if (samesrc) {
+               if (samesrc) {
                        pr_debug("share the same clock\n");
                        div = 2;
                } else {