drm/i915: Remove framestart_delay sanitation

Now that we track framestart_delay in the crtc state with readout
and state checker support we can remove the explicit framestart_delay
sanitation code.

Also I'm not convinced reprogramming this while the pipe is running
is even valid. CHICKEN_TRANS (hsw+) and TRANS_CHICKEN2 (cpt+) docs
at least make no mention of double buffering which seems to imply
that live reprogramming is not supported. On older platforms
PIPECONF and PCH_TRANSCONF (ibx) are double buffered though, so
might be that we could do this on the older platforms. But doesn't
really make sense to special case old platforms for this.

So from now on if the BIOS has misprogrammed this we shall simply do
a full modeset at boot to fix it up. Such systems will of course lose
fastboot, but I think less code (and less uncertainty what
reprogramming this on a running pipe will even do) outweighs that.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220221110356.5532-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7b0a877..ad4a631 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9935,59 +9935,6 @@ static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
                (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
 }
 
-static void intel_sanitize_frame_start_delay(struct intel_crtc_state *crtc_state)
-{
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-
-       crtc_state->framestart_delay = 1;
-
-       if (DISPLAY_VER(dev_priv) >= 9 ||
-           IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
-               i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
-               u32 val;
-
-               if (transcoder_is_dsi(cpu_transcoder))
-                       return;
-
-               val = intel_de_read(dev_priv, reg);
-               val &= ~HSW_FRAME_START_DELAY_MASK;
-               val |= HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
-               intel_de_write(dev_priv, reg, val);
-       } else {
-               i915_reg_t reg = PIPECONF(cpu_transcoder);
-               u32 val;
-
-               val = intel_de_read(dev_priv, reg);
-               val &= ~PIPECONF_FRAME_START_DELAY_MASK;
-               val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
-               intel_de_write(dev_priv, reg, val);
-       }
-
-       if (!crtc_state->has_pch_encoder)
-               return;
-
-       if (HAS_PCH_IBX(dev_priv)) {
-               i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
-               u32 val;
-
-               val = intel_de_read(dev_priv, reg);
-               val &= ~TRANS_FRAME_START_DELAY_MASK;
-               val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
-               intel_de_write(dev_priv, reg, val);
-       } else {
-               enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc);
-               i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder);
-               u32 val;
-
-               val = intel_de_read(dev_priv, reg);
-               val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-               val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
-               intel_de_write(dev_priv, reg, val);
-       }
-}
-
 static void intel_sanitize_crtc(struct intel_crtc *crtc,
                                struct drm_modeset_acquire_ctx *ctx)
 {
@@ -9998,9 +9945,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
        if (crtc_state->hw.active) {
                struct intel_plane *plane;
 
-               /* Clear any frame start delays used for debugging left by the BIOS */
-               intel_sanitize_frame_start_delay(crtc_state);
-
                /* Disable everything but the primary plane */
                for_each_intel_plane_on_crtc(dev, crtc, plane) {
                        const struct intel_plane_state *plane_state =