Use CONFIG_ARCH_T4160 instead.
Signed-off-by: York Sun <york.sun@nxp.com>
config TARGET_T4160QDS
bool "Support T4160QDS"
+ select ARCH_T4160
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T4160RDB
bool "Support T4160RDB"
+ select ARCH_T4160
select SUPPORT_SPL
select PHYS_64BIT
config ARCH_T2081
bool
+config ARCH_T4160
+ bool
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
-obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
-obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
#endif
#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
+ defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
case 0x29:
case 0x2d:
case 0x2e:
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_PPC_T4080)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
defined(CONFIG_ARCH_T2081)
svr = get_svr();
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
+#elif defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {NONE, NONE, NONE, NONE,
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_PPC_T4080)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
-#if defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_ARCH_T4160)
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#elif defined(CONFIG_PPC_T4080)
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_PPC_T4080)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
defined(CONFIG_PPC_T4080)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o
-obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o
obj-$(CONFIG_ARCH_B4860) += b4860.o
CONFIG_PPC64BRIDGE
CONFIG_PPC_CLUSTER_START
CONFIG_PPC_SPINTABLE_COMPATIBLE
-CONFIG_PPC_T4160
CONFIG_PPC_T4240
CONFIG_PQ_MDS_PIB
CONFIG_PQ_MDS_PIB_ATM