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x86/amd: Add missing feature flag for fam15h models 10h-1fh processors
author
Andreas Herrmann
<andreas.herrmann3@amd.com>
Fri, 20 Jan 2012 16:38:23 +0000
(17:38 +0100)
committer
Ingo Molnar
<mingo@elte.hu>
Thu, 26 Jan 2012 11:06:38 +0000
(12:06 +0100)
That is the last one missing for those CPUs.
Others were recently added with commits
fb215366b3c7320ac25dca766a0152df16534932
(KVM: expose latest Intel cpu new features (BMI1/BMI2/FMA/AVX2) to guest)
and
commit
969df4b82904a30fef19a67398a0c854d223ea67
(x86: Report cpb and eff_freq_ro flags correctly)
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Link:
http://lkml.kernel.org/r/20120120163823.GC24508@alberich.amd.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/include/asm/cpufeature.h
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diff --git
a/arch/x86/include/asm/cpufeature.h
b/arch/x86/include/asm/cpufeature.h
index 17c5d4bdee5ed5124c7be91bf8d4ef73b39b7c2f..8d67d428b0f993f79031bb5f9702bd44adc8001a 100644
(file)
--- a/
arch/x86/include/asm/cpufeature.h
+++ b/
arch/x86/include/asm/cpufeature.h
@@
-159,6
+159,7
@@
#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */
#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */