platform/x86: intel_pmc_core: Fix TigerLake power gating status map

TigerLake's LPM power gating status register has errors in the bit-to-name
mapping as well as with the marked reserved bits according to the actual
implementation. Hence, update the right bit-to-name mapping and the
reserved bits in accordance with actual implementation.

Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David E. Box <david.e.box@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20201006224702.12697-3-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index ed9fdf7c8928cc692c5e2e3b835ffefeabab42a3..cf4006e08c699d7d5a20c70a1342d99bf7fbbd65 100644 (file)
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -426,30 +426,30 @@ static const struct pmc_bit_map tgl_clocksource_status_map[] = {
 };
 
 static const struct pmc_bit_map tgl_power_gating_status_map[] = {
-       {"SPI_PG_STS",                          BIT(2)},
-       {"xHCI_PG_STS",                         BIT(3)},
-       {"PCIe_Ctrller_A_PG_STS",               BIT(4)},
-       {"PCIe_Ctrller_B_PG_STS",               BIT(5)},
-       {"PCIe_Ctrller_C_PG_STS",               BIT(6)},
-       {"GBE_PG_STS",                          BIT(7)},
-       {"SATA_PG_STS",                         BIT(8)},
-       {"HDA0_PG_STS",                         BIT(9)},
-       {"HDA1_PG_STS",                         BIT(10)},
-       {"HDA2_PG_STS",                         BIT(11)},
-       {"HDA3_PG_STS",                         BIT(12)},
-       {"PCIe_Ctrller_D_PG_STS",               BIT(13)},
-       {"ISIO_PG_STS",                         BIT(14)},
-       {"SMB_PG_STS",                          BIT(16)},
-       {"ISH_PG_STS",                          BIT(17)},
-       {"ITH_PG_STS",                          BIT(19)},
-       {"SDX_PG_STS",                          BIT(20)},
-       {"xDCI_PG_STS",                         BIT(25)},
-       {"DCI_PG_STS",                          BIT(26)},
-       {"CSME0_PG_STS",                        BIT(27)},
-       {"CSME_KVM_PG_STS",                     BIT(28)},
-       {"CSME1_PG_STS",                        BIT(29)},
-       {"CSME_CLINK_PG_STS",                   BIT(30)},
-       {"CSME2_PG_STS",                        BIT(31)},
+       {"CSME_PG_STS",                         BIT(0)},
+       {"SATA_PG_STS",                         BIT(1)},
+       {"xHCI_PG_STS",                         BIT(2)},
+       {"UFSX2_PG_STS",                        BIT(3)},
+       {"OTG_PG_STS",                          BIT(5)},
+       {"SPA_PG_STS",                          BIT(6)},
+       {"SPB_PG_STS",                          BIT(7)},
+       {"SPC_PG_STS",                          BIT(8)},
+       {"SPD_PG_STS",                          BIT(9)},
+       {"SPE_PG_STS",                          BIT(10)},
+       {"SPF_PG_STS",                          BIT(11)},
+       {"LSX_PG_STS",                          BIT(13)},
+       {"P2SB_PG_STS",                         BIT(14)},
+       {"PSF_PG_STS",                          BIT(15)},
+       {"SBR_PG_STS",                          BIT(16)},
+       {"OPIDMI_PG_STS",                       BIT(17)},
+       {"THC0_PG_STS",                         BIT(18)},
+       {"THC1_PG_STS",                         BIT(19)},
+       {"GBETSN_PG_STS",                       BIT(20)},
+       {"GBE_PG_STS",                          BIT(21)},
+       {"LPSS_PG_STS",                         BIT(22)},
+       {"MMP_UFSX2_PG_STS",                    BIT(23)},
+       {"MMP_UFSX2B_PG_STS",                   BIT(24)},
+       {"FIA_PG_STS",                          BIT(25)},
        {}
 };