clk: samsung: exynosautov9: add cmu_fsys2 clock support

CMU_FSYS2 is responsible to control clocks of BLK_FSYS2 which includes
ufs and ethernet IPs. This patch adds some essential clocks to be
controlled by ethernet/ufs drivers instead of listing full clocks.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-8-chanho61.park@samsung.com

diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index aaa78b9..8c6ecd3 100644 (file)
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1067,6 +1067,73 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
        .clk_name               = "dout_clkcmu_core_bus",
 };
 
+/* ---- CMU_FSYS2 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
+#define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER     0x0600
+#define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER        0x0620
+#define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER        0x0610
+#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK      0x2098
+#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO        0x209c
+#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK      0x20a4
+#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO        0x20a8
+
+static const unsigned long fsys2_clk_regs[] __initconst = {
+       PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER,
+       PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER,
+       PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER,
+       CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK,
+       CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
+       CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK,
+       CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS2 */
+PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" };
+PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" };
+PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" };
+
+static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {
+       MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user",
+           mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1),
+       MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user",
+           mout_fsys2_ufs_embd_user_p,
+           PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1),
+       MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user",
+           mout_fsys2_ethernet_user_p,
+           PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {
+       GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk",
+            "mout_fsys2_ufs_embd_user",
+            CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21,
+            0, 0),
+       GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro",
+            "mout_fsys2_ufs_embd_user",
+            CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
+            21, 0, 0),
+       GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk",
+            "mout_fsys2_ufs_embd_user",
+            CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21,
+            0, 0),
+       GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro",
+            "mout_fsys2_ufs_embd_user",
+            CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
+            21, 0, 0),
+};
+
+static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
+       .mux_clks               = fsys2_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(fsys2_mux_clks),
+       .gate_clks              = fsys2_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(fsys2_gate_clks),
+       .nr_clk_ids             = FSYS2_NR_CLK,
+       .clk_regs               = fsys2_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(fsys2_clk_regs),
+       .clk_name               = "dout_clkcmu_fsys2_bus",
+};
+
 /* ---- CMU_PERIS ---------------------------------------------------------- */
 
 /* Register Offset definitions for CMU_PERIS (0x10020000) */
@@ -1133,6 +1200,8 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
                .compatible = "samsung,exynosautov9-cmu-core",
                .data = &core_cmu_info,
        }, {
+               .compatible = "samsung,exynosautov9-cmu-fsys2",
+               .data = &fsys2_cmu_info,
        }, {
                .compatible = "samsung,exynosautov9-cmu-peris",
                .data = &peris_cmu_info,